Fix Bugs

- Initial Z280 work caused some regression.

Source/HBIOS/Config/RCZ280_ext.asm

@@ -26,10 +26,14 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
 INTMODE		.SET	1
 ;
+Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
+;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)

Source/HBIOS/cfg_master.asm

@@ -42,6 +42,7 @@ Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
 N8_PPI0		.EQU	$80		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
 N8_PPI1		.EQU	$84		; N8: SECOND PARALLEL PORT REGISTERS BASE ADR

Source/HBIOS/cfg_rcz280.asm

@@ -37,6 +37,7 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;

Source/HBIOS/hbios.asm

@@ -427,10 +427,20 @@ HBX_BNKSEL1:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ;
 HBX_BNKCPY:
-#IF (INTMODE > 0)
-	;LD	A,I
+#IF (CPUFAM == CPU_Z280)
+	PUSH	IY
+	PUSH	BC
+	;LD	C,$00
+	LD	C,Z280_MSR
+	;LDCTL	IY,(C)
+	.DB	$FD,$ED,$66
+	POP	BC
+	PUSH	IY
 	DI
-	;PUSH	AF
+#ELSE
+	LD	A,I
+	DI
+	PUSH	AF
 #ENDIF
 	LD	(HBX_BC_SP),SP		; PUT STACK
 	LD	SP,HBX_TMPSTK		; ... IN HI MEM
@@ -461,9 +471,18 @@ HBX_BC_LAST:
 
 	LD	SP,$FFFF		; RESTORE STACK
 HBX_BC_SP	.EQU	$ - 2		; ... TO ORIGINAL VALUE
-#IF (INTMODE > 0)
-	;POP	AF
-	;JP	PO,$+4
+#IF (CPUFAM == CPU_Z280)
+	POP	IY
+	PUSH	BC
+	;LD	C,$00
+	LD	C,Z280_MSR
+	;LDCTL	(C),IY
+	.DB	$FD,$ED,$6E
+	POP	BC
+	POP	IY
+#ELSE
+	POP	AF
+	JP	PO,$+4
 	EI
 #ENDIF
 	RET
@@ -825,17 +844,19 @@ HB_START:
 	LD	SP,HBX_LOC		; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
 ;
 #IF (CPUFAM == CPU_Z280)
-	;LD	C,$12		; CACHE CONTROL REGISTER
-	;LD	HL,$0060	; DISABLE INSTRUCTION CACHE
-	;;LDCTL	(C),HL		; SET IT (8 BITS)
+	;;LD	C,$12			; CACHE CONTROL REGISTER
+	;LD	C,Z280_CCR		; CACHE CONTROL REGISTER
+	;LD	HL,$0060		; DISABLE INSTRUCTION CACHE
+	;;LDCTL	(C),HL			; SET IT (8 BITS)
 	;.DB	$ED,$6E
 	;;PCACHE			; PURGE ANY REMNANTS OF CACHE
 	;.DB	$ED,$65
 ;
-	LD	C,$02		; BUS TIMING AND CONTROL REGISTER
-	LD	HL,$0033	; 3 I/O WAIT STATES ADDED
-	;LD	HL,$00F3	; 3 I/O W/S & 3 INT ACK W/S
-	;LDCTL	(C),HL		; SET IT (8 BITS)
+	;LD	C,$02			; BUS TIMING AND CONTROL REGISTER
+	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REGISTER
+	LD	HL,$0033		; 3 I/O WAIT STATES ADDED
+	;LD	HL,$00F3		; 3 I/O W/S & 3 INT ACK W/S
+	;LDCTL	(C),HL			; SET IT (8 BITS)
 	.DB	$ED,$6E
 #ENDIF
 ;
@@ -969,6 +990,7 @@ HB_START:
 	LD	DE,0
 	LD	BC,$8000
 	CALL	HBX_BNKCPY
+	;DI
 ;
 ; TRANSITION TO HBIOS IN RAM BANK
 ;
@@ -1198,15 +1220,15 @@ HB_CPU2:
 ;
 #ENDIF
 ;
-#IF (CPUFAM == CPU_Z280)
-;
-	; Z280 PHI IS OSC / 2
-	LD	A,(CPUOSC / 2) / 1000000
-	LD	(CB_CPUMHZ),A
-	LD	DE,(CPUOSC / 2) / 1000
-	LD	(CB_CPUKHZ),DE
-;
-#ENDIF
+;#IF (CPUFAM == CPU_Z280)
+;;
+;	; Z280 PHI IS OSC / 2
+;	LD	A,(CPUOSC / 2) / 1000000
+;	LD	(CB_CPUMHZ),A
+;	LD	DE,(CPUOSC / 2) / 1000
+;	LD	(CB_CPUKHZ),DE
+;;
+;#ENDIF
 ;
 	DIAG(%00011111)
 ;
@@ -1224,6 +1246,31 @@ HB_CPU2:
 ;
 #ENDIF
 ;
+#IF (CPUFAM == CPU_Z280)
+;
+	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REG
+	;LDCTL	HL,(C)			; GET IT
+	.DB	$ED,$66
+	LD	A,L			; PUT IN A
+	AND	%00111100		; CLEAR DC AND I/O FIELDS
+	OR	Z280_INTWAIT << 6	; SET INT ACK WAIT STATES
+	OR	Z280_IOWAIT		; SET I/O WAIT STATES
+	LD	L,A			; BACK TO L
+	;LDCTL	(C),HL			; SET IT
+	.DB	$ED,$6E
+;
+	LD	C,Z280_BTIR		; BUS TIMING AND INIT REG
+	;LDCTL	HL,(C)			; GET IT
+	.DB	$ED,$66
+	LD	A,L			; PUT IN A
+	AND	%11110011		; CLEAR DC AND I/O FIELDS
+	OR	Z280_MEMWAIT << 2	; SET LOW MEM WAIT STATES
+	LD	L,A			; BACK TO L
+	;LDCTL	(C),HL			; SET IT
+	.DB	$ED,$6E
+;
+#ENDIF
+;
 #IF (INTMODE == 2)
 	; SETUP Z80 IVT AND INT MODE 2
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
@@ -1483,6 +1530,33 @@ HB_SPDTST:
 	CALL	PRTHEXBYTE
 #ENDIF
 ;
+#IF (CPUFAM == CPU_Z280)
+	CALL	PRTSTRD
+	.TEXT	", BUS @ $"
+	LD	C,Z280_BTIR		; BUS TIMING AND CTL REG
+	;LDCTL	HL,(C)			; GET IT
+	.DB	$ED,$66
+	LD	A,L			; MOVE TO A
+	AND	%00000011		; ISOLATE CS FIELD
+	LD	HL,(CB_CPUKHZ)		; GET CPU SPEED
+	CP	%00000001		; BUS @ 1/1
+	JR	Z,HB_Z280BUS		; GOT IT, SHOW IT
+	SRL	H			; DIVIDE
+	RR	L			; ... BY 2
+	CP	%00000000		; BUS @ 1/2
+	JR	Z,HB_Z280BUS		; GOT IT, SHOW IT
+	SRL	H                       ; DIVIDE
+	RR	L                       ; ... BY 2
+	CP	%00000010		; BUS @ 1/4
+	JR	Z,HB_Z280BUS		; GOT IT, SHOW IT
+	PRTS("???$")			; INVALID VALUE
+	JR	HB_Z280BUS1		; CONTINUE
+HB_Z280BUS:
+	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
+HB_Z280BUS1:
+	PRTS("MHz$")			; SUFFIX
+#ENDIF
+;
 ; DISPLAY CPU CONFIG
 ;
 	CALL	NEWLINE
@@ -1506,12 +1580,21 @@ HB_SPDTST:
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" I/O W/S$"
+#IF (CPUFAM == CPU_Z280)
+	CALL	PRTSTRD
+	.TEXT	", $"
+	LD	A,Z280_INTWAIT
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" INT W/S$"
+#ENDIF
 #IF (INTMODE > 0)
 	CALL	PRTSTRD
 	.TEXT	", INT MODE $"
 	LD	A,INTMODE
 	CALL	PRTDECB
 #ENDIF
+
 ;
 ; DISPLAY MEMORY CONFIG
 ;
@@ -1529,19 +1612,25 @@ HB_SPDTST:
 	CALL	NEWLINE
 	PRTS("Z280: $")
 	PRTS("MSR=$")
-	LD	C,$00			; MASTER STATUS REGISTER
+	LD	C,Z280_MSR		; MASTER STATUS REGISTER
 	;LDTCL	HL,(C)			; GET VALUE
 	.DB	$ED,$66
 	CALL	PRTHEXWORDHL
 	CALL	PC_SPACE
 	PRTS("BTCR=$")
-	LD	C,$02			; BUS TIMING AND CONTROL REGISTER
+	LD	C,Z280_BTCR		; BUS TIMING AND CONTROL REGISTER
+	;LDTCL	HL,(C)			; GET VALUE
+	.DB	$ED,$66
+	CALL	PRTHEXWORDHL
+	CALL	PC_SPACE
+	PRTS("BTIR=$")
+	LD	C,Z280_BTIR		; BUS TIMING AND CONTROL REGISTER
 	;LDTCL	HL,(C)			; GET VALUE
 	.DB	$ED,$66
 	CALL	PRTHEXWORDHL
 	CALL	PC_SPACE
 	PRTS("CCR=$")
-	LD	C,$12			; CACHE CONTROL REGISTER
+	LD	C,Z280_CCR		; CACHE CONTROL REGISTER
 	;LDTCL	HL,(C)			; GET VALUE
 	.DB	$ED,$66
 	CALL	PRTHEXWORDHL
@@ -2840,15 +2929,34 @@ SYS_SETSECS:
 ;
 SYS_PEEK:
 #IF (INTMODE == 1)
-	;LD	A,I
+  #IF (CPUFAM == CPU_Z280)
+	PUSH	IY
+	;LD	C,$00
+	LD	C,Z280_MSR
+	;LDCTL	IY,(C)
+	.DB	$FD,$ED,$66
+	PUSH	IY
 	DI
-	;PUSH	AF
+  #ELSE
+	LD	A,I
+	DI
+	PUSH	AF
+  #ENDIF
 #ENDIF
 	CALL	HBX_PEEK		; IMPLEMENTED IN PROXY
 #IF (INTMODE == 1)
-	;POP	AF
-	;JP	PO,$+4
+  #IF (CPUFAM == CPU_Z280)
+	;LD	C,$00
+	LD	C,Z280_MSR
+	POP	IY
+	;LDCTL	(C),IY
+	.DB	$FD,$ED,$6E
+	POP	IY
+  #ELSE
+	POP	AF
+	JP	PO,$+4
 	EI
+  #ENDIF
 #ENDIF
 	XOR	A
 	RET
@@ -2862,15 +2970,96 @@ SYS_PEEK:
 ;
 SYS_POKE:
 #IF (INTMODE == 1)
+
+	;EI
+	;
+	;LD	C,$00
+	;.DB	$ED,$66
+	;CALL	PC_SPACE
+	;CALL	PRTHEXWORDHL
+	;
+	;CALL	PC_SPACE
 	;LD	A,I
-	DI
 	;PUSH	AF
+	;POP	HL
+	;CALL	PRTHEXWORDHL
+	;
+	;DI
+	;
+	;LD	C,$00
+	;.DB	$ED,$66
+	;CALL	PC_SPACE
+	;CALL	PRTHEXWORDHL
+	;
+	;CALL	PC_SPACE
+	;LD	A,I
+	;PUSH	AF
+	;POP	HL
+	;CALL	PRTHEXWORDHL
+	;
+	;
+	;
+	;
+	;OUT	(DIAGPORT),A
+	;DI
+	;HALT
+	;
+	;;PUSH	HL
+	;;;LD	C,$00
+	;;LD	C,Z280_MSR
+	;;LDCTL	HL,(C)
+	;;BIT	5,L
+	;;POP	HL
+	;;PUSH	AF
+	;;DI
+	;
+	;;POP	AF
+	;;JP	Z,$+4
+	;;EI
+	;
+	;
+	;
+	;;PUSH	IY
+	;;;LD	C,$00
+	;;LD	C,Z280_MSR
+	;;LDCTL	IY,(C)
+	;;PUSH	IY
+	;;DI
+	;
+	;;;LD	C,$00
+	;;LD	C,Z280_MSR
+	;;POP	IY
+	;;LDCTL	(C),IY
+	;;POP	IY
+
+  #IF (CPUFAM == CPU_Z280)
+	PUSH	IY
+	;LD	C,$00
+	LD	C,Z280_MSR
+	;LDCTL	IY,(C)
+	.DB	$FD,$ED,$66
+	PUSH	IY
+	DI
+  #ELSE
+	LD	A,I
+	DI
+	PUSH	AF
+  #ENDIF
 #ENDIF
 	CALL	HBX_POKE		; IMPLEMENTED IN PROXY
 #IF (INTMODE == 1)
-	;POP	AF
-	;JP	PO,$+4
+  #IF (CPUFAM == CPU_Z280)
+	;LD	C,$00
+	LD	C,Z280_MSR
+	POP	IY
+	;LDCTL	(C),IY
+	.DB	$FD,$ED,$6E
+	POP	IY
+  #ELSE
+	POP	AF
+	JP	PO,$+4
 	EI
+  #ENDIF
 #ENDIF
 	XOR	A
 	RET

Source/HBIOS/std.asm

@@ -330,6 +330,9 @@ FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
   #IF (CPUFAM == CPU_Z180)
     #INCLUDE "z180.inc"
   #ENDIF
+  #IF (CPUFAM == CPU_Z280)
+    #INCLUDE "z280.inc"
+  #ENDIF
 #ENDIF
 ;
 ; SETUP DEFAULT CPU SPEED VALUES
@@ -345,6 +348,9 @@ CPUKHZ		.SET	CPUKHZ / 2	; ADJUST FOR HALF SPEED OPERATION
 CPUKHZ		.SET	CPUKHZ * 2	; ADJUST FOR DOUBLE SPEED OPERATION
     #ENDIF
   #ENDIF
+  #IF (CPUFAM == CPU_Z280)
+CPUKHZ		.SET	CPUKHZ / 2	; Z180 PHI IS ALWAYS 1/2 OSC
+  #ENDIF
 #ENDIF
 ;
 CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN MHZ

Source/HBIOS/z280.inc

@@ -0,0 +1,13 @@
+;
+; Z280 REGISTERS
+;
+Z280_MSR	.EQU	$00	; MASTER STATUS REG
+Z280_ISR	.EQU	$16	; INTERRUPT STATUS REG
+Z280_VPR	.EQU	$06	; INT/TRAP VECT PTR REG
+Z280_IOPR	.EQU	$08	; I/O PAGE REG
+Z280_BTIR	.EQU	$FF	; BUS TIMING & INIT REG
+Z280_BTCR	.EQU	$02	; BUS TIMING & CONTROL REG
+Z280_SLR	.EQU	$04	; STACK LIMIT REG
+Z280_TCR	.EQU	$10	; TRAP CONTROL REG
+Z280_CCR	.EQU	$12	; CACHE CONTROL REG
+Z280_LAR	.EQU	$14	; LOCAL ADDRESS REG

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.19"
+#DEFINE BIOSVER	"3.1.1-pre.20"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.19"
+	db	"3.1.1-pre.20"
 	endm