diff --git a/Source/HBIOS/asci.asm b/Source/HBIOS/asci.asm
index dc05caba..ec0a9763 100644
--- a/Source/HBIOS/asci.asm
+++ b/Source/HBIOS/asci.asm
@@ -232,6 +232,10 @@ ASCI_INTRCV1:
 	ADD	A,8			; BUMP TO RDR PORT
 	LD	C,A			; PUT IN C, B IS STILL ZERO
 	IN	A,(C)			; READ PORT
+  #IF (ASCIBOOT != 0)
+	CP	ASCIBOOT		; REBOOT REQUEST?
+	JP	Z,SYS_RESCOLD		; IF SO, DO IT, NO RETURN
+  #ENDIF
 	LD	B,A			; SAVE BYTE READ
 	LD	L,(IY+6)		; SET HL TO
 	LD	H,(IY+7)		; ... START OF BUFFER STRUCT
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index a7d8b686..6d0bbb3d 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -91,6 +91,7 @@ UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index a1a27eff..43eb2c88 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -112,6 +112,7 @@ ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_STD	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 43b66c08..5072ad1b 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -138,6 +138,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
@@ -162,6 +163,7 @@ ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 5a09e7d4..2e3f672a 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -106,6 +106,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index acf639ed..0d19eb43 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -109,6 +109,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 73cf6316..b12a12cf 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -108,6 +108,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
@@ -117,6 +118,7 @@ ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 7918fc84..09e953ca 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -134,6 +134,7 @@ ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 9db69706..2aa7448b 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -123,6 +123,7 @@ ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index e3ec540e..1fb43200 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -107,6 +107,7 @@ ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index ed0aacf8..e63e655d 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -103,6 +103,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
@@ -112,6 +113,7 @@ ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 5a013853..8e7e323a 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -267,6 +267,10 @@ SIO_INTRCV1:
 	; RECEIVE CHARACTER INTO BUFFER
 	LD	C,(IY+4)		; DATA PORT TO C
 	IN	A,(C)			; READ PORT
+  #IF (SIOBOOT != 0)
+	CP	SIOBOOT		; REBOOT REQUEST?
+	JP	Z,SYS_RESCOLD		; IF SO, DO IT, NO RETURN
+  #ENDIF
 	LD	B,A			; SAVE BYTE READ
 	LD	L,(IY+7)		; SET HL TO
 	LD	H,(IY+8)		; ... START OF BUFFER STRUCT
diff --git a/Source/Images/d_bp/u0/UNZIP154.COM b/Source/Images/d_bp/u0/UNZIP154.COM
new file mode 100644
index 00000000..f0572630
Binary files /dev/null and b/Source/Images/d_bp/u0/UNZIP154.COM differ
diff --git a/Source/Images/d_bp/u0/UNZIP186.COM b/Source/Images/d_bp/u0/UNZIP186.COM
new file mode 100644
index 00000000..c750ff52
Binary files /dev/null and b/Source/Images/d_bp/u0/UNZIP186.COM differ
diff --git a/Source/Images/d_cpm22/u0/UNZIP154.COM b/Source/Images/d_cpm22/u0/UNZIP154.COM
new file mode 100644
index 00000000..f0572630
Binary files /dev/null and b/Source/Images/d_cpm22/u0/UNZIP154.COM differ
diff --git a/Source/Images/d_cpm22/u0/UNZIP186.COM b/Source/Images/d_cpm22/u0/UNZIP186.COM
new file mode 100644
index 00000000..c750ff52
Binary files /dev/null and b/Source/Images/d_cpm22/u0/UNZIP186.COM differ
diff --git a/Source/Images/d_zsdos/u0/UNZIP154.COM b/Source/Images/d_zsdos/u0/UNZIP154.COM
new file mode 100644
index 00000000..f0572630
Binary files /dev/null and b/Source/Images/d_zsdos/u0/UNZIP154.COM differ
diff --git a/Source/Images/d_zsdos/u0/UNZIP186.COM b/Source/Images/d_zsdos/u0/UNZIP186.COM
new file mode 100644
index 00000000..c750ff52
Binary files /dev/null and b/Source/Images/d_zsdos/u0/UNZIP186.COM differ
diff --git a/Source/RomDsk/ROM_1024KB/UNZIP154.COM b/Source/RomDsk/ROM_1024KB/UNZIP154.COM
new file mode 100644
index 00000000..f0572630
Binary files /dev/null and b/Source/RomDsk/ROM_1024KB/UNZIP154.COM differ
diff --git a/Source/RomDsk/ROM_1024KB/UNZIP186.COM b/Source/RomDsk/ROM_1024KB/UNZIP186.COM
new file mode 100644
index 00000000..c750ff52
Binary files /dev/null and b/Source/RomDsk/ROM_1024KB/UNZIP186.COM differ
diff --git a/Source/ver.inc b/Source/ver.inc
index 05bb4404..3115b8e7 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.71"
+#DEFINE BIOSVER	"3.1.1-pre.72"
diff --git a/Source/ver.lib b/Source/ver.lib
index 999bbaf4..676093af 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.71"
+	db	"3.1.1-pre.72"
 	endm