mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Reintegrate wbw -> trunk
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@@ -12,29 +12,28 @@ UART0_DIV .EQU (1843200 / (16 * BAUDRATE))
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; B: FUNCTION (IN)
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; C: CHARACTER (IN/OUT)
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; E: DEVICE/UNIT (IN)
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;
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;
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;
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UART_DISPATCH:
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#IF (PLATFORM == PLT_N8)
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LD A,C ; GET DEVICE/UNIT
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AND $0F ; ISOLATE UNIT
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JR Z,UART0
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JP Z,UART0
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DEC A
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JR Z,UART1
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JP Z,UART1
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CALL PANIC
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#ENDIF
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;
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UART0:
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; LD C,E ; FIX: COMPAT W/OLD DRIVERS, GET CHAR INTO C
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LD A,B ; GET REQUESTED FUNCTION
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AND $0F ; ISOLATE SUB-FUNCTION
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JR Z,UART0_IN
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JP Z,UART0_IN
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DEC A
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JR Z,UART0_OUT
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JP Z,UART0_OUT
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DEC A
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JR Z,UART0_IST
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JP Z,UART0_IST
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DEC A
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JR Z,UART0_OST
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JP Z,UART0_OST
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CALL PANIC
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;
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;
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@@ -42,14 +41,49 @@ UART0:
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UART_INIT:
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#IF (PLATFORM == PLT_N8)
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; ASCI0
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PRTS("ASCI0: IO=0x$")
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LD A,CPU_TDR0
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CALL PRTHEXBYTE
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CALL PC_COMMA
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LD A,CPU_RDR0
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CALL PRTHEXBYTE
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PRTS(" BAUD=$")
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#IF ((BAUDRATE / 100) > 0)
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LD HL,BAUDRATE / 100
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CALL PRTDEC
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#ENDIF
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#IF ((BAUDRATE % 100) < 10)
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PRTC("0")
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#ENDIF
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LD HL,BAUDRATE % 100
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CALL PRTDEC
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LD A,66H
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OUT0 (CPU_ASEXT0),A
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LD A,64H
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OUT0 (CPU_CNTLA0),A
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LD A,Z180_CNTLB0
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OUT0 (CPU_CNTLB0),A
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; ASCI1
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CALL NEWLINE
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PRTS("ASCI1: IO=0x$")
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LD A,CPU_TDR1
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CALL PRTHEXBYTE
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CALL PC_COMMA
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LD A,CPU_RDR1
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CALL PRTHEXBYTE
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PRTS(" BAUD=$")
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#IF ((BAUDRATE / 100) > 0)
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LD HL,BAUDRATE / 100
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CALL PRTDEC
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#ENDIF
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#IF ((BAUDRATE % 100) < 10)
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PRTC("0")
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#ENDIF
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LD HL,BAUDRATE % 100
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CALL PRTDEC
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LD A,66H
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OUT0 (CPU_ASEXT1),A
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LD A,64H
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@@ -57,6 +91,22 @@ UART_INIT:
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LD A,Z180_CNTLB1
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OUT0 (CPU_CNTLB1),A
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#ELSE
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PRTS("UART0: IO=0x$")
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LD A,SIO_BASE
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CALL PRTHEXBYTE
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PRTS(" BAUD=$")
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#IF ((BAUDRATE / 100) > 0)
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LD HL,BAUDRATE / 100
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CALL PRTDEC
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#ENDIF
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#IF ((BAUDRATE % 100) < 10)
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PRTC("0")
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#ENDIF
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LD HL,BAUDRATE % 100
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CALL PRTDEC
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CALL PC_SPACE
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LD A,80H
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OUT (SIO_LCR),A ; DLAB ON
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LD A,UART0_DIV
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@@ -65,8 +115,9 @@ UART_INIT:
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OUT (SIO_DLM),A ; SET DIVISOR (MS)
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LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
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#IF (UARTAFC)
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PRTS(" AFC$")
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LD A,$55 ; TEST VALUE
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OUT (SIO_SCR),A ; SET SCRATCH REG TO TEST VALUE
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LD A,0BFH
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@@ -76,12 +127,12 @@ UART_INIT:
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JR NZ,UART_AFC1 ; NZ, HAVE EFR, DO IT
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SET 5,B ; ENABLE AUTO FLOW CONTROL
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JR UART_AFC2
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UART_AFC1:
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UART_AFC1:
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LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
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OUT (SIO_EFR),A ; SAVE IT
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UART_AFC2:
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#ENDIF
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LD A,03H
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OUT (SIO_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
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@@ -89,8 +140,10 @@ UART_AFC2:
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OUT (SIO_MCR),A ; SAVE IT
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#IF (UARTFIFO)
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LD A,07H ; ENABLE AND RESET FIFOS
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OUT (SIO_FCR),A
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; LD A,07H ; ENABLE AND RESET FIFOS
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LD A,01H ; ENABLE AND RESET FIFOS
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OUT (SIO_FCR),A ; ENABLE FIFOS
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PRTS(" FIFO$")
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#ENDIF
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#ENDIF
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@@ -103,7 +156,7 @@ UART0_IN:
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OR A
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JR Z,UART0_IN
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#IF (PLATFORM == PLT_N8)
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IN0 A,(CPU_RDR0) ; READ THE CHAR FROM THE UART
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IN0 A,(CPU_RDR0) ; READ THE CHAR FROM THE UART
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#ELSE
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IN A,(SIO_RBR) ; READ THE CHAR FROM THE UART
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#ENDIF
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@@ -118,7 +171,7 @@ UART0_IST:
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IN0 A,(CPU_STAT0)
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AND 70H ; PARITY, FRAMING, OR OVERRUN ERROR
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JR Z,UART0_IST1 ; ALL IS WELL, CHECK FOR DATA
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; CLEAR ERROR(S) OR NOTHING FURTHER CAN BE RECEIVED!!!
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IN0 A,(CPU_CNTLA0)
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RES 3,A ; CLEAR EFR (ERROR FLAG RESET)
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@@ -126,7 +179,7 @@ UART0_IST:
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UART0_IST1: ; CHECK FOR STAT0.RDRF (DATA READY)
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IN0 A,(CPU_STAT0) ; READ LINE STATUS REGISTER
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AND $80 ; TEST IF DATA IN RECEIVE BUFFER
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AND $80 ; TEST IF DATA IN RECEIVE BUFFER
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#ELSE
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IN A,(SIO_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; TEST IF DATA IN RECEIVE BUFFER
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@@ -196,7 +249,7 @@ UART1_IST:
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IN0 A,(CPU_STAT1)
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AND 70H ; PARITY, FRAMING, OR OVERRUN ERROR
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JR Z,UART1_IST1 ; ALL IS WELL, CHECK FOR DATA
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; CLEAR ERROR(S) OR NOTHING FURTHER CAN BE RECEIVED!!!
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IN0 A,(CPU_CNTLA1)
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RES 3,A ; CLEAR EFR (ERROR FLAG RESET)
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@@ -204,7 +257,7 @@ UART1_IST:
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UART1_IST1: ; CHECK FOR STAT0.RDRF (DATA READY)
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IN0 A,(CPU_STAT1) ; READ LINE STATUS REGISTER
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AND $80 ; TEST IF DATA IN RECEIVE BUFFER
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AND $80 ; TEST IF DATA IN RECEIVE BUFFER
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL CHAR READY, A = 1
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