Preliminary Support for ROMless Booting

Nhyodyne Sound Support

Doc/ChangeLog.txt

@@ -60,6 +60,8 @@ Version 3.1.1
 - D?T: Substantial update to TastyBasic incuding a .COM executable
 - PMS: Added VGM audio file player
 - WBW: ZPMLDR and ZPM3 fixes, credit to Lars Nelson for finding ZPM3 source!
+- DDW: Add support for MBC sound card
+- WBW: Add support for "romless" booting
 
 Version 3.1
 -----------

ReadMe.md

@@ -3,7 +3,7 @@
 ## Z80/Z180 System Software
 
 Version 3.1 Pre-release  
-02 Feb 2022
+28 Feb 2022
 
 Wayne Warthen <wwarthen@gmail.com>
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Getting Started
 Wayne Warthen (mailto:wwarthen@gmail.com)
-02 Feb 2022
+28 Feb 2022
 
 
 
@@ -17,7 +17,7 @@ RomWBW
 Z80/Z180 System Software
 
 Version 3.1 Pre-release
-02 Feb 2022
+28 Feb 2022
 
 Wayne Warthen wwarthen@gmail.com
 

Source/Apps/Test/2piotst/2piotst.mac

@@ -0,0 +1,567 @@
+; 24.9.2018 PMS (b1ackmai1er)
+; Modified version for ECB-ZILOG PERIPHERALS BOARD - TEST 2 PIO's
+; 01.11.2011 WKA
+; Assembler M80
+; ECB-4PIO
+; Testprogramm f<>r die I/O-Karte ECB-4PIO in Z80-Mnemonics
+
+	PAGE 	72
+	.Z80
+	ASEG
+	ORG 	100H
+;
+;CP/M-ADDRESSES
+;* * * * * * * 
+;
+BOOT	EQU 0		;WARMBOOT CP/M
+BDOS	EQU 5		;ENTRY BDOS
+NMI	EQU 66H		;Error-ROUTINE
+;
+;CONSOLE-CODES
+;* * * * * * *
+;
+EOT	EQU 4		;END OF TEXT
+BS	EQU 8		;BACKSPACE
+TAB	EQU 9		;TABULATOR
+LF	EQU 0AH		;LINE-FEED
+CR	EQU 0DH		;CARRIAGE-RETURN
+FF	EQU 0CH		;FORM-FEED
+ESC	EQU 1BH		;ESCAPE
+CTRLC	EQU 'C'-40H	;CONTROL-C
+CTRLW	EQU 'W'-40H	;CONTROL-W
+CTRLX	EQU 'X'-40H	;CONTROL-X
+CTRLY	EQU 'Y'-40H	;CONTROL-Y
+CTRLZ	EQU 'Z'-40H	;CONTROL-Z
+;
+BASE 	EQU 0B8H 	; 4 DIL-SCHALTER
+;
+PIO0AD	EQU BASE+0 	; PIO 0 A DATEN
+PIO0AC	EQU BASE+2 	; PIO 0 A CONTROL
+PIO0BD	EQU BASE+1 	; PIO 0 B DATEN
+PIO0BC	EQU BASE+3 	; PIO 0 B CONTROL
+;
+PIO1AD	EQU BASE+4 	; PIO 1 A DATEN
+PIO1AC	EQU BASE+6 	; PIO 1 A CONTROL
+PIO1BD	EQU BASE+5 	; PIO 1 B DATEN
+PIO1BC	EQU BASE+7 	; PIO 1 B CONTROL
+;
+MAIN:	LD	DE,PIO_SRTMSG
+	CALL	PSTRIN
+;
+	LD	DE,INI_MSG
+	CALL	PSTRIN
+	CALL	INIT
+;
+	LD	DE,PIO0ADW	;PIO0 A
+	CALL	PSTRIN
+	LD	A,55H
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO0AD),A
+	IN	A,(PIO0AD)
+	PUSH	AF
+;
+	LD	DE,PIO0ADR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO0ADW
+	CALL	PSTRIN
+	LD	A,0AAH
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO0AD),A
+	IN	A,(PIO0AD)
+	PUSH	AF
+;
+	LD	DE,PIO0ADR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO0BDW	;PIO0 B
+	CALL	PSTRIN
+	LD	A,55H
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO0BD),A
+	IN	A,(PIO0BD)
+	PUSH	AF
+;
+	LD	DE,PIO0BDR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO0BDW
+	CALL	PSTRIN
+	LD	A,0AAH
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO0BD),A
+	IN	A,(PIO0BD)
+	PUSH	AF
+;
+	LD	DE,PIO0BDR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO1ADW	;PIO1 A
+	CALL	PSTRIN
+	LD	A,55H
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO1AD),A
+	IN	A,(PIO1AD)
+	PUSH	AF
+;
+	LD	DE,PIO1ADR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO1ADW
+	CALL	PSTRIN
+	LD	A,0AAH
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO1AD),A
+	IN	A,(PIO1AD)
+	PUSH	AF
+;
+	LD	DE,PIO1ADR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO1BDW	;PIO1 B
+	CALL	PSTRIN
+	LD	A,55H
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO1BD),A
+	IN	A,(PIO1BD)
+	PUSH	AF
+;
+	LD	DE,PIO1BDR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO1BDW
+	CALL	PSTRIN
+	LD	A,0AAH
+	PUSH	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+ 	CALL	PSTRIN
+	POP	AF
+	OUT	(PIO1BD),A
+	IN	A,(PIO1BD)
+	PUSH	AF
+;
+	LD	DE,PIO1BDR
+	CALL	PSTRIN
+	POP	AF
+	CALL	OUTB
+	LD	DE,LINE_E
+	CALL	PSTRIN
+;
+	LD	DE,PIO_ENDMSG
+	CALL	PSTRIN
+	JP	BOOT
+;
+;==========================================================================
+INIT:	LD 	HL,PIO0T	; PIO0 INITITALISIEREN
+	CALL 	INITX
+        LD 	HL,PIO1T 	; PIO1 INITITALISIEREN
+        CALL 	INITX
+	RET
+;
+INITX:	LD 	A,(HL) 		; BYTE-ANZAHL
+	OR 	A
+	RET 	Z
+	LD 	B,A		; Port-Adresse nach C
+        INC 	HL
+        LD 	C,(HL)
+        INC 	HL
+        OTIR
+        JR 	INITX
+;
+PIO0T:	DEFB 05 		; 5 BYTE ZUM PIO 0 A CONTROL
+	DEFB PIO0AC
+        DEFB 00000011B 		; DIS-INT
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 11001111B 		; BETR.ART BIT EIN/AUSG.
+        DEFB 00000000B 		; ALLES AUSG.
+        DEFB 01 		; 1 BYTE ZUM PIO 0 A DATEN
+	DEFB PIO0AD
+        DEFB 00000000B		; DATEN "LOW"
+;
+        DEFB 05 		; 5 BYTE ZUM PIO 0 B CONTROL
+	DEFB PIO0BC
+        DEFB 00000011B 		; DIS-INT
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 01001111B		; BETR.ART BYTE EINGABE
+        DEFB 11001111B 		; BETR.ART BIT EIN/AUSG.
+        DEFB 00000000B 		; ALLES AUSG.
+        DEFB 01 		; 1 BYTE ZUM PIO 0 B DATEN
+	DEFB PIO0BD
+        DEFB 00000000B		; DATEN "LOW"
+        DEFB 0 			; ENDE PIO 0 B -TABELLE
+;
+PIO1T:	DEFB 05 		; 5 BYTE ZUM PIO 1 A CONTROL
+	DEFB PIO1AC
+        DEFB 00000011B 		; DIS-INT
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 11001111B 		; BETR.ART BIT EIN/AUSG.
+        DEFB 00000000B 		; ALLES AUSG.
+        DEFB 01 		; 1 BYTE ZUM PIO 1 A DATEN
+	DEFB PIO1AD
+        DEFB 00000000B		; DATEN "LOW"
+;
+        DEFB 05 		; 5 BYTE ZUM PIO 1 B CONTROL
+	DEFB PIO1BC
+        DEFB 00000011B 		; DIS-INT
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 01001111B 		; BETR.ART BYTE EINGABE
+        DEFB 11001111B 		; BETR.ART BIT EIN/AUSG.
+        DEFB 00000000B 		; ALLES AUSG.
+        DEFB 01 		; 1 BYTE ZUM PIO 1 B DATEN
+	DEFB PIO1BD
+        DEFB 00000000B		; DATEN "LOW"
+        DEFB 0 			; ENDE PIO 1 B -TABELLE
+;
+;==========================================================================
+;
+;Output on Screen
+;****************
+;
+PRBS:	LD E,BS
+	CALL PCHAR
+	RET
+;
+;Output CR+LF on Screen
+;**********************
+;
+CRLF:	LD E,CR
+	CALL PCHAR
+	LD E,LF
+	CALL PCHAR
+	RET
+;
+;Output ASCII-Character
+;**********************
+;
+PRINP:	PUSH AF
+	LD E,A
+	CALL PCHAR
+	POP AF
+	RET;
+;
+;CALL BDOS with Register Save
+;****************************
+;
+INCHA:	LD C,1		;INPUT CHARACTER TO A
+	JR BDO
+PCHAR:	LD C,2		;PRINT CHARACTER IN E
+	JR BDO
+PSTRIN:	LD C,9		;PRINT STRING
+	JR BDO
+INBUFF:	LD C,10		;READ CONSOLE-BUFFER
+	JR BDO
+CSTS:	LD C,11		;CONSOLE-STATUS
+	JR BDO
+OPEN:	LD C,15		;OPEN FILE
+	JR BDO
+CLOSE:	LD C,16		;CLOSE FILE
+	JR BDO
+DELETE:	LD C,19		;DELETE FILE
+	JR BDO
+READS:	LD C,20		;READ SEEK
+	JR BDO
+WRITES:	LD C,21		;WRITE SEEK
+	JR BDO
+MAKE:	LD C,22		;MAKE FILE
+	JR BDO
+SETDMA:	LD C,26		;SET DMA-ADDRESS
+BDO:	PUSH HL
+	PUSH DE
+	PUSH BC
+	PUSH IX
+	PUSH IY
+	CALL BDOS
+	POP IY
+	POP IX
+	POP BC
+	POP DE
+	POP HL
+	RET
+;
+;DIRECT CONSOLE INPUT
+;********************
+;
+INDCON:	CALL INDCOX
+	CP 0
+	JR Z,INDCON
+	RET
+;
+INDCOX:	LD C,6		;Code for Direct Console Input
+	LD E,0FFH	;Code for Input
+	PUSH HL
+	PUSH DE
+	PUSH BC
+	PUSH IX
+	PUSH IY
+	CALL BDOS
+	POP IY
+	POP IX
+	POP BC
+	POP DE
+	POP HL
+	RET
+;
+;
+;Output WORD
+;***********
+;
+;PARAMETER: Entry WORD IN HL
+;*********
+;
+OUTW:	LD A,H
+	CALL OUTB
+	LD A,L
+	CALL OUTB
+	RET
+;
+;Output BYTE
+;***********
+;
+;PARAMETER: Entry BYTE IN A
+;*********
+;
+OUTB:	PUSH AF
+	RRCA
+	RRCA
+	RRCA
+	RRCA
+	AND 0FH
+	CALL HBTHE	;Change Half-BYTE
+	POP AF
+	AND 0FH
+	CALL HBTHE
+	RET
+;
+;Output HALF-BYTE
+;****************
+;
+;PARAMETER: Entry Half-BYTE IN A (BIT 0 - 3)
+;*********
+;
+HBTHE:	CP 0AH
+	JR C,HBTHE1
+	ADD A,7		;Character to Letter
+HBTHE1:	ADD A,30H
+	LD E,A
+	CALL PCHAR
+	RET
+;
+;Input ADDRESS
+;*************
+;
+;PARAMETER: Exit with ADDRESS IN HL
+;*********
+;
+INADR:	LD HL,0
+INADR1:	CALL INCHAR	;Input TETRADE
+	LD D,A
+	CALL INBYT1	;IN HEXA
+	RET C		;END OF Input
+	ADD HL,HL
+	ADD HL,HL
+	ADD HL,HL
+	ADD HL,HL
+	OR L
+	LD L,A
+	JR INADR1	;New Key
+;
+;
+;Input BYTE
+;**********
+;
+;PARAMTER: Exit with BYTE IN A
+;********
+;
+INBYT:	CALL INADR
+	LD A,L
+	RET
+;
+;Input of one TETRADE to A (BIT 0-3)
+;************************************
+;
+INBYT1:	SUB '0'
+	RET C
+	CP 'G'-30H
+	JR NC,INBYT3	;Error
+	CP ':'-30H
+	JR C,INBYT2
+	CP 'A'-30H
+	JR C,INBYT3	;Error
+	SUB 7
+INBYT2:	OR A
+	RET
+;
+INBYT3:	SCF
+	RET
+;
+;Input ASCII-Character to A
+;**************************
+;
+INCON:	CALL INDCON	;Input ASCII-Character to A
+	CP CTRLC	;TEST CONTROL-C
+	JP Z,QUIT
+	CP CTRLX	;TEST CONTROL-X
+	JR Z,INCHA1
+	CP CTRLW	;TEST CONTROL-W
+	JR Z,INCHA3
+	CP CTRLY	;TEST CONTROL-Y
+	JR Z,INCHA2
+	CP BS
+	RET Z
+	CP CR
+	RET Z
+	CP ' '
+	JR C,INCON
+	JR INCH1
+;
+INCHAR:	CALL INCHA	;Input ASCII-Character to A
+	CP CTRLC	;TEST CONTROL-C
+	JR Z,QUIT
+	CP CTRLX	;TEST CONTROL-X
+	JR Z,INCHA1
+	CP CTRLW	;TEST CONTROL-W
+	JR Z,INCHA3
+	CP CTRLY	;TEST CONTROL-Y
+	JR Z,INCHA2
+	CP BS
+	RET Z
+	CP CR
+	RET Z
+	CP ' '
+	JR C,INCHAR	;Input invalied
+;
+INCH1:	CP 'A'
+	RET C		;Character ok
+;
+	RES 5,A		;lower case -> upper case
+	RET
+INCHA1:	POP HL
+	LD E,FF
+	CALL PCHAR	;Clear screen
+	JP GOON
+INCHA2:	POP HL
+	LD E,FF
+	CALL PCHAR	;Clear screen
+	JP GOON
+INCHA3:	LD E,FF
+	CALL PCHAR
+	RET
+;
+;ABBRUCH DER BEARBEITUNG
+;***********************
+;
+COMPLT:	LD DE,TCOMP
+	CALL PSTRIN
+	JP GOON
+QUIT:	CALL CRLF
+	LD DE,TQUIT
+	JR FINIS
+INTTIM:	POP DE		;STACK OK
+;	CALL DESAK
+	LD DE,TNMIAB
+	CALL PSTRIN
+	LD DE,MAIN	;NEW ADDRESS
+	PUSH DE
+	RETN
+FINIS:	CALL PSTRIN	;AT BDOS-ERROR
+GOON:
+	JP BOOT
+;
+;
+;TEXT-Messages
+;*************
+;
+TCOMP:	DEFB ESC,21,0,14H,ESC,23,0
+	DEFM 'Function complete !!$'
+TQUIT:	DEFB ESC,23,0,14H,7
+	DEFM 'End Run RAMFTEST$'
+TNMIAB:	DEFB ESC,23,0,14H
+	DEFM 'Time Out !!$'
+;
+;
+INI_MSG:DEFM	'ECB-4PIO Init all PIO Bit-Mode ',CR,LF,'$'
+PIO0ADW:DEFM	'ECB-4PIO Write to  PIO0AD ','$'
+PIO0ADR:DEFM	'ECB-4PIO Read from PIO0AD ','$'
+PIO0BDW:DEFM	'ECB-4PIO Write to  PIO0BD ','$'
+PIO0BDR:DEFM	'ECB-4PIO Read from PIO0BD ','$'
+PIO1ADW:DEFM	'ECB-4PIO Write to  PIO1AD ','$'
+PIO1ADR:DEFM	'ECB-4PIO Read from PIO1AD ','$'
+PIO1BDW:DEFM	'ECB-4PIO Write to  PIO1BD ','$'
+PIO1BDR:DEFM	'ECB-4PIO Read from PIO1BD ','$'
+
+PIO_SRTMSG:
+	DEFM	'ECB-ZILOG PERIPHERALS start test 1.0',CR,LF,'$'
+PIO_ENDMSG:	
+	DEFM	'ECB-ZILOG PERIPHERALS end test 1.0',CR,LF,'$'
+LINE_E:	DEFM	'H',CR,LF,'$'
+;
+	IF1
+	.PRINTX 'Pass 1 complete'
+	ENDIF
+;
+	IF2
+	.PRINTX 'Pass 2 complete'
+	.PRINTX 'Assembly complete'
+	ENDIF
+;
+	END	
+

Source/Apps/Test/2piotst/Build.cmd

@@ -0,0 +1,13 @@
+@echo off
+setlocal
+
+set TOOLS=..\..\..\..\Tools
+
+set PATH=%TOOLS%\zxcc;%PATH%
+
+set CPMDIR80=%TOOLS%/cpm/
+
+zxcc M80 -=2piotst/l || exit /b
+zxcc L80 -2piotst,2piotst.com/n/e || exit /b
+
+copy /Y 2piotst.com ..\..\..\..\Binary\Apps\Test\ || exit /b

Source/Apps/Test/2piotst/Clean.cmd

@@ -0,0 +1,8 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin
+if exist *.rel del *.rel
+if exist *.prn del *.prn

Source/Apps/Test/2piotst/Makefile

@@ -0,0 +1,8 @@
+OBJECTS = 2piotst.com
+DEST = ../../../../Binary/Apps/Test
+TOOLS =../../../../Tools
+OTHERS = *.rel
+
+include $(TOOLS)/Makefile.inc
+
+2piotst.com : 2piotst.rel

Source/Apps/Test/Build.cmd

@@ -20,6 +20,8 @@ pushd rzsz && call Build || exit /b & popd
 pushd vdctest && call Build || exit /b & popd
 pushd kbdtest && call Build || exit /b & popd
 pushd ps2info && call Build || exit /b & popd
+pushd 2piotst && call Build || exit /b & popd
+pushd piomon && call Build || exit /b & popd
 
 goto :eof
 

Source/Apps/Test/Clean.cmd

@@ -17,3 +17,5 @@ pushd rzsz && call Clean || exit /b 1 & popd
 pushd vdctest && call Clean || exit /b 1 & popd
 pushd kbdtest && call Clean || exit /b 1 & popd
 pushd ps2info && call Clean || exit /b 1 & popd
+pushd 2piotst && call Clean || exit /b 1 & popd
+pushd piomon && call Clean || exit /b 1 & popd

Source/Apps/Test/DMAmon/Readme.txt

@@ -1 +1,8 @@
 DMAmon is a program to verify operation of the Z80 MBC DMA board
+
+Version 2 has been hacked to include testing for interrupts.  This
+requires running the application under RomWBW using IM2.  There
+is an equate in the source file to disable interrupt testing
+if needed.
+
+--WBW 10:36 AM 3/14/2022

Source/Apps/Test/DMAmon/dmamon.asm

@@ -16,6 +16,14 @@ TRUE		.EQU	~FALSE
 SPD_FIXED	.EQU	0		; PLATFORM SPEED FIXED AND CANNOT CHANGE SPEEDS
 SPD_HILO	.EQU	1		; PLATFORM CAN CHANGE BETWEEN TWO SPEEDS
 ;
+; INTERRUPT TESTING CONFIGURATION
+; N.B., INTERRUPT TESTING REQUIRES ROMWBW!!!
+; ASSUMES SYSTEM IS ALREADY CONFIGURED FOR IM2 OPERATION
+; INTIDX MUST BE SET TO AN UNUSED INTERRUPT SLOT
+;		
+INTENABLE	.EQU	TRUE		; ENABLE INT TESTING
+INTIDX		.EQU	1		; INT VECTOR INDEX
+;
 ; SYSTEM SPEED CHARACTERISTICS
 ;
 SPD_UNSUP	.EQU	0		; PLATFORM CAN CHANGE SPEEDS BUT IS UNSUPPORTED
@@ -56,14 +64,20 @@ DMA_RESET			.equ	$c3
 ;DMA_RESET_PORT_B_TIMING	.equ	$cb
 ;DMA_CONTINUE			.equ	$d3
 ;DMA_DISABLE_INTERUPTS		.equ	$af
-;DMA_ENABLE_INTERUPTS		.equ	$ab
+DMA_ENABLE_INTERUPTS		.equ	$ab
 ;DMA_RESET_DISABLE_INTERUPTS	.equ 	$a3
 ;DMA_ENABLE_AFTER_RETI		.equ	$b7
-;DMA_REINIT_STATUS_BYTE		.equ	$8b
+DMA_REINIT_STATUS_BYTE		.equ	$8b
 ;
 DMA_RDY				.EQU	%00001000
 DMA_FORCE			.EQU	0
-
+;
+bf_sysint			.equ	$FC	; INT function
+;		
+bf_sysintinfo			.equ	$00	; INT INFO subfunction
+bf_sysintget			.equ	$10	; INT GET subfunction
+bf_sysintset			.equ	$20	; INT SET subfunction
+;
 #IF (DMA_USEHS & (DMAMODE=DMAMODE_MBC))
 #IF (CPUSPDDEF=SPD_HIGH)
 #DEFINE DMAIOSLO LD A,(HB_RTCVAL) \ AND %11110111 \ OUT (RTCIO),A 
@@ -100,66 +114,128 @@ MAIN:
 	LD	SP,STACK		; STACK
 ;
 	call	PRTSTRD			; WELCOME
-	.db	"DMA MONITOR\n\r$"
+	.db	"\n\rDMA Monitor V2\n\r$"
+;
+#IF (INTENABLE)
+;
+	; Install interrupt handler in upper mem
+	ld	hl,reladr
+	ld	de,$A000
+	ld	bc,hsiz
+	ldir
+;
+	; Install interrupt vector (RomWBW specific!!!)
+	ld	hl,int		; pointer to my interrupt handler
+	ld	b,bf_sysint
+	ld	c,bf_sysintset	; set new vector
+	ld	e,INTIDX	; vector idx
+	di
+	rst	08		; do it
+	ld	(orgvec),hl	; save the original vector
+	ei			; interrupts back on
+;
+#ENDIF
 ;
 MENULP:	CALL	DISPM			; DISPLAY MENU
 	CALL	CIN			; GET SELECTION
+	; Force upper case
+	CP	'a'			; < 'a'
+	JR	C,MENULP1		; IF SO, JUST CONTINUE
+	CP	'z'+1			; > 'z'
+	JR	NC,MENULP1		; IS SO, JUST CONTINUE
+	SUB	'a'-'A'			; CONVERT TO UPPER
 ;
+MENULP1:
+	CALL	NEWLINE
 	CP	'D'
 	JP	Z,DMATST_D		; DUMP REGISTERS
 	CP	'I'
 	JP	Z,DMATST_I		; INITIALIZE
+#IF (INTENABLE)
+	CP	'T'
+	JP	Z,DMATST_T		; TOGGLE INT USAGE
+#ENDIF
 	CP	'M'
-	JP	Z,DMATST_M		; MEMORY MOVE
+	JP	Z,DMATST_M		; MEMORY COPY
+	CP	'N'
+	JP	Z,DMATST_N		; MEMORY COPY ITER
 	CP	'0'
 	JP	Z,DMATST_01
 	CP	'1'
-	JR	Z,DMATST_01
+	JP	Z,DMATST_01
 	CP	'R'
 	JP	Z,DMATST_R		; TOGGLE RESET
 	CP	'Y'
 	JP	Z,DMATST_Y		; TOGGLE READY
 	CP	'X'
-	JR	Z,DMABYE		; EXIT
+	JP	Z,DMABYE		; EXIT
 ;
 	JR	MENULP
 ;
-DMABYE:	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
+DMABYE:
+#IF (INTENABLE)
+	; Deinstall interrupt vector
+	ld	hl,(orgvec)	; original vector
+	ld	b,bf_sysint
+	ld	c,bf_sysintset	; set new vector
+	ld	e,INTIDX	; vector idx
+	di
+	rst	08		; do it
+	ei			; interrupts back on
+#ENDIF
+;
+	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
 	RET
 ;
 DMATST_I:
 	call	PRTSTRD
-	.db	"\n\rSTART DMA_INIT\n\r$"
+	.db	"\n\rStart Initialization\n\r$"
 	CALL	DMA_INIT
 	JP	MENULP
 ;
+#IF (INTENABLE)
+;
+DMATST_T:
+	LD	A,(USEINT)
+	XOR	$FF
+	LD	(USEINT),A
+	JP	MENULP
+;
+#ENDIF
+;
 DMATST_M:
 	call	PRTSTRD
-	.db	"\n\rSTART DMAMemMove\n\r$"
-	CALL	DMAMemMove
+	.db	"\n\rPerforming Memory-Memory Copy Test\n\r$"
+	CALL	DMAMemTest
+	JP	MENULP
+;
+DMATST_N:
+	call	PRTSTRD
+	.db	"\n\rPerforming Iterative Memory-Memory Copy Test\n\r$"
+	CALL	DMAMemTestIter
 	JP	MENULP
 ;
 DMATST_01:
 	call	PRTSTRD
-	.db	"\n\rTOGGLE PORT\n\r$"
+	.db	"\n\rPerforming Port Selection Test\n\r$"
 	CALL	DMA_Port01
 	JP	MENULP
 ;
 DMATST_D:
 	call	PRTSTRD
-	.db	"\n\rSTART DMARegDump\n\r$"
+	.db	"\n\rDump Registers\n\r$"
 	CALL	DMARegDump
 	JP	MENULP
 ;
 DMATST_Y:
 	call	PRTSTRD
-	.db	"\n\rTEST READY\n\r$"
+	.db	"\n\rPerforming Ready Bit Test\n\r$"
 	CALL	DMA_ReadyT
 	JP	MENULP
 ;
 DMATST_R:
 	call	PRTSTRD
-	.db	"\n\rRESET\n\r$"
+	.db	"\n\rPerforming Reset\n\r$"
 ;	CALL	
 	JP	MENULP
 ;==================================================================================================
@@ -167,19 +243,39 @@ DMATST_R:
 ;==================================================================================================
 ;
 DISPM:	call	PRTSTRD
-	.db	"\n\rDMA DEVICE: $"
+	.db	"\n\rDMA Device: $"
 	LD	C,DMAMODE		; DISPLAY
 	LD	A,00000111B		; TARGET
 	LD	DE,DMA_DEV_STR		; DEVICE
 	CALL	PRTIDXMSK
-	CALL	NEWLINE
 ;
 	call	PRTSTRD
-	.db	"DMA PORT: $"
+	.db	", Port=0x$"
 	LD	A,DMABASE		; DISPLAY
 	CALL	PRTHEXBYTE		; DMA PORT
-	CALL	NEWLINE
 ;
+#IF (INTENABLE)
+;
+	call	PRTSTRD
+	.db	"\n\rInterrupts=$"
+	LD	A,(USEINT)
+	OR	A
+	LD	A,'Y'
+	JR	NZ,DISPM_INT
+	LD	A,'N'
+	JR	DISPM_INT
+;
+DISPM_INT:
+	CALL	COUT
+;
+	call	PRTSTRD
+	.db	", Interrupt Count=$"
+	ld	hl,(counter)
+	call	PRTDEC
+;
+#ENDIF
+;
+	call	NEWLINE
 	LD	HL,MENU_OPT		; DISPLAY
 	CALL	PRTSTR			; MENU OPTIONS
 ;
@@ -206,7 +302,7 @@ DMA_INIT:
 	jr	nz,DMA_NOTFOUND
 ;
 	call	PRTSTRD
-	.db	" DMA FOUND\n\r$"
+	.db	" DMA Found\n\r$"
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
@@ -224,7 +320,7 @@ DMA_EXIT:
 DMA_NOTFOUND:
 	push	af
 	call	PRTSTRD
-	.db	" NOT PRESENT$"
+	.db	" NOT Present$"
 	pop	af
 	jr	DMA_EXIT
 ;
@@ -242,38 +338,41 @@ DMA_DEV_STR:
 MENU_OPT:
 	.TEXT	"\n\r"
 	.TEXT	"I) Initialize DMA\n\r"
-	.TEXT	"M) Memory to Memory test\n\r"
-	.TEXT	"0) DMA Port select test\n\r"
-	.TEXT	"1) DMA Latch Port select test\n\r"
-	.TEXT	"Y) Ready bit test\n\r"
+	.TEXT	"T) Toggle Interrupt Usage\n\r"
+	.TEXT	"M) Test Memory-Memory Copy\n\r"
+	.TEXT	"N) Test Memory-Memory Copy Iteratively\n\r"
+	.TEXT	"0) Test DMA Port Selection\n\r"
+	.TEXT	"1) Test DMA Latch Port Selection\n\r"
+	.TEXT	"Y) Test Ready Bit\n\r"
 	.TEXT	"X) Exit\n\r"
 
 	.TEXT	">$"
 ;
 ;==================================================================================================
-; TOGGLE A PORT ON AND OFF
+; PULSE PORT
 ;==================================================================================================
 ;
 DMA_Port01:
+	call	PRTSTRD
+	.db	"\r\nPulsing port 0x$"
 	sub	'0'			; Calculate
 	add	a,DMABASE		; Port to
+	call	PRTHEXBYTE
+	call	NEWLINE
 	ld	c,a			; toggle
-	ld	b,0
+	ld	b,$20			; loop counter
 portlp:	push	bc
-	call	PRTSTRD
-	.db	"\n\rON ...$"
-	call	PRTHEXWORD
+	call	PC_PERIOD
 	push	bc
 	ld	b,0
 	ld	a,0
 portlp1:out	(c),a
 	djnz	portlp1
 	pop	bc
-	call	PRTSTRD
-	.db	" OFF$"
 	call	delay	
 	pop	bc
 	djnz	portlp
+	call	NEWLINE
 	JP	MENULP
 ;
 delay:	push	bc
@@ -290,18 +389,23 @@ dlylp:	dec	bc
 ;==================================================================================================
 ;
 DMA_ReadyT:
+	call	NEWLINE
 	ld	c,DMABASE+1		; toggle
-	ld	b,0
+	ld	b,$20			; loop counter
 portlp2:push	bc
+	ld	a,b
+	call	PRTDECB
 	call	PRTSTRD
-	.db	"\n\rON ...$"
-	call	PRTHEXWORD
+	.db	": ON$"
+	call	delay
 	ld	a,$FF
 	ld	c,DMABASE+1
 	out	(c),a
 	call	PRTSTRD
-	.db	" OFF$"
+	.db	" -> OFF$"
 	call	delay
+	call	PRTSTRD
+	.db	"\r               \r$"
 	ld	c,DMABASE+1
 	ld	a,0
 	out	(c),a
@@ -332,8 +436,16 @@ DMAMemMove:
 	LD	HL,PROEND	; DMA COPY
 	LD	DE,$8000
 	LD	BC,4096-1
-	CALL	DMALDIR
-
+	LD	A,(USEINT)	; USE INTS?
+	OR	A		; TEST VALUE
+	JR	NZ,DMAMemMove1	; IF SO, DO SO
+	CALL	DMALDIR		; ELSE NORMAL DMA
+	JR	DMAMemMove2
+;
+DMAMemMove1:
+	CALL	DMALDIRINT	; DMA W/ INTERRUPTS
+;
+DMAMemMove2:
 ;
 ;	LD	HL,$8400	; PLANT
 ;	LD	A,$00		; BAD
@@ -345,15 +457,57 @@ DMAMemMove:
 NXTCMP:	CPI
 	JP	PO,CMPOK
 	JR	Z,NXTCMP
-
-	call	PRTHEXWORD
+	RET			; RET W/ ZF CLEAR
+;
+CMPOK:
+	RET			; RET W/ ZF SET
+;
+;==================================================================================================
+; DMA MEMORY TEST
+;==================================================================================================
+;
+DMAMemTest:
+	call	DMAMemMove	; do a single memory copy
+	jr	z,DMAMemTestOK
+	jr	DMAMemTestFail
+;
+DMAMemTestOK:
 	call	PRTSTRD
-	.db	" TEST MEMORY MOVE FAILED\n\r$"
-	RET
-
-CMPOK:	call	PRTSTRD
-	.db	"TEST MEMORY MOVE SUCCEEDED\n\r$"
-	RET
+	.db	"\n\rMemory-Memory Test Passed\n\r$"
+	ret
+;
+DMAMemTestFail:
+	call	PRTSTRD
+	.db	"\n\rMemory-Memory Test Failed\n\r$"
+	ret
+;
+;==================================================================================================
+; DMA MEMORY MOVE ITERATIVE
+;==================================================================================================
+;
+DMAMemTestIter:
+	ld	b,$20		; loop counter
+	call	PRTSTRD
+	.db	"\n\rPerforming $"
+	ld	a,b
+	call	PRTDECB
+	call	PRTSTRD
+	.db	" iterations, '.'=OK, '*'=Fail\n\r$"
+DMAMemTestIterLoop:
+	push	bc		; save loop control
+	call	DMAMemMove	; do an iteration
+	jr	z,DMAMemTestIterOK
+	call	PC_ASTERISK	; signal failure
+	jr	DMAMemTestIterCont	; continue
+;
+DMAMemTestIterOK:
+	call	PC_PERIOD	; signal pass
+;
+DMAMemTestIterCont:
+	pop	bc
+	djnz	DMAMemTestIterLoop
+	call	NEWLINE
+	ret
 ;
 ;==================================================================================================
 ; DMA PROBE - WRITE TO ADDRESS REGISTER AND READ BACK
@@ -455,6 +609,62 @@ DMADest		.dw	0 		; R4-Port B, Destination address
 DMACopy_Len 	.equ	$-DMACopy
 ;
 ;==================================================================================================
+; DMA COPY BLOCK CODE -  ASSUMES DMA PREINITIALIZED
+; INTERRUPT VERSION!
+;==================================================================================================
+;
+DMALDIRINT:
+;
+#IF (INTENABLE)
+;
+	ld	(DMASourceInt),hl	; populate the dma
+	ld	(DMADestInt),de		; register template
+	ld	(DMALengthInt),bc
+;
+	ld	hl,DMACopyInt		; program the
+	ld	b,DMACopyInt_Len	; dma command
+	ld	c,DMABASE		; block
+;
+	DMAIOSLO
+	di
+	otir				; load and execute dma
+	ei
+;
+	ld	a,DMA_READ_STATUS_BYTE	; check status
+	out	(DMABASE),a		; of transfer
+	in	a,(DMABASE)		; set non-zero
+	and	%00111011		; if failed
+	sub	%00011011
+	DMAIONOR
+;
+#ENDIF
+;
+	ret
+;
+#IF (INTENABLE)
+;
+DMACopyInt 	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+DMASourceInt	.dw	0 		; R0-Port A, Start address
+DMALengthInt	.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10100000 	; R3-DMA, interrupt, stop on match disabled
+		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+DMADestInt	.dw	0 		; R4-Port B, Destination address
+		.db	%00011110	; R4-Interrupt control byte: Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse control byte
+		.db	INTIDX*2	; R4-Interrupt vector
+;		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config
+		.db	%10011010
+		.db	DMA_LOAD 	; R6-Command Load
+		.db	DMA_FORCE_READY	; R6-Command Force ready
+		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACopyInt_Len 	.equ	$-DMACopyInt
+;
+#ENDIF
+;
+;==================================================================================================
 ; DMA I/O OUT BLOCK CODE - ADDRESS TO I/O PORT
 ;==================================================================================================
 ;
@@ -552,8 +762,6 @@ DMAIn_Len 	.equ	$-DMAInCode
 ; DEBUG - READ START, DESTINATION AND COUNT REGISTERS
 ;==================================================================================================
 ;
-;#IF (0)
-;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
 	out	(DMABASE),a
@@ -586,7 +794,6 @@ DMARegDump:
 ;
 	call	NEWLINE
 	ret
-;#ENDIF
 ;
 CIO_CONSOLE	.EQU	$80	; CONSOLE UNIT TO C
 BF_CIOOUT	.EQU	$01	; HBIOS FUNC: OUTPUT CHAR
@@ -662,10 +869,52 @@ CST:
 	POP	DE
 	POP	BC
 	RET
-
+;
+USEINT	.DB	FALSE		; USE INTERRUPTS FLAG
+;
 SAVSTK:	.DW	2
 	.FILL	64
 STACK:	.EQU	$
+;
+orgvec	.dw	0		; saved interrupt vector
+;
+;===============================================================================
+; Interrupt Handler
+;===============================================================================
+;
+reladr	.equ	$		; relocation start adr
+;
+	.org	$A000		; code will run here
+;
+int:
+	; According to the DMA doc, you must issue
+	; a DMA_DISABLE command prior to a
+	; DMA_REINIT_STATUS_BYTE command to avoid a
+	; potential race condition.
+	ld	a,DMA_DISABLE
+	out	(DMABASE),a
+;	
+	; The doc confuses me, but apparently it is
+	; necessary to reinitialize the status byte
+	; when an end-of-block interrupt occurs.  Otherwise,
+	; the end-of-block condition remains set and
+	; causes the interrupt to fire continuously.
+	ld	a,DMA_REINIT_STATUS_BYTE
+	out	(DMABASE),a
+;
+	ld	hl,(counter)
+	inc	hl
+	ld	(counter),hl
+;
+	or	$ff		; signal int handled
+	ret
+;
+counter	.dw	0
+;
+hsiz	.equ	$ - $A000	; size of handler to relocate
+;
+	.org	reladr + hsiz
+;
 PROEND:	.EQU	$
 ;
 	.END

Source/Apps/Test/DMAmon/dmamon.sh

@@ -1,3 +0,0 @@
-~/RomWBW-dev/Tools/unix/uz80as/uz80as -t z80 dmamon.asm dmamon.bin
-#srec_cat dmamon.bin -binary -offset 0x0100 --address-length=2 -o dmamon.hex -Intel
-cat dmamon.bin > dmamon.com

Source/Apps/Test/Makefile

@@ -1,5 +1,5 @@
 OBJECTS = 
-SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info
+SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info 2piotst piomon
 DEST = ../../../Binary/Apps/Test
 TOOLS =../../../Tools
 

Source/Apps/Test/piomon/Build.cmd

@@ -0,0 +1,10 @@
+@echo off
+setlocal
+
+set TOOLS=../../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t180 -g3 -fFF piomon.asm piomon.com piomon.lst || exit /b
+
+copy /Y piomon.com ..\..\..\..\Binary\Apps\Test\ || exit /b

Source/Apps/Test/piomon/Clean.cmd

@@ -0,0 +1,6 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin

Source/Apps/Test/piomon/Makefile

@@ -0,0 +1,7 @@
+OBJECTS = piomon.com
+DEST = ../../../../Binary/Apps/Test
+TOOLS =../../../../Tools
+
+USETASM=1
+
+include $(TOOLS)/Makefile.inc

Source/Apps/Test/piomon/Readme.txt

@@ -0,0 +1,36 @@
+PIOMON is a program to verify operation of the Z80 MBC DUALPIO board
+
+Most testing requires the use of loopback hardware constructed as:
+
+Channel A   RDY STB  D0  D1  D2  D3  D4  D5  D6  D7
+             \   /   |   |   |   |   |   |   |   |
+              \ /    |   |   |   |   |   |   |   |
+               X     |   |   |   |   |   |   |   |
+              / \    |   |   |   |   |   |   |   |
+             /   \   |   |   |   |   |   |   |   |
+Channel B   RDY STB  D0  D1  D2  D3  D4  D5  D6  D7
+
+The DUALPIO has, well, 2 PIO chips.  Only one chip
+is tested at a time.  At startup, PIOMON will ask
+you for the port of the chip to test.  It defaults
+to the standard port number for the primary PIO chip
+on an MBC DUALPIO board.
+
+The port number specified is the base I/O port.  Each
+chip has two channels which are addressed in the
+menu by specifying A or B.
+
+MBC DUALPIO Primary PIO = 0xB8
+MBC DUALPIO Secondary PIO = 0xBC
+
+If you try to use PIOMON without the RDY and STB
+cross connected, you may have interrupt issues
+because STB will be floating.
+
+N.B., V1 and V2 of the DUALPIO lack a hardware reset.  The
+PIO chips will reset at power-on, but they do not reset
+when the reset button is pushed.
+
+Happy St. Patrick's Day!!!
+
+--WBW 7:42 PM 3/17/2022

Source/Apps/Tune/tune.asm

@@ -622,6 +622,9 @@ CFGTBL:	;	PLT	RSEL	RDAT	RIN	Z180	ACR
 ;
 	.DB	$0B,	$33,	$32,	$32,	$FF,	$FF	; RCZ280 W/ LINC SOUND MODULE
 	.DW	HWSTR_LINC
+;
+	.DB	13,	$A0,	$A1,	$A0,	$FF,	$A2	; MBC
+	.DW	HWSTR_MBC
 ;
 	.DB	$FF					; END OF TABLE MARKER
 ;
@@ -674,6 +677,7 @@ HWSTR_RCEB	.DB	"RC2014 Sound Module (EB)",0
 HWSTR_RCEB6	.DB	"RC2014 Sound Module (EBv6)",0
 HWSTR_RCMF	.DB	"RC2014 Sound Module (MF)",0
 HWSTR_LINC	.DB	"Z50 LiNC Sound Module",0
+HWSTR_MBC	.DB	"NHYODYNE Sound Module",0
 
 MSGUNSUP	.db	"MYM files not supported with HBIOS yet!\r\n", 0
 
@@ -2649,4 +2653,3 @@ data:
 ;
 ;===============================================================================
 	.END
-

Source/Apps/assign.asm

@@ -22,12 +22,14 @@
 ;   2016-04-08 [WBW] Determine key memory addresses dynamically
 ;   2019-08-07 [WBW] Fixed DPB selection error
 ;   2019-11-17 [WBW] Added preliminary CP/M 3 support
-;   2019-12-24 [WBW] Fixed location of BIOS save area\
+;   2019-12-24 [WBW] Fixed location of BIOS save area
 ;   2020-04-29 [WBW] Updated for larger DPH (16 -> 20 bytes)
 ;   2020-05-06 [WBW] Add patch level to version compare
 ;   2020-05-10 [WBW] Set media change flag in XDPH for CP/M 3
 ;   2020-05-12 [WBW] Back out media change flag
 ;   2021-12-06 [WBW] Fix inverted ROM/RAM DPB mapping in buffer alloc
+;   2022-02-28 [WBW] Use HBIOS to swap banks under CP/M 3
+;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -43,6 +45,7 @@ stksiz	.equ	$40		; Working stack size
 ;
 restart	.equ	$0000		; CP/M restart vector
 bdos	.equ	$0005		; BDOS invocation vector
+bnksel	.equ	$FFF3		; HBIOS bank select vector
 ;
 stamp	.equ	$40		; loc of RomWBW CBIOS zero page stamp
 ;
@@ -108,8 +111,11 @@ init:
 	ld	c,$0C		; function number
 	call	bdos		; do it, HL := version
 	ld	(cpmver),hl	; save it
-	ld	a,l		; low byte
-	cp	$30		; CP/M 3.0?
+	;push	hl		; *debug*
+	;pop	bc		; *debug*
+	;call	prthexword	; *debug*
+	;ld	a,l		; low byte
+	;cp	$30		; CP/M 3.0?
 ;
 	; get location of config data and verify integrity
 	ld	hl,stamp	; HL := adr or RomWBW zero page stamp
@@ -231,18 +237,24 @@ initx:
 ; CP/M 3 initialization
 ;
 initcpm3:
-	ld	hl,(bioloc)
-	ld	de,22*3		; offset of DRVTBL func
-	add	hl,de		; HL := DRVTBL func
-	call	jphl		; do it, HL := DRVTBL adr
-	ld	(drvtbl),hl	; save it
+	ld	a,22		; XBIOS DRVTBL function
+	call	xbios		; Invoke XBIOS
+	ld	(drvtbl),hl	; save DRVTBL address
+;
+; The CP/M 3 drvtbl is in common memory, but the XDPHs are not.
+; So, here we temporarily swap the bank to the CP/M 3 system
+; bank.  We cannot use the CP/M Direct BIOS call because it
+; explicitly blocks use of SELMEM, so we are foreced to use
+; HBIOS call.  The CP/M 3 system bank is always the HBIOS
+; user bank.
 ;
 	; switch to sysbnk
-	ld	hl,(bioloc)
-	ld	de,27*3		; offset of SELMEM func
-	add	hl,de		; HL := SELMEM func
-	ld	a,0		; bank 0 is system bank
-	call	jphl
+	ld	a,($FFE0)	; get current bank
+	push	af		; save it
+	ld	bc,$F8F2	; HBIOS Get Bank Info
+	rst	08		; call HBIOS, E=User Bank
+	ld	a,e		; HBIOS User Bank
+	call	bnksel		; HBIOS BNKSEL
 ;
 	; copy CP/M 3 drvtbl to drvmap working copy
 	ld	hl,(drvtbl)	; get drive table in HL
@@ -278,11 +290,8 @@ initc4:
 	djnz	initc2
 ;
 	; switch back to tpabnk
-	ld	hl,(bioloc)
-	ld	de,27*3		; offset of SELMEM func
-	add	hl,de		; HL := SELMEM func
-	ld	a,1		; bank 1 is tpa bank
-	call	jphl
+	pop	af		; recover prev bank
+	call	bnksel		; HBIOS BNKSEL
 ;
  	; return success
 	xor	a		; signal success
@@ -397,6 +406,15 @@ usage:
 	call	crlf		; formatting
 	ld	de,msgban1	; point to version message part 1
 	call	prtstr		; print it
+	ld	de,msg22	; assume CP/M 2.2
+	ld	a,(cpmver)	; low byte of ver
+	cp	$30		; CP/M 3.0?
+	jp	c,usage1	; if not, jump ahead
+	ld	de,msg3		; CP/M 3
+usage1:
+	call	prtstr
+	ld	de,msbban2	; next portion of banner
+	call	prtstr
 	ld	a,(unamod)	; get UNA flag
 	or	a		; set flags
 	ld	de,msghb	; point to HBIOS mode message
@@ -404,7 +422,7 @@ usage:
 	ld	de,msgub	; point to UBIOS mode message
 	call	nz,prtstr	; if UNA, say so
 	call	crlf		; formatting
-	ld	de,msgban2	; point to version message part 2
+	ld	de,msgban3	; point to version message part 2
 	call	prtstr		; print it
 	call	crlf2		; blank line
 	ld	de,msguse	; point to usage message
@@ -728,13 +746,13 @@ makdph3:
 ;
 ;
 instcpm3:
-;
-	; switch to sysbnk
-	ld	hl,(bioloc)
-	ld	de,27*3		; offset of SELMEM func
-	add	hl,de		; HL := SELMEM func
-	ld	a,0		; bank 0 is system bank
-	call	jphl
+	; swicth to sysbnk
+	ld	a,($FFE0)	; get current bank
+	push	af		; save it
+	ld	bc,$F8F2	; HBIOS Get Bank Info
+	rst	08		; call HBIOS, E=User Bank
+	ld	a,e		; HBIOS User Bank
+	call	$FFF3		; HBIOS BNKSEL
 ;
 	; copy drvmap working copy to CP/M 3 drvtbl
 	ld	hl,(drvtbl)	; get drvtbl address
@@ -802,11 +820,8 @@ instc3:
 	djnz	instc1
 ;
 	; switch back to tpabnk
-	ld	hl,(bioloc)
-	ld	de,27*3		; offset of SELMEM func
-	add	hl,de		; HL := SELMEM func
-	ld	a,1		; bank 1 is tpa bank
-	call	jphl
+	pop	af		; recover prev bank
+	call	$FFF3		; HBIOS BNKSEL
 ;
 	; set SCB drive door open flag
 	ld	a,$54		; SCB drive door opened flag
@@ -1733,6 +1748,23 @@ cbios:
 	call	addhl		; determine specific function address
 	jp	(hl)		; invoke CBIOS
 ;
+; Routine to call CPM3 BIOS routines via BDOS
+; function 50.
+;
+xbios:
+	ld	(biofnc),a	; set BIOS function
+	ld	c,50		; direct BIOS call function
+	ld	(dereg),de	; set DE parm
+	ld	de,biospb	; BIOS parameter block
+	jp	bdos		; invoke BDOS
+;
+biospb:
+biofnc	.db	0		; BIOS function
+areg	.db	0		; A register
+bcreg	.dw	0		; BC register
+dereg	.dw	0		; DE register
+hlreg	.dw	0		; HL register
+;
 ; Add the value in A to HL (HL := HL + A)
 ;
 addhl:
@@ -1911,10 +1943,13 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.4a for RomWBW CP/M, 6-Dec-2021",0
+msgban1	.db	"ASSIGN v1.5 for RomWBW CP/M ",0
+msg22	.db	"2.2",0
+msg3	.db	"3",0
+msbban2	.db	", 28-Feb-2022",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
-msgban2	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
+msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"Usage: ASSIGN D:[=[{D:|<device>[<unitnum>]:[<slicenum>]}]][,...]",13,10
 	.db	"  ex. ASSIGN           (display all active assignments)",13,10
 	.db	"      ASSIGN /?        (display version and usage)",13,10

Source/Doc/Applications.md

@@ -168,6 +168,11 @@ This command is particularly sensitive to being matched to the
 appropriate version of the RomWBW ROM you are using. Be very careful
 to keep all copies of `ASSIGN.COM` up to date with your ROM.
 
+Additionally, the `ASSIGN` command must be able to adjust to CP/M 2.2
+vs. CP/M 3.  If you utilize an RSX that modifies the BDOS version
+returned, you are likely to have serious problems.  In this case, be
+sure to use `ASSIGN` prior to loading the RSX or after it is unloaded.
+
 ## Etymology
 
 The `ASSIGN` command is an original product and the source code is

Source/HBIOS/Build.cmd

@@ -93,8 +93,10 @@ copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin osimg_small.bin || exit
 :: should yield a result of zero.
 ::
 
-for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
-  "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
+if %ROMSize% gtr 0 (
+    for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
+      "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
+    )
 )
 
 ::
@@ -113,17 +115,23 @@ for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
 :: HBIOS on the fly for testing purposes.
 ::
 
-copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin + ..\RomDsk\rom%ROMSize%_wbw.dat %ROMName%.rom || exit /b
-copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
-copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+if %ROMSize% gtr 0 (
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin + ..\RomDsk\rom%ROMSize%_wbw.dat %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
+    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+) else (
+    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.upd || exit /b
+    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+)
 
 ::
 :: Copy results to output directory
 ::
 
-copy %ROMName%.rom ..\..\Binary || exit /b
-copy %ROMName%.upd ..\..\Binary || exit /b
-copy %ROMName%.com ..\..\Binary || exit /b
+if exist %ROMName%.rom copy %ROMName%.rom ..\..\Binary || exit /b
+if exist %ROMName%.upd copy %ROMName%.upd ..\..\Binary || exit /b
+if exist %ROMName%.com copy %ROMName%.com ..\..\Binary || exit /b
 
 goto :eof
 
@@ -188,6 +196,7 @@ call Build RCZ80 kio 512 || exit /b
 call Build RCZ80 mt 512 || exit /b
 call Build RCZ80 duart 512 || exit /b
 call Build RCZ80 zrc 512 || exit /b
+call Build RCZ80 zrc_ram 0 || exit /b
 call Build RCZ180 ext 512 || exit /b
 call Build RCZ180 nat 512 || exit /b
 call Build RCZ280 ext 512 || exit /b

Source/HBIOS/Build.ps1

@@ -76,8 +76,8 @@ while ($true)
 
 while ($true)
 {
-	if (($RomSize -eq 128) -or ($RomSize -eq 256) -or ($RomSize -eq 512) -or ($RomSize -eq 1024)) {break}
-	$RomSize = (Read-Host -prompt "ROM Size [128|256|512|1024]").Trim()
+	if (($RomSize -eq 0) -or ($RomSize -eq 128) -or ($RomSize -eq 256) -or ($RomSize -eq 512) -or ($RomSize -eq 1024)) {break}
+	$RomSize = (Read-Host -prompt "ROM Size [0|128|256|512|1024]").Trim()
 }
 
 #

Source/HBIOS/Build.sh

@@ -26,6 +26,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; ROMSIZE="512"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; ROMSIZE="0"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="MBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
@@ -71,7 +72,7 @@ if [ -z "${ROMSIZE}" ] ; then
 	ROMSIZE="512"
 fi
 
-while [ ! '(' "${ROMSIZE}" = 1024 -o "${ROMSIZE}" = 512 -o "${ROMSIZE}" = 256 -o "${ROMSIZE}" = 128 ')' ] ; do
+while [ ! '(' "${ROMSIZE}" = 1024 -o "${ROMSIZE}" = 512 -o "${ROMSIZE}" = 256 -o "${ROMSIZE}" = 128 -o "${ROMSIZE}" = 0 ')' ] ; do
 	echo -n "Romsize :"
 	read ROMSIZE
 done

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -30,6 +30,7 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 ;
+RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -0,0 +1,54 @@
+;
+;==================================================================================================
+;   RC2014 Z80 ZRC CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+;
+RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+;
+AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Makefile

@@ -56,18 +56,26 @@ $(ROMNAME).rom $(ROMNAME).com $(ROMNAME).img &: $(ROMDEPS)
 	if [ $(ROM_PLATFORM) != UNA ] ; then \
 		cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin usrrom.bin >osimg1.bin ; \
 		cat imgpad2.bin >osimg2.bin ; \
-		for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
-			srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
-		done \
+		if [ $(ROMSIZE) -gt 0 ] ; then \
+			for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
+				srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
+			done \
+		fi \
 	fi
 	if [ $(ROM_PLATFORM) = UNA ] ; then \
 		cp osimg.bin $(DEST)/UNA_WBW_SYS.bin ; \
 		cp ../RomDsk/rom$(ROMSIZE)_una.dat $(DEST)/UNA_WBW_ROM$(ROMSIZE).bin ; \
 		cat ../UBIOS/UNA-BIOS.BIN osimg.bin ../UBIOS/FSFAT.BIN ../RomDsk/rom$(ROMSIZE)_una.dat >$(ROMNAME).rom ; \
 	else \
-		cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/rom$(ROMSIZE)_wbw.dat >$(ROMNAME).rom ; \
-		cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
-		cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+		if [ $(ROMSIZE) -gt 0 ] ; then \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/rom$(ROMSIZE)_wbw.dat >$(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
+			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+		else \
+			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).upd ; \
+			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+		fi \
 	fi
 
 prereq: $(FONTS) camel80.bin tastybasic.bin

Source/HBIOS/ay38910.asm

@@ -48,6 +48,14 @@ AY_RDAT		.EQU	$32
 AY_RIN		.EQU	$32
 #ENDIF
 ;
+#IF (AYMODE == AYMODE_MBC)
+AY_RSEL		.EQU	$A0
+AY_RDAT		.EQU	$A1
+AY_RIN		.EQU	AY_RSEL
+AY_ACR		.EQU	$A2
+AY_CLK		.SET	3579545 	; MSX NTSC COLOUR BURST FREQ = 315/88
+#ENDIF
+;
 ;======================================================================
 ;
 ;	REGISTERS
@@ -128,6 +136,10 @@ AY38910_INIT:
 	PRTS(" MODE=MSX$")
 #ENDIF
 ;
+#IF (AYMODE == AYMODE_MBC)
+	PRTS(" MODE=MBC$")
+#ENDIF
+;
 #IF (AYMODE == AYMODE_LINC)
 	PRTS(" MODE=LINC$")
 #ENDIF
@@ -136,7 +148,7 @@ AY38910_INIT:
 	LD	A,AY_RSEL
 	CALL	PRTHEXBYTE
 ;
-#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8))
+#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8) | (AYMODE == AYMODE_MBC))
 	LD	A,$FF			; ACTIVATE DEVICE BIT 4 IS AY RESET CONTROL, BIT 3 IS ACTIVE LED
 	OUT	(AY_ACR),A		; SET INIT AUX CONTROL REG
 #ENDIF

Source/HBIOS/cfg_dyno.asm

@@ -125,7 +125,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -179,6 +179,8 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -192,7 +194,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_ezz80.asm

@@ -163,7 +163,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -221,6 +221,8 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -234,7 +236,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_master.asm

@@ -286,6 +286,11 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -303,7 +308,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mbc.asm

@@ -152,7 +152,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
@@ -218,6 +218,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
+PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -235,7 +240,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mk4.asm

@@ -151,7 +151,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -219,6 +219,11 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -236,7 +241,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_n8.asm

@@ -153,7 +153,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -217,6 +217,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -234,7 +239,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz180.asm

@@ -169,7 +169,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -233,6 +233,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -246,7 +251,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz280.asm

@@ -185,7 +185,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -249,6 +249,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -262,7 +267,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz80.asm

@@ -174,7 +174,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -238,6 +238,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -251,7 +256,7 @@ SNMODE		.EQU	SNMODE_RCZ80	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_sbc.asm

@@ -152,7 +152,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
@@ -218,6 +218,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -235,7 +240,7 @@ SNMODE		.EQU	SNMODE_VGM	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_scz180.asm

@@ -164,7 +164,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -228,6 +228,11 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -241,7 +246,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_zeta.asm

@@ -162,6 +162,11 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_zeta2.asm

@@ -135,7 +135,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -173,6 +173,8 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/hbios.asm

@@ -513,7 +513,7 @@ HBX_BNKSEL1:
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
-	ADD	A,$10			; ADD 16 x 32K - RAM STARTS FROM 512K
+	ADD	A,ROMSIZE / 32		; STARTING RAM BANK NUMBER OFFSET
 ;
 HBX_ROM:
 	OUT	($1F),A			; HCS WRITE TO THE BANK CONTROL REGISTER
@@ -575,7 +575,7 @@ HBX_BNKCPY:
 	SC	Z280_BNKCPYX		; SYSCALL TO BNKCPYX
 	RET
 ;
-IOPRVAL	.DW	0			; TEMP STORAGE FOR IOPR
+IOPRSAV	.DW	0			; TEMP STORAGE FOR IOPR
 ;
 #ELSE
   #IF (CPUFAM == CPU_Z280)
@@ -1530,6 +1530,31 @@ MBC_SINGLE:
 ;
 #ENDIF
 ;
+; IF THIS IS A ROM-LESS SYSTEM, THEN WE NEED TO COPY THE "APP" BANK TO
+; TPA.  IT IS DONE PRIOR TO COPYING HBIOS TO IT'S FINAL BANK BECAUSE
+; THE SOURCE OF THE APP BANK CODE MAY BE THE BANK THAT HBIOS WANTS TO
+; USE AS IT'S FINAL LOCATION (PRIMARILY IN CASE OF RAMBOOT WHERE THE
+; SYSTEM HAS THE MINIMUM 128KB OF RAM).
+;
+#IFDEF ROMBOOT
+  #IF (ROMSIZE == 0)
+	LD	A,(HB_CURBNK)
+	LD	(HB_SRCBNK),A
+	LD	A,BID_USR
+	LD	(HB_DSTBNK),A
+	LD	HL,HB_END
+	LD	DE,0
+	LD	BC,$8000
+    #IF (MEMMGR == MM_Z280)
+	CALL	Z280_BNKCPY
+    #ELSE
+	CALL	HBX_BNKCPY
+    #ENDIF
+;
+  #ENDIF
+;
+#ENDIF
+;
 ; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
 ;
 	LD	A,(HB_RAMFLAG)
@@ -2439,6 +2464,7 @@ HB_Z280BUS1:
 #ENDIF
 ;
 #IFDEF ROMBOOT
+  #IF (ROMSIZE > 0)
 ;
 ; ROM CHECKSUM VERIFICATION
 ; EACH OF THE FIRST 4 ROM BANKS HAS A CHECKSUM INJECTED SUCH THAT
@@ -2509,6 +2535,7 @@ HB_CKBNKSIZ	.EQU	$-HB_CKBNK	; SIZE OF ROUTINE
 ;
 HB_ROMCKZ:
 ;
+  #ENDIF
 #ENDIF
 ;
 ; LOW BATTERY DIAGNOSTIC MESSAGE
@@ -2712,15 +2739,8 @@ INITSYS4:
 	LDCTL	(C),HL
 #ENDIF
 ;
-; CHAIN TO OS LOADER
+#IFNDEF ROMBOOT
 ;
-#IFDEF ROMBOOT
-	; PERFORM BANK CALL TO OS IMAGES BANK IN ROM
-	LD	A,BID_IMG0		; CHAIN TO OS IMAGES BANK
-	LD	IX,0			; ENTER AT ADDRESS 0
-	CALL	HBX_BNKCALL		; GO THERE
-	HALT				; WE SHOULD NEVER COME BACK!
-#ELSE
 	; COPY OS IMAGE: BID_USR:<IMG START> --> BID_USR:0
 	LD	B,BF_SYSSETCPY		; HBIOS FUNC: SETUP BANK COPY
 	LD	D,BID_USR		; D = DEST BANK = USER BANK
@@ -2734,16 +2754,23 @@ INITSYS4:
 	LD	DE,0			; TO USER ADDRESS 0
 	RST	08			; DO IT
 ;
-	; PERFORM BANK CALL TO USER BANK
-	LD	A,BID_USR		; CHAIN TO OS IMAGES BANK
+#ENDIF
+;
+; CHAIN TO LOADER
+;
+#IFDEF ROMBOOT
+  #IF (ROMSIZE > 0)
+	LD	A,BID_IMG0		; CHAIN TO OS IMAGES BANK
+  #ELSE
+	LD	A,BID_USR		; CHAIN TO USER BANK
+  #ENDIF
+#ELSE
+	LD	A,BID_USR		; CHAIN TO USER BANK
+#ENDIF
 	LD	IX,0			; ENTER AT ADDRESS 0
 	CALL	HBX_BNKCALL		; GO THERE
 	HALT				; WE SHOULD NEVER COME BACK!
 ;
-#ENDIF
-;
-	RET
-;
 ;	CALL A LIST OF ROUTINES POINTED TO BY DE OF LENGTH B.
 ;
 CALLLIST:
@@ -2814,6 +2841,9 @@ HB_PCINITTBL:
 #IF (ACIAENABLE)
 	.DW	ACIA_PREINIT
 #ENDIF
+#IF (PIOENABLE)
+	.DW	PIO_PREINIT
+#ENDIF
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_PREINIT
 #ENDIF
@@ -2933,6 +2963,9 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (PIOENABLE)
+	.DW	PIO_INIT
+#ENDIF
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_INIT
 #ENDIF
@@ -5428,7 +5461,7 @@ Z280_BNKCPY:
 	; SELECT I/O PAGE $FF
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
 	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
-	LD	(IOPRVAL),HL		; SAVE IT
+	LD	(IOPRSAV),HL		; SAVE IT
 	LD	L,$FF			; I/O PAGE $FF
 	LDCTL	(C),HL
 ;
@@ -5456,7 +5489,7 @@ Z2DMALOOP:
 ;
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
-	LD	HL,(IOPRVAL)		; RESTORE I/O PAGE
+	LD	HL,(IOPRSAV)		; RESTORE I/O PAGE
 	LDCTL	(C),HL
 ;
 	; SETUP RETURN VALUES
@@ -5886,6 +5919,15 @@ SIZ_SPK	.EQU	$ - ORG_SPK
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (PIOENABLE)
+ORG_PIO		.EQU	$
+  #INCLUDE "pio.asm"
+SIZ_PIO		.EQU	$ - ORG_PIO
+		.ECHO	"PIO occupies "
+		.ECHO	SIZ_PIO
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (PIO_4P | PIO_ZP | PIO_SBC)
 ORG_PIO		.EQU	$
   #INCLUDE "pio.asm"
@@ -6736,7 +6778,7 @@ PS_SDPRPCON	.TEXT	"PRPCON$"
 PS_SDPPPCON	.TEXT	"PPPCON$"
 PS_SDSIO	.TEXT	"SIO$"
 PS_SDACIA	.TEXT	"ACIA$"
-PS_SDPIO	.TEXT	"PORT$"
+PS_SDPIO	.TEXT	"PIO$"
 PS_SDUF		.TEXT	"UF$"
 PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
@@ -6999,7 +7041,9 @@ SLACK		.EQU	BNKTOP - $
 		.ECHO	" bytes.\n"
 ;
 #IFDEF ROMBOOT
+  #IF (ROMSIZE > 0)
 		.FILL	SLACK
+  #ENDIF
 #ENDIF
 ;
 		.END

Source/HBIOS/pio_ps.asm

@@ -0,0 +1,999 @@
+; PIO driver sets up the parallel port as a subtype of Serial/Char device.
+;
+;
+; HBIOS initializes driver by:
+;
+; 1) Calling Pre-initialization
+;
+;    This involves setting up all the data structures describing the devices.
+;    If possible, do a hardware test to verify it is available for adding to available devices.
+;
+; 2) Calling device initialization.
+;
+;    Hardware initialization.
+;    Configure to initial state or to a new state.
+;
+; Implementation limitations:
+;
+; The fully functionality of the Z80 PIO can only be realized by using Z80 interrupt mode 2.
+; Registers cannot be interrogated for interrupts status and the originating interrupt
+; device cannot be determine.
+;
+; Full implementation of IM2 functionality for an ECB-ZP and ECB-4P board would require the 
+; allocation of an interrupt handler for each chip channel. Thus, 12 interrupt handlers
+; would be required to support this configuration. As the HBIOS only has an allocation of
+; 16, a full implmentation is impractical.
+;
+; The compromise solution is to allow 4 interrupts for the PIO driver. All remaining PIO's
+; are limited to Bit mode or blind read and write to the input/output ports.
+;
+; Zilog PIO reset state:
+;
+;	Both port mask registers are reset to inhibit All port data bits.
+;	Port data bus lines are set to a high-impedance state and the Ready "handshake"
+;	Mode 1 (output) is automatically selected.
+;	The vector address registers are not reset.
+;	Both port interrupt enable flip-flops are reset.
+;	Both port output registers are reset.
+;
+; Register addressing example for ECB-ZP and ECB-4P assuming base address 90h and 88h respectively.
+;
+; PIO ----ZP---- ----4P----
+;  0  DATA 0 90h DATA 0 B8h
+;  0  DATA 1 91h DATA 1 B9h
+;  0  CMD  0 92h CMD  0 BAh
+;  0  CMD  1 93h CMD  1 BBh
+;  1  DATA 0 94h DATA 0 BCh
+;  1  DATA 1 95h DATA 1 BDh
+;  1  CMD  0 96h CMD  0 BEh
+;  1  CMD  1 97h CMD  1 BFh
+;  2             DATA 0 C0h
+;  2             DATA 1 C1h
+;  2             CMD  0 C2h
+;  2             CMD  1 C3h
+;  3             DATA 0 C4h
+;  3             DATA 1 C5h
+;  3             CMD  0 C6h
+;  3             CMD  1 C7h
+;
+PIODEBUG	.EQU	1
+;
+M_Output	.EQU	$00 << 6
+M_Input		.EQU	$01 << 6
+M_Bidir		.EQU	$02 << 6
+M_BitCtrl	.EQU	$03 << 6
+M_BitAllIn	.EQU	$FF
+M_BitAllOut	.EQU	$00
+;
+PIO_NONE	.EQU	0
+PIO_ZPIO	.EQU	1
+PIO_8255	.EQU	2
+PIO_PORT	.EQU	3
+
+; SET MAXIMUM NUMBER OF INTERRUPTS AVAILABLE FOR ALL
+; ENSURE INTERRUPTS ARE NOT TURNED ON IF IM2 IS NOT SET.
+
+INT_ALLOC	.DB	0
+INT_N		.EQU	00000000B
+#IF	(INTMODE == 2)
+INT_Y		.EQU	00000100B
+INT_ALLOW	.EQU	4
+#ELSE
+INT_Y		.EQU	INT_N
+INT_ALLOW	.EQU	0
+#ENDIF
+;
+INT0		.EQU	00000000B
+INT1		.EQU	00000001B
+INT2		.EQU	00000010B
+INT3		.EQU	00000011B
+
+;
+; SETUP THE DISPATCH TABLE ENTRIES
+;
+; PIO_CNT HOLDS THE NUMBER OF DEVICED CALCULATED FROM THE NUMBER OF DEFPIO MACROS
+; PIO_CNT SHOULD INCREASE BY 2 FOR EVERY PIO CHIP ADDED.
+;
+; PIO_PREINIT WILL READ THROUGH ALL PIOCFG TABLES AND CONFIGURE EACH TABLE.
+; IT WITH THEN CALL PIO_INITUNIT TO INITIALIZE EACH DEVICE TO ITS DEFAULT STATE
+; 
+; EXPECTS NOTHING ON ENTRY
+;
+PIO_PREINIT:
+	CALL	NEWLINE		;D
+	LD	B,PIO_CNT		; LOOP CONTROL
+	LD	C,0			; PHYSICAL UNIT INDEX
+	XOR	A			; ZERO TO ACCUM
+;	LD	(PIO_DEV),A		; CURRENT DEVICE NUMBER
+	LD	(INT_ALLOC),A		; START WITH NO INTERRUPTS ALLOCATED
+PIO_PREINIT0:	
+	PUSH	BC			; SAVE LOOP CONTROL
+;	LD	A,C			; INITIALIZE THE UNIT
+
+;	PUSH	AF		;D
+;	LD	A,'u'		;D
+;	CALL	COUT		;D
+;	POP	AF		;D
+;	CALL	PRTHEXBYTE	;D	UNIT
+;	CALL	PC_SPACE	;D
+
+;	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+;	RLCA				; ...
+;	RLCA				; ... TO GET OFFSET INTO CFG TABLE
+;	RLCA
+;;	RLCA
+;	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+;	PUSH	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	POP	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	PUSH	HL			; SAVE IT
+;	POP	IY			; ... TO IY
+
+	CALL	IDXCFG			
+
+	LD	(HL),C
+
+	PUSH	AF		;D
+	LD	A,'c'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	PUSH	BC		;D
+	PUSH	HL		;D
+	POP	BC		;D
+	CALL	PRTHEXWORD	;D	CONFIG TABLE
+	CALL	PC_SPACE	;D
+	POP	BC		;D
+
+	LD	A,(IY+1)		; GET THE PIO TYPE DETECTED
+	CP	PIO_PORT		; SET FLAGS
+
+	PUSH	AF		;D
+	LD	A,'t'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	CALL	PRTHEXBYTE	;D	TYPE
+	CALL	PC_SPACE	;D
+
+;	JR	Z,BADINIT
+
+;	PUSH	BC			; SAVE LOOP CONTROL
+;	LD	BC,PIO_FNTBL		; BC := FUNCTION TABLE ADDRESS	
+;	DEC	A
+;	JR	Z,TYPFND		; SKIP IT IF NOTHING FOUND
+;	LD	BC,PPI_FNTBL		; BC := FUNCTION TABLE ADDRESS
+;	DEC	A
+;	JR	Z,TYPFND		; ADD ENTRY IF PIO FOUND, BC:DE
+;	LD	BC,PRT_FNTBL
+;	DEC	A
+;	JR	Z,TYPFND
+;	POP	BC
+;	JR	BADINIT
+
+	PUSH	HL
+	LD	DE,-1			; INITIALIZE THIS DEVICE WITH
+	CALL	PIO_INITDEV		; DEFAULT VALUES
+	POP	HL
+
+;	JR	NZ,SKPINIT
+
+	; AT THIS POINT WE KNOW WE
+	; HAVE A VALID DEVICE SO ADD IT
+	
+	LD	A,8			; CALCULATE THE FUNCTION TABLE 
+	CALL	ADDHLA			; POSITION WHICH FOLLOWS THE
+	PUSH	HL			; CONFIGURATION TABLE OF EACH
+	POP	BC			; DEVICE
+
+TYPFND:	PUSH	AF		;D
+	LD	A,'f'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	PUSH	BC		;D
+	CALL	PRTHEXWORD	;D	FUNCTION TABLE
+	POP	BC		;D
+	CALL	NEWLINE		;D
+
+	PUSH	IY			; ADD ENTRY IF PIO FOUND, BC:DE
+	POP	DE			; BC: DRIVER FUNCTION TABLE
+	CALL	CIO_ADDENT		; DE: ADDRESS OF UNIT INSTANCE DATA
+
+BADINIT:POP	BC			; RESTORE LOOP CONTROL
+
+	INC	C			; NEXT PHYSICAL UNIT
+SKPINIT:DJNZ	PIO_PREINIT0		; LOOP UNTIL DONE
+
+	PUSH	AF		;D
+	PRTS("INTS=$")		;D
+	LD	A,(INT_ALLOC)	;D
+	CALL	PRTHEXBYTE	;D
+	POP	AF		;D
+	PUSH	DE		;D
+	LD	DE,CIO_TBL-3	;D
+	CALL	DUMP_BUFFER	;D
+	POP	DE		;D
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; INDEX INTO THE CONFIG TABLE
+; ON ENTRY C = UNIT NUMBER
+; ON EXIT IY = CONFIG DATA POINTER
+; ON EXIT DE = CONFIG TABLE START
+;
+; EACH CONFIG TABLE IS 24 BYTES LONG
+;
+CFG_SIZ		.EQU	24
+;
+IDXCFG:	LD	A,C
+	RLCA				; X 2
+	RLCA				; X 4
+	RLCA				; X 8
+	LD	H,0
+	LD	L,A			; HL = X 8
+	PUSH	HL
+	ADD	HL,HL			; HL = X 16
+	POP	DE
+	ADD	HL,DE			; HL = X 24
+	LD	DE,PIO_CFG
+	ADD	HL,DE
+	PUSH	HL			; COPY CFG DATA PTR
+	POP	IY			; ... TO IY
+	RET
+	
+; PIO_INITDEV - INITIALIZE DEVICE
+;
+; IF DE = FFFF THEN THE SETUP PARAMETER WORD WILL BE READ FROM THE DEVICE CONFIGURATION  
+; TABLE POINTED TO BY IY AND THE PIO PORT WILL BE PROGRAMMED BASED ON THAT CONFIGURATION. 
+;
+; OTHERWISE THE PIO PORT WILL BE PROGRAMMED BY THE SETUP PARAMETER WORD IN DE AND THIS 
+; WILL BE SAVED IN THE DEVICE CONFIGURATION TABLE POINTED TO BY IY.
+;
+; ALL OTHER CONFIGURATION OF THE DEVICE CONFIGURATION TABLE IS DONE UPSTEAM BY PIO_PREINIT 
+
+PIO_INITDEV:
+	; TEST FOR -1 (FFFF) WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
+	LD	A,D			; TEST DE FOR
+	AND	E			; ... VALUE OF -1
+	INC	A			; ... SO Z SET IF -1
+	JR	NZ,PIO_INITDEV1		; IF DE == -1, REINIT CURRENT CONFIG
+PIO_INITDEV0:
+	; LOAD EXISTING CONFIG (DCW) TO REINIT
+	LD	E,(IY+4)		; LOW BYTE
+	LD	D,(IY+5)		; HIGH BYTE	
+;
+PIO_INITDEV1:				; WHICH DEVICE TYPE?
+	LD	A,(IY+1)
+	CP	PIO_ZPIO		
+	JR	Z,SETPIO0
+	CP	PIO_8255
+	JP	Z,SET_8255
+	CP	PIO_PORT
+	JP	Z,SET_PORT
+BAD_SET:OR	$FF			; UNKNOWN DEVICE
+	RET
+
+SETPIO0:LD	A,E			; GET MODE 
+	AND	11000000B		; BITS (B7B6)
+	CP	10000000B		; IS IT BIDIR?
+	JR	NZ,SETPIO1
+	LD	A,(IY+2)		; GET CHANNEL
+	OR	A
+	JR	NZ,BAD_SET		; CAN'T DO ON CH1
+
+	; VALIDATE INTERRUPT REQUEST
+	; GRANT INTERRUPT IF THERE IS A FREE INTERRUPT
+	; GRANT INTERRUPT IF AN INTERRUPT IS ALREADY ALLOCATED TO THIS UNIT
+
+SETPIO1:PUSH	AF		;D
+	LD	A,'['		;D
+	CALL	COUT		;D
+	LD	A,(IY)		;D
+	CALL	PRTHEXBYTE	;D
+	LD	A,']'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+
+	BIT	2,E			; SKIP IF WE ARE NOT REQUESTING 
+	JP	Z,SETPIO2		; AN INTERRUPT
+
+	PRTS("[INTREQ]$")	;D
+
+;	LD	A,(IY+4)		; GET CURRENT INTERRUPT SETTING
+;	BIT	2,A			; SKIP IF IT IS ALREADY
+;	JP	NZ,SETPIO2		; ALLOCATED TO THIS UNIT
+
+	LD	A,(INT_ALLOC)		; WE NEED TO ALLOCATE AN
+	CP	INT_ALLOW		; INTERRUPT. DO WE HAVE 
+	JR	NC,BAD_SET		; ONE FREE?
+
+	PRTS("[ALLOCINT]$")	;D
+
+	; WHICH INTERRUPT IS FREE ?
+	; SCAN THROUGH THE CFG TABLES
+	; AND FIND A FREE ONE
+
+	PUSH	AF			; NESTED LOOP
+	LD	DE,CFG_SIZ		; OUTSIDE LOOP IS INTERRUPT
+	LD	B,INT_ALLOW		; INSIDE LOOP IS DEVICE
+SETPIOP: LD	C,B 
+	 DEC	C
+	 PUSH	BC
+	 LD	B,PIO_CNT
+	 LD	HL,PIO_CFG+4
+SETPIOX: LD	A,(HL)
+	 BIT	2,A			; JUMP TO NEXT DEVICE
+	 JR	Z,SETPIOY		; IF NO INTERRUPT ON 
+	 AND	00000011B		; THIS DEVICE
+
+	 CP	C			; IF WE MATCH AN INTERRUPT HERE THEN IT IS NOT FREE.
+	 JR	NZ,SETPIOY		; SO EXIT INSIDE LOOP AND TRY NEXT INTERRUPT
+
+	 XOR	A			; WE MATCH INT 0 - IF WE ARE CHECKING FOR IT THEN
+	 OR	C			; WE REGARD IS AS FREE.
+	 JR	NZ,SETPIOZ
+
+SETPIOY: ADD	HL,DE			
+	 DJNZ	SETPIOX
+
+	 JR	SETPIOQ			; WE GET HERE IF THE CURRENT INTERRUPT
+					; WAS NOT MATCHED SO IT IS FREE
+SETPIOZ: POP	BC
+	DJNZ	SETPIOP
+	POP	AF
+
+	PRTS("[NONEFREE]$")
+	RET
+
+SETPIOQ:PUSH	AF			; AVAILABLE INTERRUPT IS IN C
+	PRTS("[FREE]=$")
+	LD	A,C
+	CALL	PRTHEXBYTE
+	POP	AF
+
+	POP	AF			
+	POP	AF
+
+SETPIOR:LD	HL,INT_ALLOC		; INCREASE THE COUNT
+	INC	(HL)			; OF USED INTERRUPTS
+	LD	A,(HL)
+
+;	LD	A,(IY)			; IS THIS UNIT 
+;	INC	A			; UNITIALIZED?
+;	JR	Z,SETPIO6
+
+	LD	A,(IY+4)		; IT IS UNITIALIZED SO
+	OR	C			; SAVE THE ALLOCATES 
+	LD	(IY+4),A		; INTERRUPT
+;
+; FOR THIS DEVICE AND INTERRUPT, UPDATE THE CONFIG TABLE FOR THIS DEVICE.
+; PIO_IN, PIO_OUT, PIO_IST, PIO_OST ENTRIES NEED TO BE REDIRECTED.
+; INTERRUPT VECTOR NEEDS TO BE UPDATED
+;
+	LD	A,(IY+0)
+	LD	HL,0
+	; SETUP PIO INTERRUPT VECTOR IN IVT
+	LD	HL,HBX_IV09+1
+
+;	CALL	SPK_BEEP
+;
+SETPIO6:RET	
+
+	; EXIT WITH FREE INTERRUPT IN C
+
+	LD	A,C
+	LD	(INT_ALLOC),A
+
+	LD	A,E
+	AND	11000000B
+	OR	00000100B
+	OR	C
+	LD	E,A
+	LD	(IY+5),A
+;
+	; TODO: DEALLOCATE AN INTERRUPT
+;
+;	LD	A,(INT_ALLOC)
+;	DEC	A
+;	LD	(INT_ALLOC),A
+;
+SETPIO2:
+
+;	DE CONTAINS THE MODE IF INTERRUPT ROUTINE SKIPPED
+
+	PRTS("[NOINTREQ]$")	;D
+
+;	LD	A,(IY+4)
+	LD	A,E			; GET MODE AND CREATE COMMAND
+	AND	11000000B		; $B0
+	OR	00001111B		; $0F	
+
+	LD	C,(IY+3)		; GET DATA PORT
+	INC	C			; POINT TO CMD
+	INC	C			; PORT	
+	OUT	(C),A			; SET MODE
+	CP	(M_BitCtrl | $0F)	; IF MODE 3
+	JR	NZ,SETPIO3		
+	LD	A,(IY+5)		; SET I/O DIRECTION
+	OUT	(C),A			; FOR MODE 3
+
+SETPIO3:; INTERUPT HANDLING
+
+	JP	SETPIO4
+
+	; SETUP THE INTERRUPT VECTOR
+
+	LD	A,E
+	AND	00000011B
+;	DEC	A			; INDEX INTO THE
+	ADD	A,A			; THE VECTOR TABLE
+	ADD	A,A			; 
+	LD	C,A
+	LD	B,0
+	LD	HL,HBX_IV09+1
+	ADD	HL,BC			; GET THE ADDRESS OF
+	PUSH	DE
+	LD	D,(HL)			; THAT INTERRUPT
+	INC	HL			; HANDLER
+	LD	E,(HL)
+	LD	HL,0	;HBX_IVT+IVT_PIO0	; POPULATE THE
+	LD	A,L			; GET LOW BYTE OF IVT ADDRESS
+	ADD	HL,BC			; INTERRUPT TABLE
+	LD	(HL),D			; WITH THE INTERRUPT
+	INC	HL			; HANDLER ADDRESS FOR
+	LD	(HL),E			; THIS UNIT
+	POP	DE
+	LD	HL,INT_ALLOC
+	LD	C,(HL)
+	LD	B,0
+	LD	HL,PRTTAB-1		; SAVE THE DATA	
+	ADD	HL,BC			; PORT FOR EACH INTERRUPT
+	LD	C,(IY+3)		
+	LD	(HL),C
+
+	INC	C			; POINT TO CMD PORT
+	INC	C
+	DI				; SET THE VECTOR ADDRESS
+	OUT	(C),A
+
+;	LD	A,10000011B		; ENABLE INTERRUPTS ON
+	OUT	(C),A			; THIS UNIT
+	EI	
+;	JR	GUD_SET
+;
+SETPIO4:LD	A,00000111B		; $07 
+	OUT	(C),A			; NO INTERRUPTS
+;
+;	SUCCESSFULL SO SAVE DEVICE CONFIGURATION WORD (DCW)
+;
+GUD_SET:LD	(IY+4),E		; LOW BYTE
+	LD	(IY+5),D		; HIGH BYTE	
+;
+;	UPDATE THE DEVICE TABLE WITH THE ADDRESSES FOR THE CORRECT ROUTINE.
+;
+	LD	A,E
+	AND	00000111B
+	LD	HL,INTMATRIX		; POINT TO EITHER THE INTERRUPT
+	JR	NZ, USEIM
+	LD	HL,POLMATRIX		; MATRIX OR THE POLLED MATRIX
+USEIM:	PUSH	HL	
+
+	PUSH	IY			; CALCULATE THE DESTINATION
+	POP	HL			; ADDRESS IN THE PIO_CFG TABLE
+	LD	BC,8			; FOR THE FOUR ADDESSES TO BE 
+	ADD	HL,BC			; COPIED TO 
+
+;	LD	B,0			; 00000000 CALCULATE THE SOURCE ADDRESS
+	LD	C,E			; XX?????? FROM THE MATRIX. EACH ENTRY 
+	SRL	C			; 0XX????? IN THE MATRIX IS 8 BYTES SO
+	SRL	C			; 00XX???? SOURCE = MATRIX BASE + (8 * MODE)
+	SRL	C			; 000XX???
+	POP	DE			; LOAD THE MATRIX BASE
+;	LD	DE,POLMATRIX
+	EX	DE,HL
+	ADD	HL,BC			; HL = SOURCE
+
+	LD	C,8			; COPY 8 BYTES
+	LDIR
+
+;	PUSH	IY
+;	POP	DE
+;	CALL	DUMP_BUFFER
+
+	XOR	A
+	RET
+
+PRTTAB:	.DB	0
+	.DB	0
+	.DB	0
+	.DB	0
+;
+;-----------------------------------------------------------------------------
+;
+; INPUT INTERRUPT VECTOR MACRO AND DEFINITION FOR FOUR PORTS
+;
+#DEFINE	PIOMIVT(PIOIN,PIOIST,PIOPRT) 		\
+#DEFCONT ;\
+#DEFCONT ;	RETURN WITH ERROR IF THERE IS	\
+#DEFCONT ;	ALREADY	A CHARACTER IN BUFFER	\
+#DEFCONT ;\
+#DEFCONT ;	OTHERWISE CHANGE THE STATUS TO	\
+#DEFCONT ;	SHOW THERE IS ONE CHARACTER IN	\
+#DEFCONT ;	THE BUFFER AND READ IT IN AND	\
+#DEFCONT ;	AND STORE IT.RETURN GOOD STATUS.\
+#DEFCONT ;\
+#DEFCONT \	LD	A,(_CIST)
+#DEFCONT \	OR	A
+#DEFCONT \	JR	NZ,_OVFL
+#DEFCONT \	LD	A,(PIOPRT)
+#DEFCONT \	LD	C,A
+#DEFCONT \	LD	A,1
+#DEFCONT \	LD	(_CIST),A
+#DEFCONT \	IN	A,(C)
+#DEFCONT \	LD	(_CICH),A
+#DEFCONT \	OR	$FF
+#DEFCONT \	RET
+#DEFCONT \_OVFL:XOR	A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT \PIOIN:CALL	PIOIST
+#DEFCONT \	JR	Z,PIOIN
+#DEFCONT \	LD	A,(_CICH)
+#DEFCONT \	LD	E,A
+#DEFCONT \	XOR	A
+#DEFCONT \	LD	(_CIST),A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	If THERE A CHARACTER		\
+#DEFCONT ;	AVAILABLE? RETURN NUMBER	\
+#DEFCONT ;	IN A - 0 OR 1			\
+#DEFCONT ;\
+#DEFCONT \PIOIST:LD	A,(_CIST)
+#DEFCONT \	AND	00000001B
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	CIST :	01 = CHARACTER READY ELSE NOT READY	\
+#DEFCONT ;	CISH :	CHARACTER STORED BY INTERRUPT		\
+#DEFCONT ;\
+#DEFCONT \_CIST	.DB	00
+#DEFCONT \_CICH	.DB	00
+;
+PIOIVT0:.MODULE	PIOIVT0
+PIOMIVT(PIO0IN,PI0_IST,PRTTAB+0)
+PIOIVT1:.MODULE PIOIVT1
+PIOMIVT(PIO1IN,PI1_IST,PRTTAB+1)
+PIOIVT2:.MODULE PIOIVT2
+PIOMIVT(PIO2IN,PI2_IST,PRTTAB+2)
+PIOIVT3:.MODULE PIOIVT3
+PIOMIVT(PIO3IN,PI3_IST,PRTTAB+3)
+;
+;-----------------------------------------------------------------------------
+;
+; OUTPUT INTERRUPT VECTOR MACRO AND DEFINITION FOR FOUR PORTS
+;
+; AN INTERRUPT IS GENERATED WHEN THE RECEIVING DEVICE CAN ACCEPT A CHARACTER
+;
+#DEFINE	PIOMOVT(PIOOUT,PIOOST,PIOPRT) 		\
+#DEFCONT ;\
+#DEFCONT ;	RETURN IF WE ARE WAITING FOR A	\
+#DEFCONT ;	CHARACTER (COST = 00)		\
+#DEFCONT ;\
+#DEFCONT ;	IF ZERO CHARACTERS READY 
+#DEFCONT ;	(COST = 01) CHANGE STATUS TO	\
+#DEFCONT ;	WAITING FOR CHARACTER (COST 00)	\
+#DEFCONT ;\
+#DEFCONT ;	IF A CHARACTER IS READY THEN	\
+#DEFCONT ;	OUTPUT AND CHANGE STATUS TO	\
+#DEFCONT ;	ZERO CHARACTERS READY		\
+#DEFCONT ;\
+#DEFCONT \	LD	A,(_COST)
+#DEFCONT \ 	DEC	A
+#DEFCONT \	RET	M
+#DEFCONT \	JR	Z,_WFC
+#DEFCONT \	LD	A,(_COCH)
+#DEFCONT \	LD	E,A
+#DEFCONT \_ONOW:LD	A,(PIOPRT)
+#DEFCONT \	LD	C,A
+#DEFCONT \	OUT	(C),E
+#DEFCONT \ 	LD	A,1
+#DEFCONT \_WFC:	LD	(_COST),A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	WAIT FOR SPACE FOR THE CHARACTER\
+#DEFCONT ;	IF WE ARE WAITING FOR A		\
+#DEFCONT ;	CHARACTRE THEN OUTPUT IT NOW	\
+#DEFCONT ;	OTHERWISE STORE IT UNTIL THE	\
+#DEFCONT ;	INTERRUPT CALLS FOR IT		\
+#DEFCONT ;\
+#DEFCONT \PIOOUT:LD	A,(_COST)
+#DEFCONT \	CP	2
+#DEFCONT \	JR	C,_ONOW
+#DEFCONT \	LD	A,E
+#DEFCONT \	LD	(_COCH),A
+#DEFCONT \	LD	A,2
+#DEFCONT \	LD	(_COST),A
+#DEFCONT \	JR	PIOOUT
+#DEFCONT ;\
+#DEFCONT ;	RETURN WITH NUMBER OF		\
+#DEFCONT ;	CHARACTERS AVAILABLE 0 or 1	\
+#DEFCONT ;\
+#DEFCONT \PIOOST:LD	A,(_COST)
+#DEFCONT \	DEC	A
+#DEFCONT \	DEC	A
+#DEFCONT \	RET	Z
+#DEFCONT \	LD	A,1
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	COST :	00 WAITING FOR CHARACTER\
+#DEFCONT ;		01 ZERO CHARACTERS READY\
+#DEFCONT ;		02 ONE CHARACTER READY	\
+#DEFCONT ;	COCH :	CHARACTER TO OUTPUT	\
+#DEFCONT ;\
+#DEFCONT \_COST	.DB	01
+#DEFCONT \_COCH	.DB	00
+;
+PIOOVT0:.MODULE	PIOOVT0
+PIOMOVT(PIO0OUT,PI0_OST,PRTTAB+0)
+PIOOVT1:.MODULE PIOOVT1
+PIOMOVT(PIO1OUT,PI1_OST,PRTTAB+1)
+PIOOVT2:.MODULE PIOOVT2
+PIOMOVT(PIO2OUT,PI2_OST,PRTTAB+2)
+PIOOVT3:.MODULE PIOOVT3
+PIOMOVT(PIO3OUT,PI3_OST,PRTTAB+3)
+;
+;-----------------------------------------------------------------------------
+;
+; NON INTERRUPT OUTPUT ROUTINE - SHARED
+;
+; INPUT WILL ALWAYS RETURN ERROR, CHARACTER RETURNED IS UNDEFINED.
+; OUTPUT WILL ALWAYS RETURN SUCCESS
+; INPUT-STATUS WILL ALWAYS RETURN 0 CHARACTERS IN BUFFER.
+; OUTPUT-STATUS WILL ALWAYS RETURN 1 CHARACTER SPACE IN BUFFER.
+
+PIOSHO_IN:
+	LD	A,1
+	RET
+;
+PIOSHO_OUT:	
+	LD	C,(IY+3)
+	OUT	(C),E
+	XOR	A
+	RET
+;
+PIOSHO_IST:	XOR	A
+	RET
+;
+PIOSH_OST:	
+	LD	A,1
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; NON INTERRUPT INPUT ROUTINE - SHARED
+;
+; INPUT WILL ALWAYS A CHARACTER AND SUCCESS.
+; OUTPUT WILL ALWAYS RETURN FAILURE
+; INPUT STATUS WILL ALWAYS RETURN 1 CHARACTER IN BUFFER.
+;OUTPUT-STATUS WILL ALWAYS RETURN 0 CHARACTER SPACE IN BUFFER.
+;
+PIOSHI_IN:
+	LD	C,(IY+3)
+	IN	A,(C)
+	LD	E,A
+	XOR	A
+	RET
+;
+PIOSHI_OUT:
+	LD	A,1
+	RET
+;
+PIOSH_IST:
+	LD	A,1
+	RET
+;
+PIOSHI_OST:
+	XOR	A
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; ON ENTRY IY POINTS TO THE DEVICE RECORD. GET AND RETURN THE CONFIGURATION WORD IN DE
+;
+PIO_QUERY:
+PPI_QUERY:
+	LD	E,(IY+4)		; FIRST CONFIG BYTE TO E
+	LD	D,(IY+5)		; SECOND CONFIG BYTE TO D
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; ON ENTRY IY POINTS TO THE DEVICE RECORD. FOR CHARACTER DEVICES BIT 6 OF ATTRIBUTE
+; INDICATES PARALLEL PORT IF 1 SO WE SET IT. COMMON TO ALL PORTS
+;
+PIO_DEVICE:
+PPI_DEVICE:
+	LD	D,CIODEV_PIO		; D := DEVICE TYPE
+	LD	E,(IY)			; E := PHYSICAL UNIT
+	LD	C,$40			; C := ATTRIBUTE
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,(IY+3)		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+INTMATRIX:
+	.DW	PIO0IN,	PIO0OUT, PI0_IST, PI0_OST
+	.DW	PIO1IN,	PIO1OUT, PI1_IST, PI1_OST
+	.DW	PIO2IN,	PIO2OUT, PI2_IST, PI2_OST
+	.DW	PIO3IN,	PIO3OUT, PI3_IST, PI3_OST
+POLMATRIX:
+	.DW	PIOSHO_IN, PIOSHO_OUT, PIOSHO_IST, PIOSH_OST	; OUTPUT
+	.DW	PIOSHI_IN, PIOSHI_OUT, PIOSH_IST,  PIOSHI_OST	; INPUT
+	.DW	0,0,0,0						; BIDIR	
+	.DW	0,0,0,0						; BIT MODE
+
+SET_8255:
+	RET	
+;
+SET_BYE:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; ------------------------------------
+; i8255 FUNCTION TABLE ROUTINES
+;-------------------------------------
+	
+PPI_IN:
+	XOR	A			; SIGNAL SUCCESS
+	RET	
+;
+PPI_OUT:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;	
+PPI_IST:
+	RET	
+;	
+PPI_OST:
+	RET
+;
+; PIO_INITDEV - Configure device.
+; If DE = FFFF then extract the configuration information from the table of devices and program the device using those settings.
+; Otherwise use the configuration information in DE to program those settings and save them in the device table
+
+PPI_INITDEV:
+	XOR	A			; SIGNAL SUCCESS
+	RET	
+PPI_INT:OR	$FF			; NZ SET TO INDICATE INT HANDLED
+	RET
+;	
+PIO_PRTCFG:
+	; ANNOUNCE PORT
+	CALL	NEWLINE			; FORMATTING
+	PRTS("PIO$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": IO=0x$")		; FORMATTING
+	LD	A,(IY+3)		; GET BASE PORT
+	CALL	PRTHEXBYTE		; PRINT BASE PORT
+;
+	; PRINT THE PIO TYPE
+	CALL	PC_SPACE		; FORMATTING
+	LD	A,(IY+1)		; GET PIO TYPE BYTE
+	LD	DE,PIO_TYPE_STR		; POINT HL TO TYPE MAP TABLE
+	CALL	PRTIDXDEA
+
+	; ALL DONE IF NO PIO WAS DETECTED
+	LD	A,(IY+1)		; GET PIO TYPE BYTE
+	OR	A			; SET FLAGS
+	RET	Z			; IF ZERO, NOT PRESENT
+;
+	PRTS(" MODE=$")			; FORMATTING
+	LD	E,(IY+4)		; LOAD CONFIG
+	LD	D,(IY+5)		; ... WORD TO DE
+	CALL	PS_PRTPC0		; PRINT CONFIG
+;
+	LD	A,(IY+4)		; PRINT
+	BIT	2,A			; ALLOCATED
+	JR	Z,NOINT			; INTERRUPT
+	PRTS("/i$")
+	LD	A,(IY+4)
+	AND	00000011B
+	CALL	PRTDECB
+NOINT:	XOR	A
+	RET
+;
+; WORKING VARIABLES
+;
+PIO_DEV		.DB	0		; DEVICE NUM USED DURING INIT
+;	
+; DESCRIPTION OF DIFFERENT PORT TYPES
+;
+PIO_TYPE_STR:
+		.TEXT	"<NOT PRESENT>$"	; IDX 0
+		.TEXT	"Zilog PIO$"		; IDX 1
+		.TEXT	"i8255 PPI$"		; IDX 2
+		.TEXT	"IO Port$"		; IDX 3
+;
+; Z80 PIO PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. TWO PORTS
+;
+;	32 BYTE DATA STRUCTURE FOR EACH PORT
+;
+;	.DB	0		; IY+0 CIO DEVICE NUMBER 			(SET DURING PRE-INIT, THEN FIXED)
+;	.DB	0		; IY+1 PIO TYPE 				(SET AT ASSEMBLY, FIXED)
+;	.DB	0		; IY+2 PIO CHANNEL				(SET AT ASSEMBLY, FIXED)
+;	.DB	PIOBASE+2	; IY+3 BASE DATA PORT				(SET AT ASSEMBLY, FIXED)
+;	.DB	0		; IY+4 SPW - MODE 3 I/O DIRECTION BYTE		(SET AT ASSEMBLE, SET WITH INIT)
+;	.DB	0		; IY+5 SPW - MODE, INTERRUPT			(SET AT ASSEMBLY, SET WITH INIT)
+;	.DW	0		; IY+6/7 FUNCTION TABLE				(SET AT ASSEMBLY, SET DURING PRE-INIT AND AT INIT)
+;	.DW	PIO_IN		; IY+8  ADDR FOR DEVICE INPUT			(SET WITH INIT)
+;	.DW	PIO_OUT		; IY+10 ADDR FOR DEVICE OUTPUT			(SET WITH INIT)
+;	.DW	PIO_IST		; IY+12 ADDR FOR DEVICE INPUT STATUS		(SET WITH INIT)
+;	.DW	PIO_OST		; IY+14 ADDR FOR DEVICE OUTPUT STATUS		(SET WITH INIT)
+;	.DW	PIO_INITDEV	; IY+16 ADDR FOR INITIALIZE DEVICE ROUTINE	(SET AT ASSEMBLY, FIXED)
+;	.DW	PIO_QUERY	; IY+18 ADDR FOR QUERY DEVICE RECORD ROUTINE	(SET AT ASSEMBLY, FIXED)
+;	.DW	PIO_DEVICE	; IY+20 ADDR FOR DEVICE TYPE ROUTINE		(SET AT ASSEMBLY, FIXED)
+;	.FILL	10
+;
+;	SETUP PARAMETER WORD:
+;
+;	+-------------------------------+ +-------+-----------+---+-------+
+;	|         BIT CONTROL           | | MODE  |           | A |  INT  |
+;	+-------------------------------+ --------------------+-----------+
+;	 F   E   D   C   B   A   9   8     7   6   5   4   3   2   1   0
+;	-- MSB (D REGISTER) --           -- LSB (E REGISTER) --
+;
+;
+; 	MSB = BIT CONTROL MAP USE IN MODE 3 
+;
+; 	MODE B7 B6 =	00 Mode 0 Output
+;			01 Mode 1 Input
+;			10 Mode 2 Bidir
+;			11 Mode 3 Bit Mode
+;
+;	INTERRUPT ALLOCATED B2	= 0 NOT ALLOCATED
+;				= 1 IS ALLOCATED
+;
+;	WHICH IVT IS ALLOCATES B1 B0	00 IVT_PIO0
+;					01 IVT_PIO1
+;					10 IVT_PIO2
+;					11 IVT_PIO3
+;	
+#DEFINE	DEFPIO(MPIOBASE,MPIOCH0,MPIOCH1,MPIOCH0X,MPIOCH1X,MPIOIN0,MPIOIN1) \
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_ZPIO
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	MPIOBASE
+#DEFCONT \ .DB	(MPIOCH0|MPIOIN0)
+#DEFCONT \ .DB	MPIOCH0X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
+#DEFCONT \ .FILL 2	
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_ZPIO
+#DEFCONT \ .DB	1
+#DEFCONT \ .DB	MPIOBASE+1
+#DEFCONT \ .DB	(MPIOCH1|MPIOIN1)
+#DEFCONT \ .DB	MPIOCH1X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
+#DEFCONT \ .FILL 2	
+;
+; i8255 PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. THREE PORTS
+;
+#DEFINE	DEFPPI(MPPIBASE,MPPICH1,MPPICH2,MPPICH3,MPPICH1X,MPPICH2X,MPPICH3X) \
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_8255
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	MPPIBASE
+#DEFCONT \ .DB	(MPPICH1|00001000B)
+#DEFCONT \ .DB	MPPICH1X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 2
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_8255
+#DEFCONT \ .DB	1
+#DEFCONT \ .DB	MPPIBASE+2
+#DEFCONT \ .DB	(MPPICH2|00010000B)
+#DEFCONT \ .DB	MPPICH2X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 2
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_8255
+#DEFCONT \ .DB	2
+#DEFCONT \ .DB	MPPIBASE+4
+#DEFCONT \ .DB	(MPPICH3|00100000B)
+#DEFCONT \ .DB	MPPICH3X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 2
+;
+; HERE WE ACTUALLY DEFINE THE HARDWARE THAT THE HBIOS CAN ACCESS
+; THE INIT ROUTINES READ AND SET THE INITIAL MODES FROM THIS INFO
+;
+PIO_CFG:
+;
+#IF	PIO_4P
+DEFPIO(PIO4BASE+0,M_Output,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+4,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+8,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+12,M_Output,M_Output,M_BitAllOut,M_Output,INT_N,INT_N)
+#ENDIF
+#IF	PIO_ZP
+DEFPIO(PIOZBASE+0,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIOZBASE+4,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+#ENDIF
+; PIO_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC))
+
+#IF 	PIO_SBC
+DEFPPI(PIOSBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut)
+#ENDIF
+;
+PIO_CNT	.EQU	($ - PIO_CFG) / CFG_SIZ 	
+;
+;-------------------------------------------------------------------
+; WHEN WE GET HERE IY POINTS TO THE PIO_CFG TABLE WE ARE WORKING ON.
+; C IS THE UNIT NUMBER
+;-------------------------------------------------------------------
+;
+;PIO_INITUNIT:
+;	LD	A,C			; SET THE UNIT NUMBER
+;	LD	(IY),A	
+;
+;	LD	DE,-1			; LEAVE CONFIG ALONE
+;	CALL	PIO_INITDEV		; IMPLEMENT IT AND RETURN
+;	XOR	A			; SIGNAL SUCCESS
+;	RET				; AND RETURN
+;
+PIO_INIT:
+;	CALL	SPK_BEEP
+	LD	B,PIO_CNT		; COUNT OF POSSIBLE PIO UNITS
+	LD	C,0			; INDEX INTO PIO CONFIG TABLE
+PIO_INIT1:
+	PUSH	BC			; SAVE LOOP CONTROL
+	
+;	LD	A,C			; PHYSICAL UNIT TO A
+;	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+;	RLCA				; ...
+;	RLCA				; ... TO GET OFFSET INTO CFG TABLE
+;	RLCA
+;;	RLCA
+;	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+;	PUSH	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	POP	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	PUSH	HL			; COPY CFG DATA PTR
+;	POP	IY			; ... TO IY
+;	POP	IY			; ... TO IY
+
+	CALL	IDXCFG
+
+	LD	A,(IY+1)		; GET PIO TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,PIO_PRTCFG		; PRINT IF NOT ZERO
+	
+;	PUSH	DE	
+;	LD	DE,$FFFF		; INITIALIZE DEVICE/CHANNEL
+;	CALL	PIO_INITDEV		; BASED ON DPW
+;	POP	DE
+
+	POP	BC			; RESTORE LOOP CONTROL
+	INC	C			; NEXT UNIT
+	DJNZ	PIO_INIT1		; LOOP TILL DONE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+SET_PORT:
+	; DEVICE TYPE IS I/O PORT SO JUST WRITE $00 TO IT
+	LD	C,(IY+3)
+	OUT	(C),A
+	XOR	A
+	RET

Source/HBIOS/std.asm

@@ -193,6 +193,7 @@ AYMODE_RCZ80	.EQU	3		; RC2014 SOUND MODULE BY ED BRINDLEY ON Z80
 AYMODE_RCZ180	.EQU	4		; RC2014 SOUND MODULE BY ED BRINDLEY ON Z180
 AYMODE_MSX	.EQU	5		; RC2014 SOUND MODULE REV6 BY ED BRINDLEY ON Z80/Z180 AT MSX PORTS
 AYMODE_LINC	.EQU	6		; LINC Z50 AY SOUND CARD
+AYMODE_MBC	.EQU	7		; MBC SOUND BOARD
 ;
 ; SN SOUND CHIP MODE SELECTIONS
 ; 
@@ -513,13 +514,13 @@ BID_RAMN	.EQU	(BID_RAM0 + ((RAMSIZE / 32) - 1))
 ;
 BID_RAMD0	.EQU	BID_RAM0	; FIRST RAM DRIVE BANK			 ^  RAM
 BID_RAMDN	.EQU	BID_RAMN - TOT_RAM_RB	; LAST RAM DRIVE BANK		 |  DRIVE
-;					; OS BUFFERS CP/M3?			-+ THESE
-;					; OS BUFFERS CP/M3?			 | MAKE
-;					; OS BUFFERS CP/M3?			 | UP
-;					; OS BUFFERS CP/M3?			 | THE
-BID_AUX		.EQU	BID_RAMN - 3	; AUX BANK (BPBIOS, ETC.)		 | 256KB
+;					; OS BUFFERS CP/M3?			-+ THESE	CPM3 BNK 5 (BUF)
+;					; OS BUFFERS CP/M3?			 | MAKE		CPM3 BNK 4 (BUF)
+;					; OS BUFFERS CP/M3?			 | UP		CPM3 BNK 3 (BUF)
+;					; OS BUFFERS CP/M3?			 | THE		CPM3 BNK 2 (BUF)
+BID_AUX		.EQU	BID_RAMN - 3	; AUX BANK (BPBIOS, ETC.)		 | 256KB	CPM3 BNK 1 (TPA)
 BID_BIOS	.EQU	BID_RAMN - 2	; BIOS BANK				 | RESERVED
-BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)		 | RAM
+BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)		 | RAM		CPM3 BNK 0 (OS)
 BID_COM		.EQU	BID_RAMN - 0	; COMMON BANK, UPPER 32K		-+ BANKS
 BID_BOOT	.EQU	BID_ROM0 + 0	; BOOT BANK				-+ THESE MAKE
 BID_IMG0	.EQU	BID_ROM0 + 1	; ROM LOADER AND FIRST IMAGES BANK	 | UP THE 128KB
@@ -528,6 +529,10 @@ BID_IMG2	.EQU	BID_ROM0 + 3	; NETWORK BOOT				-+ ROM BANKS
 BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK			 |  ROM
 BID_ROMDN	.EQU	BID_ROMN	; LAST ROM DRIVE BANK			 V  DRIVE
 ;
+#IF (ROMSIZE == 0)
+BID_BOOT	.SET	BID_RAM0	; SPECIAL CASE ROM-LESS SYSTEM
+#ENDIF
+;
 #IF (BIOS == BIOS_WBW)
 ;
   #IF (!MDRAM)

Source/Images/Build.cmd

@@ -23,6 +23,7 @@ call BuildDisk.cmd nzcom hd wbw_hd512 ..\zsdos\zsys_wbw.sys || exit /b
 call BuildDisk.cmd cpm3 hd wbw_hd512 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 hd wbw_hd512 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 hd wbw_hd512 || exit /b
+call BuildDisk.cmd dos65 hd wbw_hd512 ..\zsdos\zsys_wbw.sys || exit /b
 
 if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd512 || exit /b
 

Source/Images/Makefile

@@ -16,7 +16,7 @@ HD512PREFIX =
 HD1024PREFIX = hd1024_prefix.dat
 
 OBJECTS = $(FDIMGS)
-OBJECTS += $(HD512IMGS) hd512_combo.img $(HD512PREFIX)
+OBJECTS += $(HD512IMGS) hd512_dos65.img hd512_combo.img $(HD512PREFIX)
 OBJECTS += $(HD1024IMGS) hd1024_combo.img $(HD1024PREFIX)
 
 OTHERS = blank144 blankhd512 blankhd1024
@@ -71,7 +71,7 @@ blankhd1024:
 	@sys= ; \
 	case $@ in \
 		(*cpm22*) sys=../CPM22/cpm_wbw.sys;; \
-		(*zsdos* | *nzcom*) sys=../ZSDOS/zsys_wbw.sys;; \
+		(*zsdos* | *nzcom* | *dos65*) sys=../ZSDOS/zsys_wbw.sys;; \
 		(*cpm3*) sys=../CPM3/cpmldr.sys;; \
 		(*zpm3*) sys=../ZPM3/zpmldr.sys;; \
 	esac ; \

Source/Images/d_dos65/u0/dos65.hex

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Source/Images/hd_dos65.txt

@@ -0,0 +1,3 @@
+#
+# Nothing to add for now
+#

Source/ZRC/Build.cmd

@@ -1,8 +1,38 @@
 @echo off
 setlocal
 
-if not exist ..\..\Binary\RCZ80_zrc.rom goto :eof
+set TOOLS=../../Tools
 
-copy /b zrc_cfldr.bin + zrc_ptbl.bin + zrc_fill_1.bin + zrc_mon.bin + zrc_fill_2.bin + ..\..\Binary\RCZ80_zrc.rom + zrc_fill_3.bin ..\..\Binary\hd1024_zrc_prefix.dat || exit /b
+set PATH=%TOOLS%\srecord;%PATH%
 
-copy /b ..\..\Binary\hd1024_zrc_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_combo.img || exit /b
+if exist ..\..\Binary\RCZ80_zrc.rom call :build_zrc
+
+if exist ..\..\Binary\RCZ80_zrc_ram.rom call :build_zrc_ram
+
+goto :eof
+
+:build_zrc
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1024_zrc_prefix.dat
+
+copy /b ..\..\Binary\hd1024_zrc_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_combo.img || exit /b
+
+goto :eof
+
+:build_zrc_ram
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1024_zrc_ram_prefix.dat
+
+copy /b ..\..\Binary\hd1024_zrc_ram_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_ram_combo.img || exit /b
+
+goto :eof

Source/ZRC/Makefile

@@ -1,6 +1,9 @@
 HD1024ZRCPREFIX = hd1024_zrc_prefix.dat
 HD1024ZRCCOMBOIMG = hd1024_zrc_combo.img
+HD1024ZRCRAMPREFIX = hd1024_zrc_ram_prefix.dat
+HD1024ZRCRAMCOMBOIMG = hd1024_zrc_ram_combo.img
 ZRCROM = ../../Binary/RCZ80_zrc.rom
+ZRCRAMROM = ../../Binary/RCZ80_zrc_ram.rom
 HD1024IMGS = ../../Binary/hd1024_cpm22.img ../../Binary/hd1024_zsdos.img ../../Binary/hd1024_nzcom.img \
 	../../Binary/hd1024_cpm3.img ../../Binary/hd1024_zpm3.img ../../Binary/hd1024_ws4.img
 
@@ -10,6 +13,10 @@ ifneq ($(wildcard $(ZRCROM)),)
 	OBJECTS += $(HD1024ZRCPREFIX) $(HD1024ZRCCOMBOIMG)
 endif
 
+ifneq ($(wildcard $(ZRCRAMROM)),)
+	OBJECTS += $(HD1024ZRCRAMPREFIX) $(HD1024ZRCRAMCOMBOIMG)
+endif
+
 DEST=../../Binary
 
 TOOLS = ../../Tools
@@ -19,7 +26,23 @@ include $(TOOLS)/Makefile.inc
 DIFFPATH = $(DIFFTO)/Binary
 
 $(HD1024ZRCPREFIX):
-	cat zrc_cfldr.bin zrc_ptbl.bin zrc_fill_1.bin zrc_mon.bin zrc_fill_2.bin $(ZRCROM) zrc_fill_3.bin >$@
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1024ZRCRAMPREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
 
 $(HD1024ZRCCOMBOIMG): $(HD1024ZRCPREFIX) $(HD1024IMGS)
-	cat $^ > $@
+	cat $^ > $@
+
+$(HD1024ZRCRAMCOMBOIMG): $(HD1024ZRCRAMPREFIX) $(HD1024IMGS)
+	cat $^ > $@

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.158"
+#DEFINE BIOSVER	"3.1.1-pre.161"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.158"
+	db	"3.1.1-pre.161"
 	endm

Tools/Makefile.inc

@@ -97,10 +97,10 @@ CPM=$(TOOLS)/cpm/bin80/
 %.rel: %.z80
 	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/MF
 
-%.hex: %.z80
-	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF
+#%.hex: %.z80
+#	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF
 
-%.hex: %.180
+%.hex: %.z80
 	$(ZXCC) $(CPM)/SLR180 -$(basename $<)/HF
 
 %.rel: %.azm
@@ -112,6 +112,9 @@ CPM=$(TOOLS)/cpm/bin80/
 %.rel: %.mac
 	$(ZXCC) $(CPM)/M80 -=$(basename $<)
 
+%.com: %.rel
+	$(ZXCC) $(CPM)/L80 -$(basename $<),$(basename $<).com/n/e
+
 ifeq ($(UNAME), Linux)
 %.eeprom: %.spin
 	$(BSTC) -e -l $<

Tools/unix/zxcc/Build-OW.cmd

@@ -1,21 +0,0 @@
-@echo off
-setlocal
-
-::
-:: Edit WATCOM variable below as needed for your environment
-::
-set WATCOM=..\..\Tools\WATCOM2
-
-set PATH=%WATCOM%\BINNT;%WATCOM%\BINW;%PATH%
-set EDPATH=%WATCOM%\EDDAT
-set INCLUDE=%WATCOM%\H;%WATCOM%\H\NT
-
-copy config.h.windows config.h
-
-cl /Fe"zxcc.exe" zxcc.c cpmdrv.c cpmglob.c cpmparse.c cpmredir.c drdos.c util.c track.c xlt.c zxbdos.c zxcbdos.c zxdbdos.c z80.c
-if errorlevel 1 exit /b 255
-
-cl /Fe"zxccdbg.exe" /DDEBUG zxcc.c cpmdrv.c cpmglob.c cpmparse.c cpmredir.c drdos.c util.c track.c xlt.c zxbdos.c zxcbdos.c zxdbdos.c z80.c
-if errorlevel 1 exit /b 255
-
-copy cpm\bios.bin .

Tools/unix/zxcc/Build-VC.cmd

@@ -1,25 +0,0 @@
-@echo off
-setlocal
-
-::
-:: Visual Studio x86 Native Tools Command Prompt is assumed
-::
-
-:: Below configures VS2012 to target Windows XP.
-:: Not sure if it will work in later versions of VS, but seems
-:: to do no harm.
-set INCLUDE=%ProgramFiles(x86)%\Microsoft SDKs\Windows\7.1A\Include;%INCLUDE%
-set PATH=%ProgramFiles(x86)%\Microsoft SDKs\Windows\7.1A\Bin;%PATH%
-set LIB=%ProgramFiles(x86)%\Microsoft SDKs\Windows\7.1A\Lib;%LIB%
-set CL=/D_USING_V110_SDK71_;%CL%
-set LINK=/SUBSYSTEM:CONSOLE,5.01 %LINK%
-
-copy config.h.windows config.h
-
-cl -I. zxcc.c cpmdrv.c cpmglob.c cpmparse.c cpmredir.c drdos.c util.c xlt.c zxbdos.c zxcbdos.c zxdbdos.c z80.c dirent.c track.c
-if errorlevel 1 exit /b 255
-
-cl -I. /DDEBUG /Fe"zxccdbg.exe" zxcc.c cpmdrv.c cpmglob.c cpmparse.c cpmredir.c drdos.c util.c xlt.c zxbdos.c zxcbdos.c zxdbdos.c z80.c dirent.c track.c
-if errorlevel 1 exit /b 255
-
-copy cpm\bios.bin .

Tools/unix/zxcc/Clean.cmd

@@ -1,11 +0,0 @@
-@echo off
-setlocal
-
-if exist *.exe del *.exe
-if exist *.obj del *.obj
-if exist *.err del *.err
-if exist *.o del *.o
-if exist *.bin del *.bin
-if exist zxcc del zxcc
-if exist zxccdbg del zxccdbg
-if exist config.h del config.h

Tools/unix/zxcc/ReadMe.txt

@@ -84,3 +84,10 @@ January 9, 2022
 
 --WBW 9:34 AM 2/10/2022
 
+- Added a call to trackFile in fcb_close.  I think it was always
+  supposed to be there.  Was not causing any real problems other
+  than superfluous attempts by releaseFile to close files that
+  were already closed.
+  
+--WBW 3:58 PM 3/2/2022
+

Tools/unix/zxcc/cpmredir.c

@@ -204,6 +204,8 @@ cpm_word fcb_close(cpm_byte* fcb)
 	}
 #endif
 
+	trackFile(NULL, fcb, handle);
+
 	FCBRET(0);
 }
 

Tools/unix/zxcc/track.c

@@ -97,6 +97,8 @@
 
 #ifdef FILETRACKER
 
+#include "cpmint.h"
+
 typedef struct _track {
 	struct _track* next;
 	int handle;
@@ -115,10 +117,21 @@ static track_t* rmHandle(track_t* s) {
 
 void releaseFile(char* fname) {
 	track_t* s = (track_t*)&openFiles;
+	DBGMSGV("releaseFile: \"%s\"\n", fname);
 	while (s->next)
 		if (strcmp(s->next->fname, fname) == 0) {
-			close(s->next->handle);
-			Msg("releaseFile closed file \"%s\"\n", s->next->fname);
+			DBGMSGV("  closing file #%i: \"%s\"\n", s->next->handle, s->next->fname);
+#ifdef _WIN32
+			{
+				BOOL b;
+				b = CloseHandle((HANDLE)s->next->handle);
+				if (!b)
+					DBGMSGV("  failed to close file #%i (Error=%lu): %s\n", s->next->handle, GetLastError(), GetErrorStr(GetLastError()));
+			}
+#else
+			if (close(s->next->handle))
+				DBGMSGV("  failed to close file #%i (errno=%lu): %s\n", s->next->handle, errno, strerror(errno));
+#endif
 			s->next = rmHandle(s->next);
 		}
 		else
@@ -127,14 +140,24 @@ void releaseFile(char* fname) {
 
 int trackFile(char* fname, void* fcb, int fd) {
 	track_t* s = (track_t*)&openFiles;
-	Msg("trackFile: \"%s\", FCB=0x%X, Handle=%i\n", fname, (byte*)fcb - RAM, fd);
+	DBGMSGV("trackFile: \"%s\", FCB=0x%X, Handle=%i\n", fname, (byte*)fcb - RAM, fd);
 	while (s->next) {	/* find any existing fcb or fd */
 		if (s->next->fcb == fcb || s->next->handle == fd) {
 			if (s->next->handle != fd) {
-				close(s->next->handle);
-				Msg("  closed file \"%s\", Handle=%i\n", s->next->fname, s->next->handle);
+				DBGMSGV("  closing file #%i: \"%s\"\n", s->next->handle, s->next->fname);
+#ifdef _WIN32
+				{
+					BOOL b;
+					b = CloseHandle((HANDLE)s->next->handle);
+					if (!b)
+						DBGMSGV("  failed to close file #%i (Error=%lu): %s\n", s->next->handle, GetLastError(), GetErrorStr(GetLastError()));
+				}
+#else
+				if (close(s->next->handle))
+					DBGMSGV("  failed to close file #%i (errno=%lu): %s\n", s->next->handle, errno, strerror(errno));
+#endif
 			}
-			Msg("  released file \"%s\", Handle=%i\n", s->next->fname, s->next->handle);
+			DBGMSGV("  released file \"%s\", Handle=%i\n", s->next->fname, s->next->handle);
 			s->next = rmHandle(s->next);	/* release the tracker */
 		}
 		else

Tools/unix/zxcc/zxcc.c

@@ -306,6 +306,12 @@ int main(int ac, char** av)
 		fprintf(stderr, "Could not initialise CPMREDIR library\n");
 		zxcc_exit(1);
 	}
+	
+#ifdef FILETRACKER
+	DBGMSG("File tracking is ENABLED\n");
+#else
+	DBGMSG("File tracking is DISABLED\n");
+#endif
 
 	/* allow environment variables to override default locations */
 	/* two options are supported, explicit overrides for each directory