Support QP/M TIMDAT Routine

QP/M is a CP/M 2.2 replacement for BDOS/CCP.  However, it adds it's own concept of date/time stamping.  Support for the QP/M date/time routine has been added.  You can configure QP/M to find the vector at address 0x0010.

A sidenote on QP/M.  By default, it uses 2 bytes at address 0x0008 to store the current drive/user.  This will conflict with RomWBW's use of RST 08 for API function calls.  I recommend using address 0x000E when configuring QP/M for the location of the current drive/user.

.gitignore

@@ -96,7 +96,7 @@ Tools/unix/zx/zx
 !Source/ZRC/*.bin
 !Source/ZZR/*.bin
 !Source/ZZR/*.hex
-!Tools/cpm/bin/*
+!Tools/cpm/**
 !Tools/unix/zx/*
 !Tools/zx/*
 

CODE_OF_CONDUCT.md

@@ -0,0 +1,128 @@
+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+We as members, contributors, and leaders pledge to make participation in our
+community a harassment-free experience for everyone, regardless of age, body
+size, visible or invisible disability, ethnicity, sex characteristics, gender
+identity and expression, level of experience, education, socio-economic status,
+nationality, personal appearance, race, religion, or sexual identity
+and orientation.
+
+We pledge to act and interact in ways that contribute to an open, welcoming,
+diverse, inclusive, and healthy community.
+
+## Our Standards
+
+Examples of behavior that contributes to a positive environment for our
+community include:
+
+* Demonstrating empathy and kindness toward other people
+* Being respectful of differing opinions, viewpoints, and experiences
+* Giving and gracefully accepting constructive feedback
+* Accepting responsibility and apologizing to those affected by our mistakes,
+  and learning from the experience
+* Focusing on what is best not just for us as individuals, but for the
+  overall community
+
+Examples of unacceptable behavior include:
+
+* The use of sexualized language or imagery, and sexual attention or
+  advances of any kind
+* Trolling, insulting or derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or email
+  address, without their explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+## Enforcement Responsibilities
+
+Community leaders are responsible for clarifying and enforcing our standards of
+acceptable behavior and will take appropriate and fair corrective action in
+response to any behavior that they deem inappropriate, threatening, offensive,
+or harmful.
+
+Community leaders have the right and responsibility to remove, edit, or reject
+comments, commits, code, wiki edits, issues, and other contributions that are
+not aligned to this Code of Conduct, and will communicate reasons for moderation
+decisions when appropriate.
+
+## Scope
+
+This Code of Conduct applies within all community spaces, and also applies when
+an individual is officially representing the community in public spaces.
+Examples of representing our community include using an official e-mail address,
+posting via an official social media account, or acting as an appointed
+representative at an online or offline event.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported to the community leaders responsible for enforcement at
+wwarthen@gmail.com.
+All complaints will be reviewed and investigated promptly and fairly.
+
+All community leaders are obligated to respect the privacy and security of the
+reporter of any incident.
+
+## Enforcement Guidelines
+
+Community leaders will follow these Community Impact Guidelines in determining
+the consequences for any action they deem in violation of this Code of Conduct:
+
+### 1. Correction
+
+**Community Impact**: Use of inappropriate language or other behavior deemed
+unprofessional or unwelcome in the community.
+
+**Consequence**: A private, written warning from community leaders, providing
+clarity around the nature of the violation and an explanation of why the
+behavior was inappropriate. A public apology may be requested.
+
+### 2. Warning
+
+**Community Impact**: A violation through a single incident or series
+of actions.
+
+**Consequence**: A warning with consequences for continued behavior. No
+interaction with the people involved, including unsolicited interaction with
+those enforcing the Code of Conduct, for a specified period of time. This
+includes avoiding interactions in community spaces as well as external channels
+like social media. Violating these terms may lead to a temporary or
+permanent ban.
+
+### 3. Temporary Ban
+
+**Community Impact**: A serious violation of community standards, including
+sustained inappropriate behavior.
+
+**Consequence**: A temporary ban from any sort of interaction or public
+communication with the community for a specified period of time. No public or
+private interaction with the people involved, including unsolicited interaction
+with those enforcing the Code of Conduct, is allowed during this period.
+Violating these terms may lead to a permanent ban.
+
+### 4. Permanent Ban
+
+**Community Impact**: Demonstrating a pattern of violation of community
+standards, including sustained inappropriate behavior,  harassment of an
+individual, or aggression toward or disparagement of classes of individuals.
+
+**Consequence**: A permanent ban from any sort of public interaction within
+the community.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage],
+version 2.0, available at
+https://www.contributor-covenant.org/version/2/0/code_of_conduct.html.
+
+Community Impact Guidelines were inspired by [Mozilla's code of conduct
+enforcement ladder](https://github.com/mozilla/diversity).
+
+[homepage]: https://www.contributor-covenant.org
+
+For answers to common questions about this code of conduct, see the FAQ at
+https://www.contributor-covenant.org/faq. Translations are available at
+https://www.contributor-covenant.org/translations.

Doc/ChangeLog.txt

@@ -60,6 +60,8 @@ Version 3.1.1
 - D?T: Substantial update to TastyBasic incuding a .COM executable
 - PMS: Added VGM audio file player
 - WBW: ZPMLDR and ZPM3 fixes, credit to Lars Nelson for finding ZPM3 source!
+- DDW: Add support for MBC sound card
+- WBW: Add support for "romless" booting
 
 Version 3.1
 -----------

LICENSE

@@ -0,0 +1,661 @@
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+available, or (2) arrange to deprive yourself of the benefit of the
+patent license for this particular work, or (3) arrange, in a manner
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+
+  A patent license is "discriminatory" if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License.  You may not convey a covered
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+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
+the work, and under which the third party grants, to any of the
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+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+  Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+  12. No Surrender of Others' Freedom.
+
+  If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all.  For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+  13. Remote Network Interaction; Use with the GNU General Public License.
+
+  Notwithstanding any other provision of this License, if you modify the
+Program, your modified version must prominently offer all users
+interacting with it remotely through a computer network (if your version
+supports such interaction) an opportunity to receive the Corresponding
+Source of your version by providing access to the Corresponding Source
+from a network server at no charge, through some standard or customary
+means of facilitating copying of software.  This Corresponding Source
+shall include the Corresponding Source for any work covered by version 3
+of the GNU General Public License that is incorporated pursuant to the
+following paragraph.
+
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+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU General Public License into a single
+combined work, and to convey the resulting work.  The terms of this
+License will continue to apply to the part which is the covered work,
+but the work with which it is combined will remain governed by version
+3 of the GNU General Public License.
+
+  14. Revised Versions of this License.
+
+  The Free Software Foundation may publish revised and/or new versions of
+the GNU Affero General Public License from time to time.  Such new versions
+will be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+  Each version is given a distinguishing version number.  If the
+Program specifies that a certain numbered version of the GNU Affero General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation.  If the Program does not specify a version number of the
+GNU Affero General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+  If the Program specifies that a proxy can decide which future
+versions of the GNU Affero General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+  Later license versions may give you additional or different
+permissions.  However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+  15. Disclaimer of Warranty.
+
+  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
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+IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
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+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
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+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU Affero General Public License as published
+    by the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU Affero General Public License for more details.
+
+    You should have received a copy of the GNU Affero General Public License
+    along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If your software can interact with users remotely through a computer
+network, you should also make sure that it provides a way for users to
+get its source.  For example, if your program is a web application, its
+interface could display a "Source" link that leads users to an archive
+of the code.  There are many ways you could offer source, and different
+solutions will be better for different programs; see section 13 for the
+specific requirements.
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU AGPL, see
+<https://www.gnu.org/licenses/>.

ReadMe.md

@@ -3,7 +3,7 @@
 ## Z80/Z180 System Software
 
 Version 3.1 Pre-release  
-28 Feb 2022
+21 Mar 2022
 
 Wayne Warthen <wwarthen@gmail.com>
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Getting Started
 Wayne Warthen (mailto:wwarthen@gmail.com)
-28 Feb 2022
+21 Mar 2022
 
 
 
@@ -17,7 +17,7 @@ RomWBW
 Z80/Z180 System Software
 
 Version 3.1 Pre-release
-28 Feb 2022
+21 Mar 2022
 
 Wayne Warthen wwarthen@gmail.com
 

Source/Apps/Test/Build.cmd

@@ -21,6 +21,7 @@ pushd vdctest && call Build || exit /b & popd
 pushd kbdtest && call Build || exit /b & popd
 pushd ps2info && call Build || exit /b & popd
 pushd 2piotst && call Build || exit /b & popd
+pushd piomon && call Build || exit /b & popd
 
 goto :eof
 

Source/Apps/Test/Clean.cmd

@@ -18,3 +18,4 @@ pushd vdctest && call Clean || exit /b 1 & popd
 pushd kbdtest && call Clean || exit /b 1 & popd
 pushd ps2info && call Clean || exit /b 1 & popd
 pushd 2piotst && call Clean || exit /b 1 & popd
+pushd piomon && call Clean || exit /b 1 & popd

Source/Apps/Test/DMAmon/Readme.txt

@@ -1 +1,8 @@
 DMAmon is a program to verify operation of the Z80 MBC DMA board
+
+Version 2 has been hacked to include testing for interrupts.  This
+requires running the application under RomWBW using IM2.  There
+is an equate in the source file to disable interrupt testing
+if needed.
+
+--WBW 10:36 AM 3/14/2022

Source/Apps/Test/DMAmon/dmamon.asm

@@ -16,6 +16,14 @@ TRUE		.EQU	~FALSE
 SPD_FIXED	.EQU	0		; PLATFORM SPEED FIXED AND CANNOT CHANGE SPEEDS
 SPD_HILO	.EQU	1		; PLATFORM CAN CHANGE BETWEEN TWO SPEEDS
 ;
+; INTERRUPT TESTING CONFIGURATION
+; N.B., INTERRUPT TESTING REQUIRES ROMWBW!!!
+; ASSUMES SYSTEM IS ALREADY CONFIGURED FOR IM2 OPERATION
+; INTIDX MUST BE SET TO AN UNUSED INTERRUPT SLOT
+;		
+INTENABLE	.EQU	TRUE		; ENABLE INT TESTING
+INTIDX		.EQU	1		; INT VECTOR INDEX
+;
 ; SYSTEM SPEED CHARACTERISTICS
 ;
 SPD_UNSUP	.EQU	0		; PLATFORM CAN CHANGE SPEEDS BUT IS UNSUPPORTED
@@ -56,14 +64,20 @@ DMA_RESET			.equ	$c3
 ;DMA_RESET_PORT_B_TIMING	.equ	$cb
 ;DMA_CONTINUE			.equ	$d3
 ;DMA_DISABLE_INTERUPTS		.equ	$af
-;DMA_ENABLE_INTERUPTS		.equ	$ab
+DMA_ENABLE_INTERUPTS		.equ	$ab
 ;DMA_RESET_DISABLE_INTERUPTS	.equ 	$a3
 ;DMA_ENABLE_AFTER_RETI		.equ	$b7
-;DMA_REINIT_STATUS_BYTE		.equ	$8b
+DMA_REINIT_STATUS_BYTE		.equ	$8b
 ;
 DMA_RDY				.EQU	%00001000
 DMA_FORCE			.EQU	0
-
+;
+bf_sysint			.equ	$FC	; INT function
+;		
+bf_sysintinfo			.equ	$00	; INT INFO subfunction
+bf_sysintget			.equ	$10	; INT GET subfunction
+bf_sysintset			.equ	$20	; INT SET subfunction
+;
 #IF (DMA_USEHS & (DMAMODE=DMAMODE_MBC))
 #IF (CPUSPDDEF=SPD_HIGH)
 #DEFINE DMAIOSLO LD A,(HB_RTCVAL) \ AND %11110111 \ OUT (RTCIO),A 
@@ -100,66 +114,128 @@ MAIN:
 	LD	SP,STACK		; STACK
 ;
 	call	PRTSTRD			; WELCOME
-	.db	"DMA MONITOR\n\r$"
+	.db	"\n\rDMA Monitor V2\n\r$"
+;
+#IF (INTENABLE)
+;
+	; Install interrupt handler in upper mem
+	ld	hl,reladr
+	ld	de,$A000
+	ld	bc,hsiz
+	ldir
+;
+	; Install interrupt vector (RomWBW specific!!!)
+	ld	hl,int		; pointer to my interrupt handler
+	ld	b,bf_sysint
+	ld	c,bf_sysintset	; set new vector
+	ld	e,INTIDX	; vector idx
+	di
+	rst	08		; do it
+	ld	(orgvec),hl	; save the original vector
+	ei			; interrupts back on
+;
+#ENDIF
 ;
 MENULP:	CALL	DISPM			; DISPLAY MENU
 	CALL	CIN			; GET SELECTION
+	; Force upper case
+	CP	'a'			; < 'a'
+	JR	C,MENULP1		; IF SO, JUST CONTINUE
+	CP	'z'+1			; > 'z'
+	JR	NC,MENULP1		; IS SO, JUST CONTINUE
+	SUB	'a'-'A'			; CONVERT TO UPPER
 ;
+MENULP1:
+	CALL	NEWLINE
 	CP	'D'
 	JP	Z,DMATST_D		; DUMP REGISTERS
 	CP	'I'
 	JP	Z,DMATST_I		; INITIALIZE
+#IF (INTENABLE)
+	CP	'T'
+	JP	Z,DMATST_T		; TOGGLE INT USAGE
+#ENDIF
 	CP	'M'
-	JP	Z,DMATST_M		; MEMORY MOVE
+	JP	Z,DMATST_M		; MEMORY COPY
+	CP	'N'
+	JP	Z,DMATST_N		; MEMORY COPY ITER
 	CP	'0'
 	JP	Z,DMATST_01
 	CP	'1'
-	JR	Z,DMATST_01
+	JP	Z,DMATST_01
 	CP	'R'
 	JP	Z,DMATST_R		; TOGGLE RESET
 	CP	'Y'
 	JP	Z,DMATST_Y		; TOGGLE READY
 	CP	'X'
-	JR	Z,DMABYE		; EXIT
+	JP	Z,DMABYE		; EXIT
 ;
 	JR	MENULP
 ;
-DMABYE:	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
+DMABYE:
+#IF (INTENABLE)
+	; Deinstall interrupt vector
+	ld	hl,(orgvec)	; original vector
+	ld	b,bf_sysint
+	ld	c,bf_sysintset	; set new vector
+	ld	e,INTIDX	; vector idx
+	di
+	rst	08		; do it
+	ei			; interrupts back on
+#ENDIF
+;
+	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
 	RET
 ;
 DMATST_I:
 	call	PRTSTRD
-	.db	"\n\rSTART DMA_INIT\n\r$"
+	.db	"\n\rStart Initialization\n\r$"
 	CALL	DMA_INIT
 	JP	MENULP
 ;
+#IF (INTENABLE)
+;
+DMATST_T:
+	LD	A,(USEINT)
+	XOR	$FF
+	LD	(USEINT),A
+	JP	MENULP
+;
+#ENDIF
+;
 DMATST_M:
 	call	PRTSTRD
-	.db	"\n\rSTART DMAMemMove\n\r$"
-	CALL	DMAMemMove
+	.db	"\n\rPerforming Memory-Memory Copy Test\n\r$"
+	CALL	DMAMemTest
+	JP	MENULP
+;
+DMATST_N:
+	call	PRTSTRD
+	.db	"\n\rPerforming Iterative Memory-Memory Copy Test\n\r$"
+	CALL	DMAMemTestIter
 	JP	MENULP
 ;
 DMATST_01:
 	call	PRTSTRD
-	.db	"\n\rTOGGLE PORT\n\r$"
+	.db	"\n\rPerforming Port Selection Test\n\r$"
 	CALL	DMA_Port01
 	JP	MENULP
 ;
 DMATST_D:
 	call	PRTSTRD
-	.db	"\n\rSTART DMARegDump\n\r$"
+	.db	"\n\rDump Registers\n\r$"
 	CALL	DMARegDump
 	JP	MENULP
 ;
 DMATST_Y:
 	call	PRTSTRD
-	.db	"\n\rTEST READY\n\r$"
+	.db	"\n\rPerforming Ready Bit Test\n\r$"
 	CALL	DMA_ReadyT
 	JP	MENULP
 ;
 DMATST_R:
 	call	PRTSTRD
-	.db	"\n\rRESET\n\r$"
+	.db	"\n\rPerforming Reset\n\r$"
 ;	CALL	
 	JP	MENULP
 ;==================================================================================================
@@ -167,19 +243,39 @@ DMATST_R:
 ;==================================================================================================
 ;
 DISPM:	call	PRTSTRD
-	.db	"\n\rDMA DEVICE: $"
+	.db	"\n\rDMA Device: $"
 	LD	C,DMAMODE		; DISPLAY
 	LD	A,00000111B		; TARGET
 	LD	DE,DMA_DEV_STR		; DEVICE
 	CALL	PRTIDXMSK
-	CALL	NEWLINE
 ;
 	call	PRTSTRD
-	.db	"DMA PORT: $"
+	.db	", Port=0x$"
 	LD	A,DMABASE		; DISPLAY
 	CALL	PRTHEXBYTE		; DMA PORT
-	CALL	NEWLINE
 ;
+#IF (INTENABLE)
+;
+	call	PRTSTRD
+	.db	"\n\rInterrupts=$"
+	LD	A,(USEINT)
+	OR	A
+	LD	A,'Y'
+	JR	NZ,DISPM_INT
+	LD	A,'N'
+	JR	DISPM_INT
+;
+DISPM_INT:
+	CALL	COUT
+;
+	call	PRTSTRD
+	.db	", Interrupt Count=$"
+	ld	hl,(counter)
+	call	PRTDEC
+;
+#ENDIF
+;
+	call	NEWLINE
 	LD	HL,MENU_OPT		; DISPLAY
 	CALL	PRTSTR			; MENU OPTIONS
 ;
@@ -206,7 +302,7 @@ DMA_INIT:
 	jr	nz,DMA_NOTFOUND
 ;
 	call	PRTSTRD
-	.db	" DMA FOUND\n\r$"
+	.db	" DMA Found\n\r$"
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
@@ -224,7 +320,7 @@ DMA_EXIT:
 DMA_NOTFOUND:
 	push	af
 	call	PRTSTRD
-	.db	" NOT PRESENT$"
+	.db	" NOT Present$"
 	pop	af
 	jr	DMA_EXIT
 ;
@@ -242,38 +338,41 @@ DMA_DEV_STR:
 MENU_OPT:
 	.TEXT	"\n\r"
 	.TEXT	"I) Initialize DMA\n\r"
-	.TEXT	"M) Memory to Memory test\n\r"
-	.TEXT	"0) DMA Port select test\n\r"
-	.TEXT	"1) DMA Latch Port select test\n\r"
-	.TEXT	"Y) Ready bit test\n\r"
+	.TEXT	"T) Toggle Interrupt Usage\n\r"
+	.TEXT	"M) Test Memory-Memory Copy\n\r"
+	.TEXT	"N) Test Memory-Memory Copy Iteratively\n\r"
+	.TEXT	"0) Test DMA Port Selection\n\r"
+	.TEXT	"1) Test DMA Latch Port Selection\n\r"
+	.TEXT	"Y) Test Ready Bit\n\r"
 	.TEXT	"X) Exit\n\r"
 
 	.TEXT	">$"
 ;
 ;==================================================================================================
-; TOGGLE A PORT ON AND OFF
+; PULSE PORT
 ;==================================================================================================
 ;
 DMA_Port01:
+	call	PRTSTRD
+	.db	"\r\nPulsing port 0x$"
 	sub	'0'			; Calculate
 	add	a,DMABASE		; Port to
+	call	PRTHEXBYTE
+	call	NEWLINE
 	ld	c,a			; toggle
-	ld	b,0
+	ld	b,$20			; loop counter
 portlp:	push	bc
-	call	PRTSTRD
-	.db	"\n\rON ...$"
-	call	PRTHEXWORD
+	call	PC_PERIOD
 	push	bc
 	ld	b,0
 	ld	a,0
 portlp1:out	(c),a
 	djnz	portlp1
 	pop	bc
-	call	PRTSTRD
-	.db	" OFF$"
 	call	delay	
 	pop	bc
 	djnz	portlp
+	call	NEWLINE
 	JP	MENULP
 ;
 delay:	push	bc
@@ -290,18 +389,23 @@ dlylp:	dec	bc
 ;==================================================================================================
 ;
 DMA_ReadyT:
+	call	NEWLINE
 	ld	c,DMABASE+1		; toggle
-	ld	b,0
+	ld	b,$20			; loop counter
 portlp2:push	bc
+	ld	a,b
+	call	PRTDECB
 	call	PRTSTRD
-	.db	"\n\rON ...$"
-	call	PRTHEXWORD
+	.db	": ON$"
+	call	delay
 	ld	a,$FF
 	ld	c,DMABASE+1
 	out	(c),a
 	call	PRTSTRD
-	.db	" OFF$"
+	.db	" -> OFF$"
 	call	delay
+	call	PRTSTRD
+	.db	"\r               \r$"
 	ld	c,DMABASE+1
 	ld	a,0
 	out	(c),a
@@ -332,8 +436,16 @@ DMAMemMove:
 	LD	HL,PROEND	; DMA COPY
 	LD	DE,$8000
 	LD	BC,4096-1
-	CALL	DMALDIR
-
+	LD	A,(USEINT)	; USE INTS?
+	OR	A		; TEST VALUE
+	JR	NZ,DMAMemMove1	; IF SO, DO SO
+	CALL	DMALDIR		; ELSE NORMAL DMA
+	JR	DMAMemMove2
+;
+DMAMemMove1:
+	CALL	DMALDIRINT	; DMA W/ INTERRUPTS
+;
+DMAMemMove2:
 ;
 ;	LD	HL,$8400	; PLANT
 ;	LD	A,$00		; BAD
@@ -345,15 +457,57 @@ DMAMemMove:
 NXTCMP:	CPI
 	JP	PO,CMPOK
 	JR	Z,NXTCMP
-
-	call	PRTHEXWORD
+	RET			; RET W/ ZF CLEAR
+;
+CMPOK:
+	RET			; RET W/ ZF SET
+;
+;==================================================================================================
+; DMA MEMORY TEST
+;==================================================================================================
+;
+DMAMemTest:
+	call	DMAMemMove	; do a single memory copy
+	jr	z,DMAMemTestOK
+	jr	DMAMemTestFail
+;
+DMAMemTestOK:
 	call	PRTSTRD
-	.db	" TEST MEMORY MOVE FAILED\n\r$"
-	RET
-
-CMPOK:	call	PRTSTRD
-	.db	"TEST MEMORY MOVE SUCCEEDED\n\r$"
-	RET
+	.db	"\n\rMemory-Memory Test Passed\n\r$"
+	ret
+;
+DMAMemTestFail:
+	call	PRTSTRD
+	.db	"\n\rMemory-Memory Test Failed\n\r$"
+	ret
+;
+;==================================================================================================
+; DMA MEMORY MOVE ITERATIVE
+;==================================================================================================
+;
+DMAMemTestIter:
+	ld	b,$20		; loop counter
+	call	PRTSTRD
+	.db	"\n\rPerforming $"
+	ld	a,b
+	call	PRTDECB
+	call	PRTSTRD
+	.db	" iterations, '.'=OK, '*'=Fail\n\r$"
+DMAMemTestIterLoop:
+	push	bc		; save loop control
+	call	DMAMemMove	; do an iteration
+	jr	z,DMAMemTestIterOK
+	call	PC_ASTERISK	; signal failure
+	jr	DMAMemTestIterCont	; continue
+;
+DMAMemTestIterOK:
+	call	PC_PERIOD	; signal pass
+;
+DMAMemTestIterCont:
+	pop	bc
+	djnz	DMAMemTestIterLoop
+	call	NEWLINE
+	ret
 ;
 ;==================================================================================================
 ; DMA PROBE - WRITE TO ADDRESS REGISTER AND READ BACK
@@ -455,6 +609,62 @@ DMADest		.dw	0 		; R4-Port B, Destination address
 DMACopy_Len 	.equ	$-DMACopy
 ;
 ;==================================================================================================
+; DMA COPY BLOCK CODE -  ASSUMES DMA PREINITIALIZED
+; INTERRUPT VERSION!
+;==================================================================================================
+;
+DMALDIRINT:
+;
+#IF (INTENABLE)
+;
+	ld	(DMASourceInt),hl	; populate the dma
+	ld	(DMADestInt),de		; register template
+	ld	(DMALengthInt),bc
+;
+	ld	hl,DMACopyInt		; program the
+	ld	b,DMACopyInt_Len	; dma command
+	ld	c,DMABASE		; block
+;
+	DMAIOSLO
+	di
+	otir				; load and execute dma
+	ei
+;
+	ld	a,DMA_READ_STATUS_BYTE	; check status
+	out	(DMABASE),a		; of transfer
+	in	a,(DMABASE)		; set non-zero
+	and	%00111011		; if failed
+	sub	%00011011
+	DMAIONOR
+;
+#ENDIF
+;
+	ret
+;
+#IF (INTENABLE)
+;
+DMACopyInt 	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+DMASourceInt	.dw	0 		; R0-Port A, Start address
+DMALengthInt	.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10100000 	; R3-DMA, interrupt, stop on match disabled
+		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+DMADestInt	.dw	0 		; R4-Port B, Destination address
+		.db	%00011110	; R4-Interrupt control byte: Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse control byte
+		.db	INTIDX*2	; R4-Interrupt vector
+;		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config
+		.db	%10011010
+		.db	DMA_LOAD 	; R6-Command Load
+		.db	DMA_FORCE_READY	; R6-Command Force ready
+		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACopyInt_Len 	.equ	$-DMACopyInt
+;
+#ENDIF
+;
+;==================================================================================================
 ; DMA I/O OUT BLOCK CODE - ADDRESS TO I/O PORT
 ;==================================================================================================
 ;
@@ -552,8 +762,6 @@ DMAIn_Len 	.equ	$-DMAInCode
 ; DEBUG - READ START, DESTINATION AND COUNT REGISTERS
 ;==================================================================================================
 ;
-;#IF (0)
-;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
 	out	(DMABASE),a
@@ -586,7 +794,6 @@ DMARegDump:
 ;
 	call	NEWLINE
 	ret
-;#ENDIF
 ;
 CIO_CONSOLE	.EQU	$80	; CONSOLE UNIT TO C
 BF_CIOOUT	.EQU	$01	; HBIOS FUNC: OUTPUT CHAR
@@ -662,10 +869,52 @@ CST:
 	POP	DE
 	POP	BC
 	RET
-
+;
+USEINT	.DB	FALSE		; USE INTERRUPTS FLAG
+;
 SAVSTK:	.DW	2
 	.FILL	64
 STACK:	.EQU	$
+;
+orgvec	.dw	0		; saved interrupt vector
+;
+;===============================================================================
+; Interrupt Handler
+;===============================================================================
+;
+reladr	.equ	$		; relocation start adr
+;
+	.org	$A000		; code will run here
+;
+int:
+	; According to the DMA doc, you must issue
+	; a DMA_DISABLE command prior to a
+	; DMA_REINIT_STATUS_BYTE command to avoid a
+	; potential race condition.
+	ld	a,DMA_DISABLE
+	out	(DMABASE),a
+;	
+	; The doc confuses me, but apparently it is
+	; necessary to reinitialize the status byte
+	; when an end-of-block interrupt occurs.  Otherwise,
+	; the end-of-block condition remains set and
+	; causes the interrupt to fire continuously.
+	ld	a,DMA_REINIT_STATUS_BYTE
+	out	(DMABASE),a
+;
+	ld	hl,(counter)
+	inc	hl
+	ld	(counter),hl
+;
+	or	$ff		; signal int handled
+	ret
+;
+counter	.dw	0
+;
+hsiz	.equ	$ - $A000	; size of handler to relocate
+;
+	.org	reladr + hsiz
+;
 PROEND:	.EQU	$
 ;
 	.END

Source/Apps/Test/DMAmon/dmamon.sh

@@ -1,3 +0,0 @@
-~/RomWBW-dev/Tools/unix/uz80as/uz80as -t z80 dmamon.asm dmamon.bin
-#srec_cat dmamon.bin -binary -offset 0x0100 --address-length=2 -o dmamon.hex -Intel
-cat dmamon.bin > dmamon.com

Source/Apps/Test/Makefile

@@ -1,5 +1,5 @@
 OBJECTS = 
-SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info 2piotst
+SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info 2piotst piomon
 DEST = ../../../Binary/Apps/Test
 TOOLS =../../../Tools
 

Source/Apps/Test/piomon/Build.cmd

@@ -0,0 +1,10 @@
+@echo off
+setlocal
+
+set TOOLS=../../../../Tools
+set PATH=%TOOLS%\tasm32;%PATH%
+set TASMTABS=%TOOLS%\tasm32
+
+tasm -t180 -g3 -fFF piomon.asm piomon.com piomon.lst || exit /b
+
+copy /Y piomon.com ..\..\..\..\Binary\Apps\Test\ || exit /b

Source/Apps/Test/piomon/Clean.cmd

@@ -0,0 +1,6 @@
+@echo off
+setlocal
+
+if exist *.com del *.com
+if exist *.lst del *.lst
+if exist *.bin del *.bin

Source/Apps/Test/piomon/Makefile

@@ -0,0 +1,7 @@
+OBJECTS = piomon.com
+DEST = ../../../../Binary/Apps/Test
+TOOLS =../../../../Tools
+
+USETASM=1
+
+include $(TOOLS)/Makefile.inc

Source/Apps/Test/piomon/Readme.txt

@@ -0,0 +1,36 @@
+PIOMON is a program to verify operation of the Z80 MBC DUALPIO board
+
+Most testing requires the use of loopback hardware constructed as:
+
+Channel A   RDY STB  D0  D1  D2  D3  D4  D5  D6  D7
+             \   /   |   |   |   |   |   |   |   |
+              \ /    |   |   |   |   |   |   |   |
+               X     |   |   |   |   |   |   |   |
+              / \    |   |   |   |   |   |   |   |
+             /   \   |   |   |   |   |   |   |   |
+Channel B   RDY STB  D0  D1  D2  D3  D4  D5  D6  D7
+
+The DUALPIO has, well, 2 PIO chips.  Only one chip
+is tested at a time.  At startup, PIOMON will ask
+you for the port of the chip to test.  It defaults
+to the standard port number for the primary PIO chip
+on an MBC DUALPIO board.
+
+The port number specified is the base I/O port.  Each
+chip has two channels which are addressed in the
+menu by specifying A or B.
+
+MBC DUALPIO Primary PIO = 0xB8
+MBC DUALPIO Secondary PIO = 0xBC
+
+If you try to use PIOMON without the RDY and STB
+cross connected, you may have interrupt issues
+because STB will be floating.
+
+N.B., V1 and V2 of the DUALPIO lack a hardware reset.  The
+PIO chips will reset at power-on, but they do not reset
+when the reset button is pushed.
+
+Happy St. Patrick's Day!!!
+
+--WBW 7:42 PM 3/17/2022

Source/Apps/Test/ps2info/ps2info.asm

@@ -6,12 +6,21 @@
 ; Simple utility that performs simple tests of an 8242 PS/2 controller,
 ; keyboard, and mouse.
 ;
+; WBW 2022-03-28: Add menu driven port selection
+;                 Add support for RHYOPHYRE
+; WBW 2022-04-01: Add menu for test functions
+; WBW 2022-04-02: Fix prtchr register saving/recovery
+;
 ;=======================================================================
 ;
 ; PS/2 Keyboard/Mouse controller port addresses (adjust as needed)
 ;
-iocmd	.equ	$E3	; PS/2 controller command port address
-iodat	.equ	$E2	; PS/2 controller data port address
+; MBC:
+iocmd_mbc	.equ	$E3	; PS/2 controller command port address
+iodat_mbc	.equ	$E2	; PS/2 controller data port address
+; RPH:
+iocmd_rph	.equ	$8D	; PS/2 controller command port address
+iodat_rph	.equ	$8C	; PS/2 controller data port address
 ;
 cpumhz	.equ	8	; for time delay calculations (not critical)
 ;
@@ -37,6 +46,8 @@ bdos	.equ	$0005			; BDOS invocation vector
 	call	crlf
 	ld	de,str_banner		; banner
 	call	prtstr
+;
+	call	setup
 ;
 	call	main			; do the real work
 ;
@@ -50,52 +61,95 @@ exit:
 	ld	sp,(stksav)		; restore stack
 	jp	restart			; return to CP/M via restart
 ;
+;=======================================================================
+; Select and setup for hardware
+;=======================================================================
+;
+setup:
+	call	crlf2
+	ld	de,str_hwmenu
+	call	prtstr
+setup1:
+	ld	c,$06			; BDOS direct console I/O
+	ld	e,$FF			; Subfunction = read
+	call	bdos
+	cp	0
+	jr	z,setup1
+	call	upcase
+	call	prtchr
+	cp	'1'			; MBC
+	jr	z,setup_mbc
+	cp	'2'			; RHYOPHYRE
+	jr	z,setup_rph
+	cp	'X'
+	jr	z,exit
+	jr	setup
+;
+setup_mbc:
+	ld	a,iocmd_mbc
+	ld	(iocmd),a
+	ld	a,iodat_mbc
+	ld	(iodat),a
+	ld	de,str_mbc
+	jr	setup2
+;
+setup_rph:
+	ld	a,iocmd_rph
+	ld	(iocmd),a
+	ld	a,iodat_rph
+	ld	(iodat),a
+	ld	de,str_rph
+	jr	setup2
+;
+setup2:
+	call	prtstr
+	call	crlf2
+	ld	de,str_cmdport
+	call	prtstr
+	;ld	a,iocmd
+	ld	a,(iocmd)
+	call	prthex
+	call	crlf
+	ld	de,str_dataport
+	call	prtstr
+	;ld	a,iodat
+	ld	a,(iodat)
+	call	prthex
+;
+	xor	a
+	ret
 ;
 ;=======================================================================
 ; Main Program
 ;=======================================================================
 ;
 main:
-;
-; Display active controller port addresses
-;
 	call	crlf2
-	ld	de,str_cmdport
+	ld	de,str_menu
 	call	prtstr
-	ld	a,iocmd
-	call	prthex
-	call	crlf
-	ld	de,str_dataport
-	call	prtstr
-	ld	a,iodat
-	call	prthex
-;
-	call	test_ctlr
-	jr	z,main0			; continue if ctlr OK
-	ld	de,str_kbd_failed
-	call	crlf2
-	call	prtstr
-	jr	mainz			; bail out if ctlr fails
-;
-main0:
-	call	test_kbd
-	jr	z,main1			; completed all tests, continue
-	ld	de,str_kbd_failed
-	call	crlf2
-	call	prtstr
-;
 main1:
-	call	test_mse
-	jr	z,main2			; completed all tests, continue
-	ld	de,str_mse_failed
-	call	crlf2
-	call	prtstr
+	ld	c,$06			; BDOS direct console I/O
+	ld	e,$FF			; Subfunction = read
+	call	bdos
+	cp	0
+	jr	z,main1
+	call	upcase
+	call	prtchr
+	cp	'X'
+	jp	z,exit
+	call	main2
+	jr	main
 ;
 main2:
-	call	test_kbdmse
-;
-mainz:
-	xor	a
+	; Dispatch to test functions
+	cp	'C'			; Test Controller
+	jp	z,test_ctlr
+	cp	'K'			; Test Keyboard
+	jp	z,test_kbd
+	cp	'M'			; Test Mouse
+	jp	z,test_mse
+	cp	'B'			; Test Both
+	jp	z,test_kbdmse
 	ret
 ;
 ; Test 8242 PS/2 Controller
@@ -109,10 +163,8 @@ test_ctlr:
 	ret	nz
 ;
 	call	ctlr_test_p1
-	;ret	nz
 ;
 	call	ctlr_test_p2
-	;ret	nz
 ;
 	ret
 ;
@@ -123,13 +175,15 @@ test_kbd:
 ; First, we attempt to contact the controller and keyboard, then
 ; print the keyboard identity and scan codes supported
 ;
-	; Run test series with translation off
 	call	crlf2
 	ld	de,str_basic
 	call	prtstr
+;
+	call	ctlr_test
+	jr	nz,test_kbd_fail
 ;
 	call	test_kbd_basic
-	ret	nz
+	jr	nz,test_kbd_fail
 ;
 ; We make two passes through the test series with different controller
 ; setup values.  The first time is with scan code translation off and
@@ -155,59 +209,83 @@ test_kbd:
 ;
 	ret
 ;
+test_kbd_fail:
+	ld	de,str_kbd_failed
+	call	crlf2
+	call	prtstr
+	ret
+;
 ; Test Mouse
 ;
 test_mse:
 	call	crlf2
 	ld	de,str_basic_mse
 	call	prtstr
+;
+	call	ctlr_test
+	jr	nz,test_mse_fail
 ;
 	ld	a,$10			; kbd disabled, mse enabled, no ints
 	call	ctlr_setup
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_reset
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_ident
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_stream
-	ret	nz
+	jr	nz,test_mse_fail
 ;
 	call	mse_echo
 ;	
 	xor	a			; signal success
 	ret
 ;
+test_mse_fail:
+	ld	de,str_mse_failed
+	call	crlf2
+	call	prtstr
+	ret
+;
 ; Test Everything
 ;
 test_kbdmse:
 	call	crlf2
 	ld	de,str_kbdmse
 	call	prtstr
+;
+	call	ctlr_test
+	jr	nz,test_kbdmse_fail
 ;
 	ld	a,$00			; kbd enabled, mse enabled, no ints
 	call	ctlr_setup
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	call	kbd_reset
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	ld	a,2
 	call	kbd_setsc
 ;
 	call	mse_reset
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	call	mse_stream
-	ret	nz
+	jr	nz,test_kbdmse_fail
 ;
 	call	kbdmse_echo
 ;	
 	xor	a			; signal success
 	ret
 ;
+test_kbdmse_fail:
+	ld	de,str_kbdmse_failed
+	call	crlf2
+	call	prtstr
+	ret
+;
 ; Perform basic keyboard tests, display keyboard identity, and
 ; inventory the supported scan code sets.
 ;
@@ -782,7 +860,9 @@ wait_write:
 	ld	a,(timeout)		; setup timeout constant
 	ld	b,a
 wait_write1:
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	ld	c,a			; save status
 	and	$02			; isolate input buf status bit
 	ret	z			; 0 means ready, all done
@@ -804,7 +884,9 @@ wait_read:
 	ld	a,(timeout)		; setup timeout constant
 	ld	b,a
 wait_read1:
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	ld	c,a			; save status
 	and	$01			; isolate input buf status bit
 	xor	$01			; invert so 0 means ready
@@ -824,7 +906,9 @@ check_read:
 ; Check for data ready to read
 ;   A=0 indicates data available (ZF set)
 ;
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	and	$01			; isolate input buf status bit
 	xor	$01			; invert so 0 means ready
 	ret
@@ -834,7 +918,9 @@ check_read_kbd:
 ; Check for keyboard data ready to read
 ;   A=0 indicates data available (ZF set)
 ;
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	and	%00100001		; isolate input buf status bit
 	cp	%00000001		; data ready, not mouse
 	ret
@@ -844,7 +930,9 @@ check_read_mse:
 ; Check for mouse data ready to read
 ;   A=0 indicates data available (ZF set)
 ;
-	in	a,(iocmd)		; get status
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
+	in	a,(c)			; get status
 	and	%00100001		; isolate input buf status bit
 	cp	%00100001		; data ready, is mouse
 	ret
@@ -860,8 +948,10 @@ put_cmd:
 	scf				; else, signal timeout error
 	ret				; and bail out
 put_cmd1:
+	ld	a,(iocmd)		; cmd port
+	ld	c,a			; ... to C
 	ld	a,e			; recover value to write
-	out	(iocmd),a		; write it
+	out	(c),a			; write it
 	or	a			; clear CF for success
 	ret
 ;
@@ -889,8 +979,10 @@ put_data:
 	scf				; else, signal timeout error
 	ret				; and bail out
 put_data1:
+	ld	a,(iodat)		; data port
+	ld	c,a			; ... to C
 	ld	a,e			; recover value to write
-	out	(iodat),a		; write it
+	out	(c),a			; write it
 	or	a			; clear CF for success
 	ret
 ;
@@ -947,7 +1039,9 @@ get_data:
 	scf				; else signal timeout error
 	ret				; and bail out
 get_data1:
-	in	a,(iodat)		; get data byte
+	ld	a,(iodat)		; data port
+	ld	c,a			; ... to C
+	in	a,(c)			; get data byte
 	or	a			; clear CF for success
 	ret
 ;
@@ -1020,11 +1114,11 @@ err_ret:
 ; Utility Routines
 ;=======================================================================
 ;
-;
 ; Print character in A without destroying any registers
 ;
 prtchr:
-	push	bc		; save registers
+	push	af		; save registers
+	push	bc
 	push	de
 	push	hl
 	ld	e,a		; character to print in E
@@ -1033,6 +1127,7 @@ prtchr:
 	pop	hl		; restore registers
 	pop	de
 	pop	bc
+	pop	af
 	ret
 ;
 prtdot:
@@ -1044,6 +1139,16 @@ prtdot:
 	pop	af		; restore af
 	ret			; done
 ;
+; Uppercase character in A
+;
+upcase:
+	cp	'a'			; below 'a'?
+	ret	c			; if so, nothing to do
+	cp	'z'+1			; above 'z'?
+	ret	nc			; if so, nothing to do
+	and	~$20			; convert character to lower
+	ret				; done
+;
 ; Print a zero terminated string at (de) without destroying any registers
 ;
 prtstr:
@@ -1239,7 +1344,21 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"PS/2 Keyboard/Mouse Information v0.4, 7-Jan-2022",0
+str_banner		.db	"PS/2 Keyboard/Mouse Information v0.6a, 2-Apr-2022",0
+str_hwmenu		.db	"PS/2 Controller Port Options:\r\n\r\n"
+			.db	"  1 - MBC\r\n"
+			.db	"  2 - RHYOPHYRE\r\n"
+			.db	"  X - Exit Application\r\n"
+			.db	"\r\nSelection? ",0
+str_mbc			.db	"MBC",0
+str_rph			.db	"RHYOPHYRE",0
+str_menu		.db	"PS/2 Testing Options:\r\n\r\n"
+			.db	"  C - Test PS/2 Controller\r\n"
+			.db	"  K - Test PS/2 Keyboard\r\n"
+			.db	"  M - Test PS/2 Mouse\r\n"
+			.db	"  B - Test Both PS/2 Keyboard and Mouse Together\r\n"
+			.db	"  X - Exit Application\r\n"
+			.db	"\r\nSelection? ",0
 str_exit		.db	"Done, Thank you for using PS/2 Keyboard/Mouse Information!",0
 str_cmdport		.db	"Controller Command Port: ",0
 str_dataport		.db	"Controller Data Port: ",0
@@ -1312,6 +1431,11 @@ str_mse_failed		.db	"***** MOUSE HARDWARE ERROR *****",13,10,13,10
 			.db	"the completion of the full set of mouse tests.",13,10
 			.db	"Check your hardware and verify the port",13,10
 			.db	"addresses being used for the controller",0
+str_kbdmse_failed	.db	"***** KEYBOARD/MOUSE HARDWARE ERROR *****",13,10,13,10
+			.db	"A basic hardware or configuration issue prevented",13,10
+			.db	"the completion of the full set of keyboard/mouse tests.",13,10
+			.db	"Check your hardware and verify the port",13,10
+			.db	"addresses being used for the controller",0
 ;
 ;=======================================================================
 ; Working data
@@ -1321,6 +1445,9 @@ stksav		.dw	0		; stack pointer saved at start
 		.fill	stksiz,0	; stack
 stack		.equ	$		; stack top
 ;
+iocmd		.db	0
+iodat		.db	0
+;
 workbuf		.fill	8
 workbuf_len	.db	0
 ;

Source/Apps/Tune/tune.asm

@@ -44,6 +44,7 @@
 ;   2020-09-03 [E?B] Add support for Ed Brindley YM/AY Sound Card v6
 ;   2021-08-13 [WBW] Add support for LiNC Z50 Sound Card
 ;   2021-08-17 [WBW] When playing via HBIOS, call BF_SNDRESET at end
+;   2022-03-20 [DDW] Add support for MBC PSG module
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -622,6 +623,9 @@ CFGTBL:	;	PLT	RSEL	RDAT	RIN	Z180	ACR
 ;
 	.DB	$0B,	$33,	$32,	$32,	$FF,	$FF	; RCZ280 W/ LINC SOUND MODULE
 	.DW	HWSTR_LINC
+;
+	.DB	13,	$A0,	$A1,	$A0,	$FF,	$A2	; MBC
+	.DW	HWSTR_MBC
 ;
 	.DB	$FF					; END OF TABLE MARKER
 ;
@@ -650,7 +654,7 @@ TMP		.DB	0	; work around use of undocumented Z80
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN
 
-MSGBAN		.DB	"Tune Player for RomWBW v3.4, 17-Aug-2021",0
+MSGBAN		.DB	"Tune Player for RomWBW v3.5, 20-Mar-2022",0
 MSGUSE		.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10
@@ -674,6 +678,7 @@ HWSTR_RCEB	.DB	"RC2014 Sound Module (EB)",0
 HWSTR_RCEB6	.DB	"RC2014 Sound Module (EBv6)",0
 HWSTR_RCMF	.DB	"RC2014 Sound Module (MF)",0
 HWSTR_LINC	.DB	"Z50 LiNC Sound Module",0
+HWSTR_MBC	.DB	"NHYODYNE Sound Module",0
 
 MSGUNSUP	.db	"MYM files not supported with HBIOS yet!\r\n", 0
 
@@ -2649,4 +2654,3 @@ data:
 ;
 ;===============================================================================
 	.END
-

Source/Apps/rtc.asm

@@ -29,6 +29,8 @@
 ;
 ;[2021/07/10] v1.7 Support MBC (AJL)
 ;
+;[2022/03/27] v1.8 Support RHYOPHYRE
+;
 ; Constants
 ;
 mask_data	.EQU	%10000000	; RTC data line
@@ -46,6 +48,7 @@ PORT_SCZ180	.EQU	$0C		; RTC port for SCZ180
 PORT_DYNO	.EQU	$0C		; RTC port for DYNO
 PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
+PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
 
 
 BDOS		.EQU	5		; BDOS invocation vector
@@ -1126,6 +1129,11 @@ HINIT:
 	LD	DE,PLT_MBC
 	CP	13		; MBC
 	JR	Z,RTC_INIT2
+;
+	LD	C,PORT_RPH
+	LD	DE,PLT_RPH
+	CP	14		; RHYOPHYRE
+	JR	Z,RTC_INIT2
 ;
 	; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
@@ -1622,7 +1630,7 @@ TESTING_BIT_DELAY_OVER:
 
 RTC_HELP_MSG:
 	.DB	0Ah, 0Dh		; line feed and carriage return
-	.TEXT	"RTC: Version 1.7"
+	.TEXT	"RTC: Version 1.8"
 	.DB	0Ah, 0Dh		; line feed and carriage return
 	.TEXT	"Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp"
 	.DB	0Ah, 0Dh		; line feed and carriage return
@@ -1751,6 +1759,7 @@ PLT_SCZ180	.TEXT	", SC Z180 RTC Module Latch Port 0x0C\r\n$"
 PLT_DYNO	.TEXT	", DYNO RTC Module Latch Port 0x0C\r\n$"
 PLT_RCZ280	.TEXT	", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"
 PLT_MBC		.TEXT	", MBC RTC Latch Port 0x70\r\n$"
+PLT_RPH		.TEXT	", RHYOPHYRE RTC Latch Port 0x84\r\n$"
 
 ;
 ; Generic FOR-NEXT loop algorithm

Source/CBIOS/cbios.asm

@@ -144,6 +144,43 @@ CBXSIZ	.EQU	$ - CBX
 	.ECHO	" bytes.\n"
 ;
 ;==================================================================================================
+; TIMDAT ROUTINE FOR QP/M
+;==================================================================================================
+;
+#IFDEF PLTWBW
+  #IF QPMTIMDAT
+;
+TIMDAT:
+	; GET CURRENT DATE/TIME FROM RTC INTO BUFFER
+	LD	B,BF_RTCGETTIM		; HBIOS GET TIME FUNCTION
+	LD	HL,CLKDAT		; POINTER TO BUFFER
+	RST	08			; DO IT
+;
+	; CONVERT ALL BYTES FROM BCD TO BINARY
+	LD	HL,CLKDAT		; BUFFER
+	LD	B,7			; DO 7 BYTES
+TIMDAT1:
+	LD	A,(HL)
+	CALL	BCD2BYTE
+	LD	(HL),A
+	INC	HL
+	DJNZ	TIMDAT1
+;
+	; SWAP BYTES 0 & 2 TO MAKE BUFFER INTO QP/M ORDER
+	LD	A,(CLKDAT+0)
+	PUSH	AF
+	LD	A,(CLKDAT+2)
+	LD	(CLKDAT+0),A
+	POP	AF
+	LD	(CLKDAT+2),A
+;
+	LD	HL,CLKDAT		; RETURN BUFFER ADDRESS
+	RET
+;
+  #ENDIF
+#ENDIF
+;
+;==================================================================================================
 ; CHARACTER DEVICE MAPPING
 ;==================================================================================================
 ;
@@ -302,6 +339,13 @@ BOOT:
 	; STANDARD BOOT INVOCATION
 	;LD	SP,STACK	; STACK FOR INITIALIZATION
 	LD	SP,CCP_LOC	; PUT STACK JUST BELOW CCP
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nCBIOS Starting...$"
+	CALL	PRTSTRD
+	.DB	"\r\nCopying INIT code to 0x8000...$"
+#ENDIF
 ;
 	; COPY INITIALIZATION CODE TO RUNNING LOCATION $8000
 	LD	HL,BUFPOOL
@@ -311,6 +355,11 @@ BOOT:
 	PUSH	HL		; SAVE START ADR AGAIN FOR BELOW
 	PUSH	BC		; SAVE LENGTH FOR BELOW
 	LDIR			; COPY THE CODE
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nClearing disk buffer...$"
+#ENDIF
 ;
 	; CLEAR BUFFER
 	POP	BC		; RECOVER LENGTH
@@ -320,10 +369,32 @@ BOOT:
 	INC	DE		; OFFSET DEST
 	DEC	BC		; REDUCE LEN BY ONE
 	LDIR			; USE LDIR TO FILL
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nStarting INIT routine at 0x8000$"
+#ENDIF
 ;
 	CALL	INIT		; PERFORM COLD BOOD ROUTINE
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nResetting CP/M...$"
+#ENDIF
 	CALL	RESCPM		; RESET CPM
+;
+#IF AUTOSUBMIT
+  #IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nPerforming Auto Submit...$"
+  #ENDIF
 	CALL	AUTOSUB		; PREP AUTO SUBMIT, IF APPROPRIATE
+#ENDIF
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nLaunching CP/M...$"
+#ENDIF
 ;
 	JR	GOCPM		; THEN OFF TO CP/M WE GO...
 ;
@@ -444,6 +515,12 @@ GOCPM:
 CURDSK:
 	LD	A,(CDISK)		; GET CURRENT USER/DISK
 GOCCP:
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nTransfer to CCP...$"
+#ENDIF
+;
 	LD	C,A			; SETUP C WITH CURRENT USER/DISK, ASSUME IT IS OK
 	JP	CCP_LOC			; JUMP TO COMMAND PROCESSOR
 ;
@@ -1680,6 +1757,12 @@ SLICE		.DB	0		; CURRENT SLICE
 SPS		.DW	0		; SECTORS PER SLICE
 STKSAV		.DW	0		; TEMP SAVED STACK POINTER
 ;
+#IFDEF PLTWBW
+  #IF QPMTIMDAT
+CLKDAT		.FILL	7,0		; RTC CLOCK DATA BUFFER
+  #ENDIF
+#ENDIF
+;
 #IFDEF PLTWBW
 BNKBIOS		.DB	0		; BIOS BANK ID
 BNKUSER		.DB	0		; USER BANK ID
@@ -2011,7 +2094,13 @@ BUFPOOL	.EQU	$		; START OF BUFFER POOL
 HEAPEND	.EQU	CBIOS_END - 64		; TOP OF HEAP MEM, END OF CBIOS LESS 32 ENTRY STACK
 ;
 INIT:
-	DI				; NO INTERRUPTS FOR NOW
+;
+#IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nStarting INIT....$"
+#ENDIF
+;
+	;DI				; NO INTERRUPTS FOR NOW
 
 	; ADJUST BOOT VECTOR TO REBOOT ROUTINE
 	LD	HL,REBOOT		; GET REBOOT ADDRESS
@@ -2068,12 +2157,21 @@ INIT:
 	LD	(BNKBIOS),A		; ... AND SAVE IT
 	LD	A,E			; GET USER BANK RETURNED IN E
 	LD	(BNKUSER),A		; ... AND SAVE IT
-
+;
+  #IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nReseting HBIOS....$"
+  #ENDIF
+;
 	; SOFT RESET HBIOS
 	LD	B,BF_SYSRESET		; HB FUNC: RESET
 	LD	C,BF_SYSRES_INT		; WARM START
 	RST	08			; DO IT
-
+;
+  #IF DEBUG
+	CALL	PRTSTRD
+	.DB	"\r\nCopying HCB....$"
+  #ENDIF
 	; CREATE A TEMP COPY OF THE HBIOS CONFIG BLOCK (HCB)
 	; FOR REFERENCE USE DURING INIT
 	LD	B,BF_SYSSETCPY		; HBIOS FUNC: SETUP BANK COPY
@@ -2264,6 +2362,17 @@ INIT3:
 	LD	DE,STR_TPA2		; AND TPA SUFFIX
 	CALL	WRITESTR
 	CALL	NEWLINE			; FORMATTING
+;
+; SETUP QP/M TIMDAT ROUTINE VECTOR IN ZERO PAGE AT 0x0010
+;
+#IFDEF PLTWBW
+  #IF QPMTIMDAT
+	LD	A,$C3			; JP INSTRUCTION
+	LD	($0010),A		; STORE AT 0x0008
+	LD	HL,TIMDAT		; ROUTINE ADDRESS
+	LD	($0011),HL		; SET VECTOR
+  #ENDIF
+#ENDIF
 ;
 	RET				; DONE
 ;
@@ -2275,6 +2384,9 @@ ERR_BIOMEM:
 ;
 ;
 ;__________________________________________________________________________________________________
+;
+#IF AUTOSUBMIT
+;
 AUTOSUB:
 ;
 	; SETUP AUTO SUBMIT COMMAND (IF REQUIRED FILES EXIST)
@@ -2306,6 +2418,8 @@ AUTOSUB:
 	LDIR				; PATCH COMMAND LINE INTO CCP
 	RET				; DONE
 ;
+#ENDIF
+;
 ;
 ;__________________________________________________________________________________________________
 DEV_INIT:

Source/CBIOS/config.asm

@@ -2,8 +2,11 @@
 ; CBIOS BUILD CONFIGURATION OPTIONS
 ;
 CLRRAMDISK	.EQU	CLR_AUTO	; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
+AUTOSUBMIT	.EQU	TRUE		; PROCESS PROFILE.SUB AT STARTUP
+QPMTIMDAT	.EQU	TRUE		; SUPPORT QP/M TIMDAT ROUTINE
 WRTCACHE	.EQU	TRUE		; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
 DSKTRACE	.EQU	FALSE		; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
+DEBUG		.EQU	FALSE		; MISCELLANEOUS DEBUG TRACING
 ;
 CPM_LOC		.EQU	$D000		; LOCATION OF START OF CCP
 ;

Source/CBIOS/util.asm

@@ -105,14 +105,61 @@ WRITESTR2:
 	POP	AF
 	RET
 ;
+#IF DEBUG
 ;
+; PRINT A STRING AT ADDRESS SPECIFIED IN HL
+; STRING MUST BE TERMINATED BY '$'
+; USAGE:
+;   LD	HL,MYSTR
+;   CALL PRTSTR
+;   ...
+;   MYSTR: .DB  "HELLO$"
 ;
-TSTPT:
-	PUSH	DE
-	LD	DE,STR_TSTPT
-	CALL	WRITESTR
-	POP	DE
-	JR	REGDMP			; DUMP REGISTERS AND RETURN
+PRTSTR:
+	LD	A,(HL)
+	INC	HL
+	CP	'$'
+	RET	Z
+	CALL	COUT
+	JR	PRTSTR
+;
+; PRINT A STRING DIRECT: REFERENCED BY POINTER AT TOP OF STACK
+; STRING MUST BE TERMINATED BY '$'
+; USAGE:
+;   CALL PRTSTRD
+;   .DB  "HELLO$"
+;   ...
+;
+PRTSTRD:
+	EX	(SP),HL
+	PUSH	AF
+	CALL	PRTSTR
+	POP	AF
+	EX	(SP),HL
+	RET
+;
+; PRINT A STRING INDIRECT: REFERENCED BY INDIRECT POINTER AT TOP OF STACK
+; STRING MUST BE TERMINATED BY '$'
+; USAGE:
+;   CALL PRTSTRI(MYSTRING)
+;   MYSTRING	.DB	"HELLO$"
+;
+PRTSTRI:
+	EX	(SP),HL
+	PUSH	AF
+	LD	A,(HL)
+	INC	HL
+	PUSH	HL
+	LD	H,(HL)
+	LD	L,A
+	CALL	PRTSTR
+	POP	HL
+	INC	HL
+	POP	AF
+	EX	(SP),HL
+	RET
+;
+#ENDIF
 ;
 ; PANIC: TRY TO DUMP MACHINE STATE
 ;
@@ -413,7 +460,52 @@ HEXCONV:
 	DAA	
 	ADC	A,40H
 	DAA	
-	RET	
+	RET
+;
+;****************************
+;	A(BCD) => A(BIN)
+;	[00H..99H] -> [0..99]
+;****************************
+;
+BCD2BYTE:
+	PUSH	BC
+	LD	C,A
+	AND	0F0H
+	SRL	A
+	LD	B,A
+	SRL	A
+	SRL	A
+	ADD	A,B
+	LD	B,A
+	LD	A,C
+	AND	0FH
+	ADD	A,B
+	POP	BC
+	RET
+;
+;*****************************
+;	 A(BIN) =>  A(BCD)
+;	[0..99] => [00H..99H]
+;*****************************
+;
+BYTE2BCD:
+	PUSH	BC
+	LD	B,10
+	LD	C,-1
+BYTE2BCD1:
+	INC	C
+	SUB	B
+	JR	NC,BYTE2BCD1
+	ADD	A,B
+	LD	B,A
+	LD	A,C
+	ADD	A,A
+	ADD	A,A
+	ADD	A,A
+	ADD	A,A
+	OR	B
+	POP	BC
+	RET
 ;
 ; PRINT A BYTE BUFFER IN HEX POINTED TO BY DE
 ; REGISTER A HAS SIZE OF BUFFER

Source/Doc/Architecture.md

@@ -223,6 +223,18 @@ initialization routine. At this point, the prior HBIOS code has been
 discarded and overwritten. Finally, the Boot Loader is invoked just like
 a ROM Boot.
 
+ROM-less Boot
+-------------
+
+Some hardware supported by RomWBW has a special mechanism for loading
+the initial code.  These systems have no ROM chips.  However, they
+have a small hardware bootstrap that loads a chunk of code from a
+disk device directlly into RAM at system startup.
+
+The startup then proceeds very much like the Application Boot
+process described above.  HBIOS is installed in it's operating bank
+and control is passed to the loader.
+
 Notes
 -----
 

Source/Fonts/fonts.txt

@@ -1,15 +1,27 @@
 Font files for ROMWBW.
 
+8x8: 8x8 cell, mostly IBM CGA, first 16 differ, thin font
+8x11: 8x11 cell, possibly VT-100?
+8x16: 8x16 cell, IBM MDA
+CGA: 8x16 cell, IBM CGA, normal (thick) CGA font, rows 8-15 are unused padding
+
 There are three fonts associated with ROMWBW supported hardware - ECB-SCG, ECB-CVDU and the ECB-VGA3.
 
 Name            Format      Size    Board & Display Mode
 ------------------------------------------------------------------------------------
-font8x8u.bin    8x8         2048    ECB-SCG, ECB-VGA3 (80x60)     
+font8x8u.bin    8x8         2048    ECB-SCG, ECB-VGA3 (80x60), MBC-VDP
 font8x11u.bin   8x11        2816    ECB-VGA3 (80x43)
 font8x16u.bin   8x16        4096    ECB-CVDU (80x25), ECB-VGA3 (80x24, 80x25, 80x30), MBC-VDC
-fontcgau.bin	8x8         4096    ECB-CVDU (80x25), MBC-VDC
+fontcgau.bin    8x16        4096    ECB-CVDU (80x25), MBC-VDC
 
-For inclusion in HBIOS the .bin format files must be convert to assembler .asm format.
+Notes:
+
+- The CGA font is roughly equivalent to the 8x8 font, but padded out to 8x16.  Scan lines
+  8-15 are unused.  The CVDU driver (8563 chip) always uses fonts defined in an 8x16 cell.
+  When the CVDU is configured for use with a CGA monitor, an 8x8 character cell is used,
+  but the font definition must still be 8x16.  The CGA font is used for this.
+
+For inclusion in HBIOS the .bin format files must be converted to assembler .asm format.
 This is acheived using the fonttool utility and is completed automatically as part of the build process.
 i.e. fonts files are converted to .asm format and then copied to the HBIOS directory. 
 

Source/HBIOS/Build.cmd

@@ -93,8 +93,10 @@ copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin osimg_small.bin || exit
 :: should yield a result of zero.
 ::
 
-for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
-  "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
+if %ROMSize% gtr 0 (
+    for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
+      "%TOOLS%\srecord\srec_cat.exe" %%f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o %%f -Binary || exit /b
+    )
 )
 
 ::
@@ -113,17 +115,23 @@ for %%f in (hbios_rom.bin osimg.bin osimg1.bin osimg2.bin) do (
 :: HBIOS on the fly for testing purposes.
 ::
 
-copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin + ..\RomDsk\rom%ROMSize%_wbw.dat %ROMName%.rom || exit /b
-copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
-copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+if %ROMSize% gtr 0 (
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin + ..\RomDsk\rom%ROMSize%_wbw.dat %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg.bin + osimg1.bin + osimg2.bin %ROMName%.upd || exit /b
+    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+) else (
+    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.rom || exit /b
+    copy /b hbios_rom.bin + osimg_small.bin %ROMName%.upd || exit /b
+    copy /b hbios_app.bin + osimg_small.bin %ROMName%.com || exit /b
+)
 
 ::
 :: Copy results to output directory
 ::
 
-copy %ROMName%.rom ..\..\Binary || exit /b
-copy %ROMName%.upd ..\..\Binary || exit /b
-copy %ROMName%.com ..\..\Binary || exit /b
+if exist %ROMName%.rom copy %ROMName%.rom ..\..\Binary || exit /b
+if exist %ROMName%.upd copy %ROMName%.upd ..\..\Binary || exit /b
+if exist %ROMName%.com copy %ROMName%.com ..\..\Binary || exit /b
 
 goto :eof
 
@@ -188,6 +196,7 @@ call Build RCZ80 kio 512 || exit /b
 call Build RCZ80 mt 512 || exit /b
 call Build RCZ80 duart 512 || exit /b
 call Build RCZ80 zrc 512 || exit /b
+call Build RCZ80 zrc_ram 0 || exit /b
 call Build RCZ180 ext 512 || exit /b
 call Build RCZ180 nat 512 || exit /b
 call Build RCZ280 ext 512 || exit /b
@@ -202,5 +211,6 @@ call Build EZZ80 std 512 || exit /b
 call Build EZZ80 tz80 512 || exit /b
 call Build DYNO std 512 || exit /b
 call Build UNA std 512 || exit /b
+call Build RPH std 512 || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
 #
 
 $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
 $PlatformListZ280 = "RCZ280"
 
 #
@@ -76,8 +76,8 @@ while ($true)
 
 while ($true)
 {
-	if (($RomSize -eq 128) -or ($RomSize -eq 256) -or ($RomSize -eq 512) -or ($RomSize -eq 1024)) {break}
-	$RomSize = (Read-Host -prompt "ROM Size [128|256|512|1024]").Trim()
+	if (($RomSize -eq 0) -or ($RomSize -eq 128) -or ($RomSize -eq 256) -or ($RomSize -eq 512) -or ($RomSize -eq 1024)) {break}
+	$RomSize = (Read-Host -prompt "ROM Size [0|128|256|512|1024]").Trim()
 }
 
 #

Source/HBIOS/Build.sh

@@ -26,6 +26,8 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; ROMSIZE="512"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; ROMSIZE="0"; bash Build.sh
+	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; ROMSIZE="512"; bash Build.sh
 	ROM_PLATFORM="MBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
@@ -71,7 +73,7 @@ if [ -z "${ROMSIZE}" ] ; then
 	ROMSIZE="512"
 fi
 
-while [ ! '(' "${ROMSIZE}" = 1024 -o "${ROMSIZE}" = 512 -o "${ROMSIZE}" = 256 -o "${ROMSIZE}" = 128 ')' ] ; do
+while [ ! '(' "${ROMSIZE}" = 1024 -o "${ROMSIZE}" = 512 -o "${ROMSIZE}" = 256 -o "${ROMSIZE}" = 128 -o "${ROMSIZE}" = 0 ')' ] ; do
 	echo -n "Romsize :"
 	read ROMSIZE
 done

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -0,0 +1,54 @@
+;
+;==================================================================================================
+;   RC2014 Z80 ZRC CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+;
+RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+;
+AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/RPH_std.asm

@@ -0,0 +1,41 @@
+;
+;==================================================================================================
+;   RHYOPHYRE STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rph.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+;
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+;
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Makefile

@@ -12,7 +12,7 @@ include $(TOOLS)/Makefile.inc
 
 FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
 
-ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO),)
+ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO RPH),)
 	TASM=$(BINDIR)/uz80as -t hd64180
 endif
 
@@ -56,18 +56,26 @@ $(ROMNAME).rom $(ROMNAME).com $(ROMNAME).img &: $(ROMDEPS)
 	if [ $(ROM_PLATFORM) != UNA ] ; then \
 		cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin usrrom.bin >osimg1.bin ; \
 		cat imgpad2.bin >osimg2.bin ; \
-		for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
-			srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
-		done \
+		if [ $(ROMSIZE) -gt 0 ] ; then \
+			for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
+				srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
+			done \
+		fi \
 	fi
 	if [ $(ROM_PLATFORM) = UNA ] ; then \
 		cp osimg.bin $(DEST)/UNA_WBW_SYS.bin ; \
 		cp ../RomDsk/rom$(ROMSIZE)_una.dat $(DEST)/UNA_WBW_ROM$(ROMSIZE).bin ; \
 		cat ../UBIOS/UNA-BIOS.BIN osimg.bin ../UBIOS/FSFAT.BIN ../RomDsk/rom$(ROMSIZE)_una.dat >$(ROMNAME).rom ; \
 	else \
-		cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/rom$(ROMSIZE)_wbw.dat >$(ROMNAME).rom ; \
-		cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
-		cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+		if [ $(ROMSIZE) -gt 0 ] ; then \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ../RomDsk/rom$(ROMSIZE)_wbw.dat >$(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg.bin osimg1.bin osimg2.bin >$(ROMNAME).upd ; \
+			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+		else \
+			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).rom ; \
+			cat hbios_rom.bin osimg_small.bin > $(ROMNAME).upd ; \
+			cat hbios_app.bin osimg_small.bin > $(ROMNAME).com ; \
+		fi \
 	fi
 
 prereq: $(FONTS) camel80.bin tastybasic.bin

Source/HBIOS/asci.asm

@@ -75,10 +75,14 @@ ASCI1_BASE	.EQU	Z180_BASE + 1	; RELATIVE TO Z180 INTERNAL IO PORTS
 ;
 ASCI_RTS	.EQU	%00010000	; ~RTS BIT OF CNTLA REG
 ;
-#IF (INTMODE == 2)
+#IF (ASCIINTS)
+;
+  #IF (INTMODE == 2)
 ;
 ASCI0_IVT	.EQU	IVT(INT_SER0)
 ASCI1_IVT	.EQU	IVT(INT_SER1)
+;
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -115,25 +119,29 @@ ASCI_PREINIT2:
 	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
 	DJNZ	ASCI_PREINIT0		; LOOP UNTIL DONE
 ;
-#IF (INTMODE >= 1)
+#IF (ASCIINTS)
+;
+  #IF (INTMODE >= 1)
 	; SETUP INT VECTORS AS APPROPRIATE
 	LD	A,(ASCI_DEV)		; GET DEVICE COUNT
 	OR	A			; SET FLAGS
 	JR	Z,ASCI_PREINIT3		; IF ZERO, NO ASCI DEVICES, ABORT
 ;
-#IF (INTMODE == 1)
+    #IF (INTMODE == 1)
 	; ADD IM1 INT CALL LIST ENTRY
 	LD	HL,ASCI_INT		; GET INT VECTOR
 	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
-#ENDIF
+    #ENDIF
 ;
-#IF (INTMODE == 2)
+    #IF (INTMODE == 2)
 	; SETUP IM2 VECTORS
 	LD	HL,ASCI_INT0
 	LD	(ASCI0_IVT),HL		; IVT INDEX
 	LD	HL,ASCI_INT1
 	LD	(ASCI1_IVT),HL		; IVT INDEX
-#ENDIF
+    #ENDIF
+;
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -188,7 +196,9 @@ ASCI_INIT1:
 ;
 ; RECEIVE INTERRUPT HANDLER
 ;
-#IF (INTMODE > 0)
+#IF (ASCIINTS)
+;
+  #IF (INTMODE > 0)
 ;
 ; IM1 ENTRY POINT
 ;
@@ -232,10 +242,10 @@ ASCI_INTRCV1:
 	ADD	A,8			; BUMP TO RDR PORT
 	LD	C,A			; PUT IN C, B IS STILL ZERO
 	IN	A,(C)			; READ PORT
-  #IF (ASCIBOOT != 0)
+    #IF (ASCIBOOT != 0)
 	CP	ASCIBOOT		; REBOOT REQUEST?
 	JP	Z,SYS_RESCOLD		; IF SO, DO IT, NO RETURN
-  #ENDIF
+    #ENDIF
 	LD	B,A			; SAVE BYTE READ
 	LD	L,(IY+6)		; SET HL TO
 	LD	H,(IY+7)		; ... START OF BUFFER STRUCT
@@ -292,6 +302,8 @@ ASCI_INTRCV3:
 ASCI_INTRCV4:
 	OR	$FF			; NZ SET TO INDICATE INT HANDLED
 	RET				; AND RETURN
+;
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -309,7 +321,7 @@ ASCI_FNTBL:
 	.ECHO	"*** INVALID ASCI FUNCTION TABLE ***\n"
 #ENDIF
 ;
-#IF (INTMODE == 0)
+#IF ((!ASCIINTS) | (INTMODE == 0))
 ;
 ASCI_IN:
 	CALL	ASCI_IST		; CHECK FOR CHAR READY
@@ -395,7 +407,7 @@ ASCI_OUT:
 ;
 ;
 ;
-#IF (INTMODE == 0)
+#IF ((!ASCIINTS) | (INTMODE == 0))
 ;
 ASCI_IST:
 	CALL	ASCI_ICHK		; ASCI INPUT CHECK
@@ -522,7 +534,7 @@ ASCI_INITGO:
 	OUT	(C),L			; WRITE CNTLB VALUE
 	INC	C			; BUMP TO
 	INC	C			; ... STAT REG, B IS STILL 0
-#IF (INTMODE > 0)
+#IF ((ASCIINTS) & (INTMODE > 0))
 	LD	A,$08			; SET RIE BIT ON
 #ELSE
 	XOR	A			; CLEAR RIE/TIE
@@ -534,7 +546,7 @@ ASCI_INITGO:
 	LD	A,$66			; STATIC VALUE FOR ASEXT
 	OUT	(C),A			; WRITE ASEXT REG
 ;
-#IF (INTMODE > 0)
+#IF ((ASCIINTS) & (INTMODE > 0))
 ;
 	; RESET THE RECEIVE BUFFER
 	LD	E,(IY+6)
@@ -609,6 +621,24 @@ ASCI_DETECT:
 ; DUE TO ENCODING BAUD IS ALWAYS DIVISIBLE BY 75
 ; Z180 DIVISOR IS ALWAYS A FACTOR OF 160
 ;
+; CNTLB=	XXPXDSSS
+; FAILSAVE = 	00100000
+;
+; PS (PRESCALE): 0=/10, 1=/30
+; DR (DIVIDE RATIO): 0=/16, 1=/64
+; SS2	SS1	SS0
+; ---	---	---
+; 0	0	0	/1
+; 0	0	1	/2
+; 0	1	0	/4
+; 0	1	1	/8
+; 1	0	0	/16
+; 1	0	1	/32
+; 1	1	0	/64
+;
+; FAILSAFE: CLOCK / 30 / 16 / 1 = CLOCK / 480
+;	IF CLOCK=18432000, BAUD=38400
+;
 ; X := CPU_HZ / 160 / 75 ==> SIMPLIFIED ==> X := CPU_KHZ / 12
 ; X := X / (BAUD / 75)
 ; IF X % 3 == 0, THEN (PS := 1, X := X / 3) ELSE PS=0
@@ -769,7 +799,7 @@ ASCI_STR_ASCIB	.DB	"ASCI W/BRG$"
 ;
 ASCI_DEV	.DB	0		; DEVICE NUM USED DURING INIT
 ;
-#IF (INTMODE == 0)
+#IF ((!ASCIINTS) | (INTMODE == 0))
 ;
 ASCI0_RCVBUF	.EQU	0
 ASCI1_RCVBUF	.EQU	0

Source/HBIOS/ay38910.asm

@@ -48,6 +48,14 @@ AY_RDAT		.EQU	$32
 AY_RIN		.EQU	$32
 #ENDIF
 ;
+#IF (AYMODE == AYMODE_MBC)
+AY_RSEL		.EQU	$A0
+AY_RDAT		.EQU	$A1
+AY_RIN		.EQU	AY_RSEL
+AY_ACR		.EQU	$A2
+AY_CLK		.SET	3579545 	; MSX NTSC COLOUR BURST FREQ = 315/88
+#ENDIF
+;
 ;======================================================================
 ;
 ;	REGISTERS
@@ -128,6 +136,10 @@ AY38910_INIT:
 	PRTS(" MODE=MSX$")
 #ENDIF
 ;
+#IF (AYMODE == AYMODE_MBC)
+	PRTS(" MODE=MBC$")
+#ENDIF
+;
 #IF (AYMODE == AYMODE_LINC)
 	PRTS(" MODE=LINC$")
 #ENDIF
@@ -136,7 +148,7 @@ AY38910_INIT:
 	LD	A,AY_RSEL
 	CALL	PRTHEXBYTE
 ;
-#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8))
+#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8) | (AYMODE == AYMODE_MBC))
 	LD	A,$FF			; ACTIVATE DEVICE BIT 4 IS AY RESET CONTROL, BIT 3 IS ACTIVE LED
 	OUT	(AY_ACR),A		; SET INIT AUX CONTROL REG
 #ENDIF

Source/HBIOS/cen.asm

@@ -0,0 +1,320 @@
+;
+;==================================================================================================
+; CENTRONICS INTERFACE DRIVER
+;==================================================================================================
+;
+; CENTRONICS-STYLE PARALLEL PRINTER DRIVER.  ASSUMES MBC PRINT BOARD
+; AS HARDWARE.
+;
+; IMPLEMENTED AS A ROMWBW CHARACTER DEVICE.  CURRENTLY HANDLES OUPUT
+; ONLY.
+;
+;  PORT 0 (INPUT/OUTPUT):
+;
+;	D7	D6	D5	D4	D3	D2	D1	D0
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;     | PD7   | PD6   | PD5   | PD4   | PD3   | PD2   | PD1   | PD0   |
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;
+;  PORT 1 (INPUT):
+;
+;	D7	D6	D5	D4	D3	D2	D1	D0
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;     | BUSY  | ACK   | POUT  | SEL   | ERR   | 0     | 0     | 0     |
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;
+;  PORT 2 (INPUT/OUTPUT):
+;
+;	D7	D6	D5	D4	D3	D2	D1	D0
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;     | STAT1 | STAT0 | ENBL  | PINT  | SEL   | RES   | LF    | STB   |
+;     +-------+-------+-------+-------+-------+-------+-------+-------+
+;
+CEN_NONE	.EQU	0
+CEN_MBC		.EQU	1
+;
+; PRE-CONSOLE INITIALIZATION - DETECT AND INIT HARDWARE
+;
+CEN_PREINIT:
+;
+; SETUP THE DISPATCH TABLE ENTRIES
+; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN
+; DISABLED.
+;
+	LD	B,CEN_CFGCNT		; LOOP CONTROL
+	XOR	A			; ZERO TO ACCUM
+	LD	(CEN_DEV),A		; CURRENT DEVICE NUMBER
+	LD	IY,CEN_CFG		; POINT TO START OF CFG TABLE
+CEN_PREINIT0:
+	PUSH	BC			; SAVE LOOP CONTROL
+	CALL	CEN_INITUNIT		; HAND OFF TO UNIT INIT CODE
+	POP	BC			; RESTORE LOOP CONTROL
+;
+	LD	A,(IY+1)		; GET THE CEN TYPE DETECTED
+	OR	A			; SET FLAGS
+	JR	Z,CEN_PREINIT2		; SKIP IT IF NOTHING FOUND
+;
+	PUSH	BC			; SAVE LOOP CONTROL
+	PUSH	IY			; CFG ENTRY ADDRESS
+	POP	DE			; ... TO DE
+	LD	BC,CEN_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	NZ,CIO_ADDENT		; ADD ENTRY IF CEN FOUND, BC:DE
+	POP	BC			; RESTORE LOOP CONTROL
+;
+CEN_PREINIT2:
+	LD	DE,CEN_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
+	DJNZ	CEN_PREINIT0		; LOOP UNTIL DONE
+;
+CEN_PREINIT3:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; CEN INITIALIZATION ROUTINE
+;
+CEN_INITUNIT:
+	CALL	CEN_DETECT		; DETERMINE CEN TYPE
+	LD	(IY+1),A		; SAVE IN CONFIG TABLE
+	OR	A			; SET FLAGS
+	RET	Z			; ABORT IF NOTHING THERE
+;
+	; UPDATE WORKING CEN DEVICE NUM
+	LD	HL,CEN_DEV		; POINT TO CURRENT DEVICE NUM
+	LD	A,(HL)			; PUT IN ACCUM
+	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
+	LD	(IY),A			; UPDATE UNIT NUM
+;
+	; SET DEFAULT CONFIG
+	LD	DE,-1			; LEAVE CONFIG ALONE
+	; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
+	; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
+	JP	CEN_INITDEVX		; IMPLEMENT IT AND RETURN
+;
+;
+;
+CEN_INIT:
+	LD	B,CEN_CFGCNT		; COUNT OF POSSIBLE CEN UNITS
+	LD	IY,CEN_CFG		; POINT TO START OF CFG TABLE
+CEN_INIT1:
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	A,(IY+1)		; GET CEN TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,CEN_PRTCFG		; PRINT IF NOT ZERO
+	POP	BC			; RESTORE LOOP CONTROL
+	LD	DE,CEN_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
+	DJNZ	CEN_INIT1		; LOOP TILL DONE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; DRIVER FUNCTION TABLE
+;
+CEN_FNTBL:
+	.DW	CEN_IN
+	.DW	CEN_OUT
+	.DW	CEN_IST
+	.DW	CEN_OST
+	.DW	CEN_INITDEV
+	.DW	CEN_QUERY
+	.DW	CEN_DEVICE
+#IF (($ - CEN_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID CEN FUNCTION TABLE ***\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
+; BYTE INTPUT
+;
+CEN_IN:
+	; INPUT NOT SUPPORTED - RETURN NULL BYTE
+	LD	E,0			; NULL BYTE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; BYTE OUTPUT
+;
+CEN_OUT:
+	CALL	CEN_OST			; READY TO SEND?
+	JR	Z,CEN_OUT		; LOOP IF NOT
+	; *** ADD CODE TO OUTPUT BYTE ***
+	LD	A,(IY+3)
+	LD	C,A			; PORT 0 (DATA)
+ 	OUT	(C),E			; OUTPUT DATA TO PORT
+ 	call 	DELAY   		; ignore anything back after a reset
+        ld      A,%00001101             ; select & strobe, LEDS OFF
+	INC 	C 			; PUT CONTROL PORT IN C
+	INC 	C
+        OUT	(C),A			; OUTPUT DATA TO PORT
+  	call 	DELAY   		; ignore anything back after a reset
+        ld      A,%00001100             ; select, LEDS OFF
+        OUT	(C),A			; OUTPUT DATA TO PORT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; INPUT STATUS
+;
+CEN_IST:
+	; INPUT NOT SUPPORTED - RETURN NOT READY
+	XOR	A			; ZERO BYTES AVAILABLE
+	RET				; DONE
+;
+; OUTPUT STATUS
+;
+CEN_OST:
+	LD	A,(IY+3)
+	LD	C,A			; PORT 0 (DATA)
+	INC 	C			; SELECT STATUS PORT
+ 	IN	A,(C)			; GET STATUS INFO
+    	AND	%10000000		; ONLY INTERESTED IN BUSY FLAG
+	RET				; DONE
+;
+; INITIALIZE DEVICE
+;
+CEN_INITDEV:
+	HB_DI				; AVOID CONFLICTS
+	CALL	CEN_INITDEVX		; DO THE REAL WORK
+	HB_EI				; INTS BACK ON
+	RET				; DONE
+;
+; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
+; PREINIT ABOVE.  PREINIT IS NOT ALLOWED TO ENABLE INTS!
+;
+CEN_INITDEVX:
+	LD	A,(IY+3)
+	LD	C,A			; PORT 0 (DATA)
+	XOR	A			; CLEAR ACCUM
+	OUT	(C),A			; SEND IT
+	INC	C			; BUMP TO
+	INC	C			; ... PORT 2
+	LD	A,%00001000		; SELECT AND ASSERT RESET, LEDS OFF
+	OUT	(C),A			; SEND IT
+ 	CALL	LDELAY			; HALF SECOND DELAY
+	LD	A,%00001100		; SELECT AND DEASSERT RESET, LEDS OFF
+	OUT	(C),A			; SEND IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; RETURN
+;
+;
+;
+CEN_QUERY:
+	LD	E,(IY+4)		; FIRST CONFIG BYTE TO E
+	LD	D,(IY+5)		; SECOND CONFIG BYTE TO D
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;
+;
+CEN_DEVICE:
+	LD	D,CIODEV_CEN		; D := DEVICE TYPE
+	LD	E,(IY)			; E := PHYSICAL UNIT
+	LD	C,$40			; C := DEVICE TYPE, 0x40 IS PIO
+	LD	H,(IY+1)		; H := MODE
+	LD	L,(IY+3)		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; CEN DETECTION ROUTINE
+;
+CEN_DETECT:
+	LD	A,(IY+3)		; BASE PORT ADDRESS
+	ADD	A,2			; USE PORT 2 FOR DETECT
+	LD	C,A			; PUT IN C FOR I/O
+	CALL	CEN_DETECT2		; CHECK IT
+	JR	Z,CEN_DETECT1		; FOUND IT, RECORD IT
+	LD	A,CEN_NONE		; NOTHING FOUND
+	RET				; DONE
+;
+CEN_DETECT1:
+	; CEN FOUND, RECORD IT
+	LD	A,CEN_MBC		; RETURN CHIP TYPE
+	RET				; DONE
+;
+CEN_DETECT2:
+	; LOOK FOR CEN AT PORT ADDRESS IN C
+	XOR	A			; DEFAULT VALUE
+	OUT	(C),A			; SEND IT
+	IN	A,(C)			; READ IT
+	AND	%11000000		; ISOLATE STATUS BITS
+	CP	%00000000		; CORRECT VALUE?
+	RET	NZ			; IF NOT, RETURN
+	LD	A,%11000000		; STATUS BITS ON (LEDS OFF)
+	OUT	(C),A			; SEND IT
+	IN	A,(C)			; READ IT
+	AND	%11000000		; ISOLATE STATUS BITS
+	CP	%11000000		; CORRECT VALUE?
+	RET				; RETURN (ZF SET CORRECTLY)
+;
+;
+;
+CEN_PRTCFG:
+	; ANNOUNCE PORT
+	CALL	NEWLINE			; FORMATTING
+	PRTS("CEN$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": IO=0x$")		; FORMATTING
+	LD	A,(IY+3)		; GET BASE PORT
+	CALL	PRTHEXBYTE		; PRINT BASE PORT
+
+	; PRINT THE CEN TYPE
+	CALL	PC_SPACE		; FORMATTING
+	LD	A,(IY+1)		; GET CEN TYPE BYTE
+	RLCA				; MAKE IT A WORD OFFSET
+	LD	HL,CEN_TYPE_MAP		; POINT HL TO TYPE MAP TABLE
+	CALL	ADDHLA			; HL := ENTRY
+	LD	E,(HL)			; DEREFERENCE
+	INC	HL			; ...
+	LD	D,(HL)			; ... TO GET STRING POINTER
+	CALL	WRITESTR		; PRINT IT
+;
+	; ALL DONE IF NO CEN WAS DETECTED
+	LD	A,(IY+1)		; GET CEN TYPE BYTE
+	OR	A			; SET FLAGS
+	RET	Z			; IF ZERO, NOT PRESENT
+;
+	; *** ADD MORE DEVICE INFO??? ***
+;
+	XOR	A
+	RET
+;
+;
+;
+CEN_TYPE_MAP:
+		.DW	CEN_STR_NONE
+		.DW	CEN_STR_MBC
+;
+CEN_STR_NONE	.DB	"<NOT PRESENT>$"
+CEN_STR_MBC	.DB	"MBC$"
+;
+; WORKING VARIABLES
+;
+CEN_DEV		.DB	0		; DEVICE NUM USED DURING INIT
+;
+; CEN DEVICE CONFIGURATION TABLE
+;
+CEN_CFG:
+;
+CEN0_CFG:
+	; CEN MODULE A CONFIG
+	.DB	0			; DEVICE NUMBER (SET DURING INIT)
+	.DB	0			; CEN TYPE (SET DURING INIT)
+	.DB	0			; MODULE ID
+	.DB	CEN0BASE		; BASE PORT
+	.DW	0			; LINE CONFIGURATION
+;
+CEN_CFGSIZ	.EQU	$ - CEN_CFG	; SIZE OF ONE CFG TABLE ENTRY
+;
+#IF (CENCNT >= 2)
+;
+CEN1_CFG:
+	; CEN MODULE B CONFIG
+	.DB	0			; DEVICE NUMBER (SET DURING INIT)
+	.DB	0			; CEN TYPE (SET DURING INIT)
+	.DB	1			; MODULE ID
+	.DB	CEN1BASE		; BASE PORT
+	.DW	0			; LINE CONFIGURATION
+;
+#ENDIF
+;
+CEN_CFGCNT	.EQU	($ - CEN_CFG) / CEN_CFGSIZ

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -100,6 +100,7 @@ DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -115,9 +116,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -125,7 +126,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -179,6 +180,10 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -192,7 +197,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_ezz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -153,9 +153,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -163,7 +163,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -221,6 +221,10 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -234,7 +238,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -30,7 +30,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
@@ -60,6 +60,11 @@ N8_ACR		.EQU	$94		; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
 N8_RMAP		.EQU	$96		; N8: ROM PAGE REGISTER ADR
 N8_DEFACR	.EQU	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
 ;
+RPH_PPI0	.EQU	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
+RPH_RTC		.EQU	$84		; RPH: RTC LATCH REGISTER ADR
+RPH_ACR		.EQU	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
+RPH_DEFACR	.EQU	$00		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
 MK4_IDE		.EQU	$80		; MK4: IDE REGISTERS BASE ADR
 MK4_XAR		.EQU	$88		; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
 MK4_SD		.EQU	$89		; MK4: SD CARD CONTROL REGISTER ADR
@@ -153,6 +158,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -205,9 +211,11 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
+GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -286,6 +294,16 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+CENCNT		.EQU	1		; CEN: NUMBER OF CHIPS TO DETECT (1-2)
+CEN0BASE	.EQU	$E8		; CEN 0: REGISTERS BASE ADR
+CEN1BASE	.EQU	$EC		; CEN 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -303,7 +321,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -141,9 +141,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	TRUE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -152,7 +152,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
@@ -218,6 +218,16 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
+PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	TRUE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+CENCNT		.EQU	1		; CEN: NUMBER OF CHIPS TO DETECT (1-2)
+CEN0BASE	.EQU	$E8		; CEN 0: REGISTERS BASE ADR
+CEN1BASE	.EQU	$EC		; CEN 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -233,9 +243,9 @@ AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AY38910ENABLE	.EQU	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	3579545 / 2	; DEFAULT TO CPUOSC / 4
+AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
@@ -122,6 +122,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -140,9 +141,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -151,7 +152,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -219,6 +220,13 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -236,7 +244,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
@@ -124,6 +124,7 @@ UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -142,9 +143,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -153,7 +154,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -217,6 +218,13 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -234,7 +242,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -125,6 +125,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -159,9 +160,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -169,7 +170,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -233,6 +234,13 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -246,7 +254,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -175,9 +175,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -185,7 +185,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -249,6 +249,13 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -262,7 +269,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -164,9 +164,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -174,7 +174,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -238,6 +238,13 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -251,7 +258,7 @@ SNMODE		.EQU	SNMODE_RCZ80	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_rph.asm

@@ -0,0 +1,251 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "RHYOPHYRE"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
+MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+;
+Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RPH_PPI0	.EQU	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
+RPH_RTC		.EQU	$84		; RPH: RTC LATCH REGISTER ADR
+RPH_ACR		.EQU	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
+RPH_DEFACR	.EQU	$20		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
+RTCIO		.EQU	RPH_RTC		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY
+DSKYMODE	.EQU	DSKYMODE_V1	; DSKY VERSION: DSKYMODE_[V1|NG]
+DSKYPPIBASE	.EQU	RPH_PPI0		; BASE I/O ADDRESS OF DSKY PPI
+DSKYOSC		.EQU	3000000		; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
+UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.EQU	TRUE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
+GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
+FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	RPH_PPI0	; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
+SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.EQU	RPH_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
+SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
+AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -141,9 +141,9 @@ VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
@@ -152,7 +152,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
@@ -218,6 +218,13 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -235,7 +242,7 @@ SNMODE		.EQU	SNMODE_VGM	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
@@ -120,6 +120,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
 ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
 ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
@@ -154,9 +155,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_RC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -164,7 +165,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -228,6 +229,13 @@ PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (P
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -241,7 +249,7 @@ SNMODE		.EQU	SNMODE_NONE	; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_una.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
@@ -114,9 +114,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -162,6 +162,13 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -33,7 +33,7 @@ DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
@@ -125,9 +125,9 @@ XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-NECENABLE	.EQU	FALSE		; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|RC|RCV9958|RCKBD]
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 ;
@@ -135,7 +135,7 @@ MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM 
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
@@ -173,6 +173,10 @@ PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
+CENENABLE	.EQU	FALSE		; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/dsrtc.asm

@@ -66,28 +66,28 @@
 ; RTC LATCH WRITE
 ; ---------------
 ;
-; BIT	SBC	SBC-004	MFPIC	N8	N8-CSIO	MK4	SC130	SC131	SC126		MBC
-; -----	-------	-------	-------	-------	-------	-------	-------	-------	---------------	-------
-; D7	RTC_OUT RTC_OUT	--	RTC_OUT RTC_OUT	RTC_OUT	--	--	RTC_OUT,I2C_SDA	RTC_OUT
-; D6	RTC_CLK RTC_CLK	--	RTC_CLK RTC_CLK	RTC_CLK	--	--	RTC_CLK		RTC_CLK
-; D5	/RTC_WE /RTC_WE	--	/RTC_WE /RTC_WE	/RTC_WE	--	--	/RTC_WE		/RTC_WE
-; D4	RTC_CE	RTC_CE	--	RTC_CE  RTC_CE	RTC_CE	--	--	RTC_CE		RTC_CE
-; D3	NC	CLKSEL	/RTC_CE	NC	NC	NC	--	--	/SPI_CS2	CLKSEL
-; D2	NC	SPK	RTC_CLK	SPI_CS	SPI_CS	NC	/SPI_CS1/SPI_CS1/SPI_CS1	SPK
-; D1	--	--	RTC_WE	SPI_CLK	NC	NC	--	--	FS		LED1
-; D0	--	--	RTC_OUT	SPI_DI	NC	NC	--	--	I2C_SCL		LED0
+; BIT	SBC	SBC-004	MFPIC	N8	N8-CSIO	MK4	SC130	SC131	SC126		MBC	RPH
+; -----	-------	-------	-------	-------	-------	-------	-------	-------	---------------	------- -------
+; D7	RTC_OUT RTC_OUT	--	RTC_OUT RTC_OUT	RTC_OUT	--	--	RTC_OUT,I2C_SDA	RTC_OUT	RTC_OUT
+; D6	RTC_CLK RTC_CLK	--	RTC_CLK RTC_CLK	RTC_CLK	--	--	RTC_CLK		RTC_CLK	RTC_CLK
+; D5	/RTC_WE /RTC_WE	--	/RTC_WE /RTC_WE	/RTC_WE	--	--	/RTC_WE		/RTC_WE	/RTC_WE
+; D4	RTC_CE	RTC_CE	--	RTC_CE  RTC_CE	RTC_CE	--	--	RTC_CE		RTC_CE	RTC_CE
+; D3	NC	CLKSEL	/RTC_CE	NC	NC	NC	--	--	/SPI_CS2	CLKSEL	--
+; D2	NC	SPK	RTC_CLK	SPI_CS	SPI_CS	NC	/SPI_CS1/SPI_CS1/SPI_CS1	SPK	--
+; D1	--	--	RTC_WE	SPI_CLK	NC	NC	--	--	FS		LED1	--
+; D0	--	--	RTC_OUT	SPI_DI	NC	NC	--	--	I2C_SCL		LED0	--
 ;
 ; RTC LATCH READ
 ; --------------
 ;
-; D7	--	--	--	--	--	--	--	--	I2C_SDA		--
-; D6	CFG	CFG	--	SPI_DO	CFG	--	--	--	--		CFG
-; D5	--	--	--	--	--	--	--	--	--		--
-; D4	--	--	--	--	--	--	--	--	--		--
-; D3	--	--	--	--	--	--	--	--	--		--
-; D2	--	--	--	--	--	--	--	--	--		--
-; D1	----	--	--	--	--	--	--	--	--		CLKSEL
-; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN
+; D7	--	--	--	--	--	--	--	--	I2C_SDA		--	--
+; D6	CFG	CFG	--	SPI_DO	CFG	--	--	--	--		CFG	--
+; D5	--	--	--	--	--	--	--	--	--		--	--
+; D4	--	--	--	--	--	--	--	--	--		--	--
+; D3	--	--	--	--	--	--	--	--	--		--	--
+; D2	--	--	--	--	--	--	--	--	--		--	--
+; D1	----	--	--	--	--	--	--	--	--		CLKSEL	--
+; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;

Source/HBIOS/gdc.asm

@@ -0,0 +1,331 @@
+;======================================================================
+;	UPD7220 GRAPHICS DEVICE CONTROLLER
+;======================================================================
+;
+;======================================================================
+; GDC DRIVER - CONSTANTS
+;======================================================================
+;
+#IF (GDCMODE == GDCMODE_ECB)
+GDC_BASE	.EQU	$??		; GDC BASE I/O PORT
+GDC_DAC_BASE	.EQU	$??		; RAMDAC BASE I/O PORT
+#ENDIF
+;
+#IF (GDCMODE == GDCMODE_RPH)
+GDC_KBDDATA	.EQU	$8C		; KBD CTLR DATA PORT
+GDC_KBDST	.EQU	$8D		; KBD CTLR STATUS/CMD PORT
+GDC_BASE	.EQU	$90		; GDC BASE I/O PORT
+GDC_DAC_BASE	.EQU	$98		; RAMDAC BASE I/O PORT
+#ENDIF
+;
+GDC_STAT	.EQU	GDC_BASE + 0		; STATUS PORT
+GDC_CMD		.EQU	GDC_BASE + 1		; COMMAND PORT
+GDC_PARAM	.EQU	GDC_BASE + 0		; PARAM PORT
+GDC_READ	.EQU	GDC_BASE + 1		; READ PORT
+GDC_DAC_WR	.EQU	GDC_DAC_BASE + 0	; RAMDAC ADR WRITE
+GDC_DAC_RD      .EQU	GDC_DAC_BASE + 3	; RAMDAC ADR READ
+GDC_DAC_PALRAM  .EQU	GDC_DAC_BASE + 1	; RAMDAC PALETTE RAM
+GDC_DAC_PIXMSK  .EQU	GDC_DAC_BASE + 2	; RAMDAC PIXEL READ MASK
+GDC_DAC_OVL_WR  .EQU	GDC_DAC_BASE + 4	; RAMDAC OVERLAY WRITE
+GDC_DAC_OVL_RD  .EQU	GDC_DAC_BASE + 7	; RAMDAC OVERLAY READ
+GDC_DAC_OVL_RAM .EQU	GDC_DAC_BASE + 5	; RAMDAC OVERLAY RAM
+;
+GDC_ROWS	.EQU	25
+GDC_COLS	.EQU	80
+;
+; *** TODO: CGA AND EGA ARE PLACEHOLDERS.  THESE EQUATES SHOULD
+; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT
+; DEFINITIONS.
+;
+#IF (GDCMON == GDCMON_CGA)
+  #DEFINE	USEFONTCGA
+  #DEFINE	GDC_FONT FONTCGA
+#ENDIF
+;
+#IF (GDCMON == GDCMON_EGA)
+  #DEFINE	USEFONT8X16
+  #DEFINE	GDC_FONT FONT8X16
+#ENDIF
+;
+TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
+;
+;======================================================================
+; GDC DRIVER - INITIALIZATION
+;======================================================================
+;
+GDC_INIT:
+	LD	IY,GDC_IDAT		; POINTER TO INSTANCE DATA
+	
+	CALL	NEWLINE
+	PRTS("GDC: MODE=$")
+#IF (GDCMODE == GDCMODE_ECB)
+	PRTS("ECB$")
+#ENDIF
+#IF (GDCMODE == GDCMODE_RPH)
+	PRTS("RPH$")
+#ENDIF
+;
+#IF (GDCMON == GDCMON_CGA)
+	PRTS(" CGA$")
+#ENDIF	
+#IF (GDCMON == GDCMON_EGA)
+	PRTS(" EGA$")
+#ENDIF	
+;
+	PRTS(" IO=0x$")
+	LD	A,GDC_BASE
+	CALL	PRTHEXBYTE
+	CALL	GDC_PROBE		; CHECK FOR HW PRESENCE
+	JR	Z,GDC_INIT1		; CONTINUE IF HW PRESENT
+;
+	; HARDWARE NOT PRESENT
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+GDC_INIT1:
+	CALL 	GDC_CRTINIT		; SETUP THE GDC CHIP REGISTERS
+	CALL	GDC_VDARES		; RESET GDC
+	CALL	KBD_INIT		; INITIALIZE KEYBOARD DRIVER
+
+	; ADD OURSELVES TO VDA DISPATCH TABLE
+	LD	BC,GDC_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	LD	DE,GDC_IDAT		; DE := GDC INSTANCE DATA PTR
+	CALL	VDA_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+
+	; INITIALIZE EMULATION
+	LD	C,A			; C := ASSIGNED VIDEO DEVICE NUM
+	LD	DE,GDC_FNTBL		; DE := FUNCTION TABLE ADDRESS
+	LD	HL,GDC_IDAT		; HL := GDC INSTANCE DATA PTR
+	CALL	TERM_ATTACH		; DO IT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; GDC DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS
+;======================================================================
+;
+GDC_FNTBL:
+	.DW	GDC_VDAINI
+	.DW	GDC_VDAQRY
+	.DW	GDC_VDARES
+	.DW	GDC_VDADEV
+	.DW	GDC_VDASCS
+	.DW	GDC_VDASCP
+	.DW	GDC_VDASAT
+	.DW	GDC_VDASCO
+	.DW	GDC_VDAWRC
+	.DW	GDC_VDAFIL
+	.DW	GDC_VDACPY
+	.DW	GDC_VDASCR
+	.DW	KBD_STAT
+	.DW	KBD_FLUSH
+	.DW	KBD_READ
+	.DW	GDC_VDARDC
+#IF (($ - GDC_FNTBL) != (VDA_FNCNT * 2))
+	.ECHO	"*** INVALID GDC FUNCTION TABLE ***\n"
+	!!!!!
+#ENDIF
+;
+GDC_VDAINI:
+	; RESET VDA
+	CALL	GDC_VDARES		; RESET VDA
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+GDC_VDAQRY:	; VIDEO INFORMATION QUERY
+	LD	C,$00		; MODE ZERO IS ALL WE KNOW
+	LD	D,GDC_ROWS	; ROWS
+	LD	E,GDC_COLS	; COLS
+	LD	HL,0		; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED YET
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+GDC_VDARES:	; VIDEO SYSTEM RESET
+	; *** TODO: RESET VIDEO SYSTEM HERE, CLEAR SCREEN,
+	; CURSOR TO TOP LEFT, CLEAR ATTRIBUTES
+	XOR	A
+	RET
+;
+GDC_VDADEV:	; VIDEO DEVICE INFORMATION
+	LD	D,VDADEV_GDC	; D := DEVICE TYPE
+	LD	E,0		; E := PHYSICAL UNIT IS ALWAYS ZERO
+	LD	H,0		; H := 0, DRIVER HAS NO MODES
+	LD	L,GDC_BASE	; L := BASE I/O ADDRESS
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+GDC_VDASCS:	; SET CURSOR STYLE
+	CALL	SYSCHK		; NOT IMPLEMENTED (YET)
+	LD	A,ERR_NOTIMPL
+	OR	A
+	RET
+
+GDC_VDASCP:	; SET CURSOR POSITION
+	CALL	GDC_XY		; SET CURSOR POSITION
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDASAT:	; SET ATTRIBUTES
+	LD	A,E		; GET THE INCOMING ATTRIBUTE
+	LD	(GDC_ATTR),A	; AND SAVE FOR LATER
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDASCO:	; SET COLOR
+	LD	A,E		; GET THE INCOMING COLOR
+	LD	(GDC_COLOR),A	; AND SAVE FOR LATER
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDAWRC:	; WRITE CHARACTER
+	LD	A,E		; CHARACTER TO WRITE GOES IN A
+	CALL	GDC_PUTCHAR	; PUT IT ON THE SCREEN
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDAFIL:	; FILL WITH CHARACTER
+	LD	A,E		; FILL CHARACTER GOES IN A
+	EX	DE,HL		; FILL LENGTH GOES IN DE
+	CALL	GDC_FILL	; DO THE FILL
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+GDC_VDACPY:	; COPY CHARACTERS/ATTRIBUTES
+	; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS GDC_POS
+	; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT
+	PUSH	HL		; SAVE LENGTH
+	CALL	GDC_XY2IDX	; ROW/COL IN DE -> SOURCE ADR IN HL
+	POP	BC		; RECOVER LENGTH IN BC
+	LD	DE,(GDC_POS)	; PUT DEST IN DE
+	JP	GDC_BLKCPY	; DO A BLOCK COPY
+
+GDC_VDASCR:	; SCROLL ENTIRE SCREEN
+	LD	A,E		; LOAD E INTO A
+	OR	A		; SET FLAGS
+	RET	Z		; IF ZERO, WE ARE DONE
+	PUSH	DE		; SAVE E
+	JP	M,GDC_VDASCR1	; E IS NEGATIVE, REVERSE SCROLL
+	CALL	GDC_SCROLL	; SCROLL FORWARD ONE LINE
+	POP	DE		; RECOVER E
+	DEC	E		; DECREMENT IT
+	JR	GDC_VDASCR	; LOOP
+GDC_VDASCR1:
+	CALL	GDC_RSCROLL	; SCROLL REVERSE ONE LINE
+	POP	DE		; RECOVER E
+	INC	E		; INCREMENT IT
+	JR	GDC_VDASCR	; LOOP
+;
+GDC_VDARDC:	; READ CHAR/ATTR VALUE FROM VIDEO BUFFER
+	OR	$FF		; UNSUPPORTED FUNCTION
+	RET
+;
+;======================================================================
+; GDC DRIVER - PRIVATE DRIVER FUNCTIONS
+;======================================================================
+;
+;----------------------------------------------------------------------
+; PROBE FOR GDC HARDWARE
+;----------------------------------------------------------------------
+;
+; ON RETURN, ZF SET INDICATES HARDWARE FOUND
+;
+; *** TODO: IMPLEMENT THIS
+;
+GDC_PROBE:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; RETURN WITH ZF SET BASED ON CP
+;
+;----------------------------------------------------------------------
+; DISPLAY CONTROLLER CHIP INITIALIZATION
+;----------------------------------------------------------------------
+;
+; *** TODO: IMPLEMENT THIS
+;
+GDC_CRTINIT:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;----------------------------------------------------------------------
+; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E
+;----------------------------------------------------------------------
+;
+GDC_XY:
+	CALL	GDC_XY2IDX		; CONVERT ROW/COL TO BUF IDX
+	LD	(GDC_POS),HL		; SAVE THE RESULT (DISPLAY POSITION)
+	; *** TODO: MOVE THE CURSOR
+	RET
+;
+;----------------------------------------------------------------------
+; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL
+; D=ROW, E=COL
+;----------------------------------------------------------------------
+;
+GDC_XY2IDX:
+	LD	A,E			; SAVE COLUMN NUMBER IN A
+	LD	H,D			; SET H TO ROW NUMBER
+	LD	E,GDC_COLS		; SET E TO ROW LENGTH
+	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET
+	LD	E,A			; GET COLUMN BACK
+	ADD	HL,DE			; ADD IT IN
+	RET				; RETURN
+;
+;----------------------------------------------------------------------
+; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR
+;----------------------------------------------------------------------
+;
+GDC_PUTCHAR:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; FILL AREA IN BUFFER WITH SPECIFIED CHARACTER AND CURRENT COLOR/ATTRIBUTE
+; STARTING AT THE CURRENT FRAME BUFFER POSITION
+;   A: FILL CHARACTER
+;   DE: NUMBER OF CHARACTERS TO FILL
+;----------------------------------------------------------------------
+;
+GDC_FILL:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+GDC_SCROLL:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+GDC_RSCROLL:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;----------------------------------------------------------------------
+; BLOCK COPY BC BYTES FROM HL TO DE
+;----------------------------------------------------------------------
+;
+GDC_BLKCPY:
+	; *** TODO: IMPLEMENT THIS
+	RET
+;
+;==================================================================================================
+;   GDC DRIVER - DATA
+;==================================================================================================
+;
+GDC_ATTR	.DB	0	; CURRENT ATTRIBUTES
+GDC_COLOR	.DB	0	; CURRENT COLOR
+GDC_POS		.DW 	0	; CURRENT DISPLAY POSITION
+;
+;==================================================================================================
+;   GDC DRIVER - INSTANCE DATA
+;==================================================================================================
+;
+GDC_IDAT:
+	.DB	GDC_KBDST
+	.DB	GDC_KBDDATA

Source/HBIOS/hbios.asm

@@ -513,7 +513,7 @@ HBX_BNKSEL1:
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
-	ADD	A,$10			; ADD 16 x 32K - RAM STARTS FROM 512K
+	ADD	A,ROMSIZE / 32		; STARTING RAM BANK NUMBER OFFSET
 ;
 HBX_ROM:
 	OUT	($1F),A			; HCS WRITE TO THE BANK CONTROL REGISTER
@@ -556,6 +556,28 @@ HBX_RAMX:
 HBX_MMA	.DB	0			; TEMPORARY STORAGE FOR REG A
 #ENDIF
 ;
+#IF (MEMMGR == MM_RPH)
+	BIT	7,A			; TEST BIT 7 FOR RAM VS. ROM
+	JR	Z,HBX_ROM		; IF NOT SET, SELECT ROM PAGE
+;
+HBX_RAM:
+	AND	%00011111		; AVOID WRAPPING BITS
+	RLCA				; SCALE SELECTOR TO
+	RLCA				; ... GO FROM Z180 4K PAGE SIZE
+	RLCA				; ... TO DESIRED 32K PAGE SIZE
+	OUT0	(Z180_BBR),A		; WRITE TO BANK BASE
+	LD	A,RPH_DEFACR | 80H	; SELECT RAM BY SETTING BIT 7
+	OUT0	(RPH_ACR),A		; ... IN RPH ACR REGISTER
+	RET				; DONE
+;
+HBX_ROM:
+	OR	RPH_DEFACR		; COMBINE WITH DEFAULT BITS
+	OUT0	(RPH_ACR),A		; BANK INDEX TO RPH ACR REGISTER
+	XOR	A			; ZERO ACCUM
+	OUT0	(Z180_BBR),A		; ZERO BANK BASE
+	RET				; DONE
+#ENDIF
+;
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Copy Data - Possibly between banks.  This resembles CP/M 3, but
 ;  usage of the HL and DE registers is reversed.
@@ -1101,6 +1123,11 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 	OUT0	(N8_ACR),A		; ... REGISTER IS INITIALIZED
 #ENDIF
 ;
+#IF (PLATFORM == PLT_RPH)
+	LD	A,RPH_DEFACR		; ENSURE RPH ACR
+	OUT0	(RPH_ACR),A		; ... REGISTER IS INITIALIZED
+#ENDIF
+;
 #IF (DIAGENABLE)
 	LD	A,%00000001
 	OUT	(DIAGPORT),A
@@ -1238,7 +1265,7 @@ Z280_INITZ:
 	LD	A,$F0
 	OUT0	(Z180_DCNTL),A
 
-  #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
+  #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8) | (MEMMGR == MM_RPH))
 	; Z180 MMU SETUP
 	LD	A,$80
 	OUT0	(Z180_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
@@ -1530,16 +1557,60 @@ MBC_SINGLE:
 ;
 #ENDIF
 ;
-; IF THIS IS NOT A ROMBOOT, THEN WE NEED TO COPY THE "APP" BANK TO
-; TPA.  IT IS DONE PRIOR TO COPYING HBIOS TO IT'S FINAL BANK BECAUSE
-; THE SOURCE OF THE APP BANK CODE MAY BE THE BANK THAT HBIOS WANTS TO
-; USE AS IT'S FINAL LOCATION (PRIMARILY IN CASE OF RAMBOOT WHERE THE
-; SYSTEM HAS THE MINIMUM 128KB OF RAM).
+; IF THIS IS A ROM-LESS SYSTEM, THEN WE NEED TO COPY THE PAYLOAD
+; (LOADER, MONITOR, ZSDOS) THAT HAS BEEN LOADED TO PHYSICAL RAM
+; BANKS 0 AND 1 TO THE USER TPA BANK TO RUN AFTER BOOT.
+; IT IS DONE PRIOR TO COPYING HBIOS TO IT'S FINAL BANK BECAUSE
+; THE PAYLOAD MAY EXTEND INTO THE HBIOS OPERATING BANK.  THIS
+; HAPPENS PRIMARILY IN THE CASE WHERE THE
+; SYSTEM HAS THE MINIMUM 128KB OF RAM.
 ;
-
-
-
-
+#IFDEF ROMBOOT
+  #IF (ROMSIZE == 0)
+ ; 
+	; THE PAYLOAD IS LIKELY TO CROSS OVER THE RAM BANK 0/1
+	; BOUNDARY.  BNKCPY DOES NOT HANDLE THIS BECAUSE IT ASSUMES
+	; THE COMMON BANK IS USED AFTER PASSING OVER THE BANK
+	; BOUNDARY.  WE WORK AROUND THAT HERE BY DOING TWO COPIES.
+	; THE FIRST ONE HANDLES THE PORTION OF THE PAYLOAD FROM THE
+	; END OF HBIOS TO THE BANK BOUNDARY ($8000).  THE SECOND
+	; ONE HANDLES THE PORTION THAT EXTENDS INTO THE SECOND
+	; PHYSICAL RAM BANK.
+;
+	; COPY PORTION OF PAYLOAD FOLLOWING HBIOS TO THE BANK
+	; BOUNDARY AT $8000 INTO START OF TPA.
+	LD	A,BID_RAM0
+	LD	(HB_SRCBNK),A
+	LD	A,BID_USR
+	LD	(HB_DSTBNK),A
+	LD	HL,HB_END
+	LD	DE,0
+	LD	BC,$8000-HB_END
+;
+    #IF (MEMMGR == MM_Z280)
+	CALL	Z280_BNKCPY
+    #ELSE
+	CALL	HBX_BNKCPY
+    #ENDIF
+;
+	; COPY REMAINDER OF PAYLOAD EXTENDING INTO THE SECOND PHYSICAL
+	; RAM BANK.  NOTE THAT THE DESTINATION ADDRESS (DE) IS
+	; ALREADY CORRECT FROM THE PRIOR COPY.
+	LD	A,BID_RAM0+1
+	LD	(HB_SRCBNK),A
+	LD	HL,$0000
+	; DE IS ALREADY CORRECT
+	LD	BC,$8000-($8000-HB_END)
+;
+    #IF (MEMMGR == MM_Z280)
+	CALL	Z280_BNKCPY
+    #ELSE
+	CALL	HBX_BNKCPY
+    #ENDIF
+;
+  #ENDIF
+;
+#ENDIF
 ;
 ; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
 ;
@@ -1875,20 +1946,20 @@ HB_CPUSPD2:
 ;
 	LD	HL,(HB_CPUOSC)	; INIT HL TO CPU OSC FREQ (KHZ)
 ;
-  #IF (Z180_CLKDIV == 0)
 	; ADJUST HL TO REFLECT HALF SPEED OPERATION
 	SRL	H		; ADJUST HL ASSUMING
 	RR	L		; HALF SPEED OPERATION
-  #ENDIF
 ;	
-  #IF (Z180_CLKDIV == 1)
+  #IF (Z180_CLKDIV >= 1)
 	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
 	CP	2		; Z8S180 REV K OR BETTER?
 	JR	C,HB_CPU3	; IF NOT, NOT POSSIBLE!
 	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
 	LD	A,$80
 	OUT0	(Z180_CCR),A
-	; HL ALREADY REFLECTS FULL SPEED OPERATION
+	; ADJUST HL TO REFLECT FULL SPEED OPERATION
+	SLA	L
+	RL	H
   #ENDIF
 ;
   #IF (Z180_CLKDIV >= 2)
@@ -2375,6 +2446,9 @@ HB_Z280BUS1:
 #ENDIF
 #IF (MEMMGR == MM_MBC)
 	.TEXT	"MBC$"
+#ENDIF
+#IF (MEMMGR == MM_RPH)
+	.TEXT	"RPH$"
 #ENDIF
 	CALL	PRTSTRD
 	.TEXT	" MMU$"
@@ -2450,6 +2524,7 @@ HB_Z280BUS1:
 #ENDIF
 ;
 #IFDEF ROMBOOT
+  #IF (ROMSIZE > 0)
 ;
 ; ROM CHECKSUM VERIFICATION
 ; EACH OF THE FIRST 4 ROM BANKS HAS A CHECKSUM INJECTED SUCH THAT
@@ -2520,6 +2595,7 @@ HB_CKBNKSIZ	.EQU	$-HB_CKBNK	; SIZE OF ROUTINE
 ;
 HB_ROMCKZ:
 ;
+  #ENDIF
 #ENDIF
 ;
 ; LOW BATTERY DIAGNOSTIC MESSAGE
@@ -2723,15 +2799,8 @@ INITSYS4:
 	LDCTL	(C),HL
 #ENDIF
 ;
-; CHAIN TO OS LOADER
+#IFNDEF ROMBOOT
 ;
-#IFDEF ROMBOOT
-	; PERFORM BANK CALL TO OS IMAGES BANK IN ROM
-	LD	A,BID_IMG0		; CHAIN TO OS IMAGES BANK
-	LD	IX,0			; ENTER AT ADDRESS 0
-	CALL	HBX_BNKCALL		; GO THERE
-	HALT				; WE SHOULD NEVER COME BACK!
-#ELSE
 	; COPY OS IMAGE: BID_USR:<IMG START> --> BID_USR:0
 	LD	B,BF_SYSSETCPY		; HBIOS FUNC: SETUP BANK COPY
 	LD	D,BID_USR		; D = DEST BANK = USER BANK
@@ -2745,16 +2814,23 @@ INITSYS4:
 	LD	DE,0			; TO USER ADDRESS 0
 	RST	08			; DO IT
 ;
-	; PERFORM BANK CALL TO USER BANK
-	LD	A,BID_USR		; CHAIN TO OS IMAGES BANK
+#ENDIF
+;
+; CHAIN TO LOADER
+;
+#IFDEF ROMBOOT
+  #IF (ROMSIZE > 0)
+	LD	A,BID_IMG0		; CHAIN TO OS IMAGES BANK
+  #ELSE
+	LD	A,BID_USR		; CHAIN TO USER BANK
+  #ENDIF
+#ELSE
+	LD	A,BID_USR		; CHAIN TO USER BANK
+#ENDIF
 	LD	IX,0			; ENTER AT ADDRESS 0
 	CALL	HBX_BNKCALL		; GO THERE
 	HALT				; WE SHOULD NEVER COME BACK!
 ;
-#ENDIF
-;
-	RET
-;
 ;	CALL A LIST OF ROUTINES POINTED TO BY DE OF LENGTH B.
 ;
 CALLLIST:
@@ -2825,6 +2901,12 @@ HB_PCINITTBL:
 #IF (ACIAENABLE)
 	.DW	ACIA_PREINIT
 #ENDIF
+#IF (PIOENABLE)
+	.DW	PIO_PREINIT
+#ENDIF
+#IF CENENABLE)
+	.DW	CEN_PREINIT
+#ENDIF
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_PREINIT
 #ENDIF
@@ -2905,8 +2987,8 @@ HB_INITTBL:
 #IF (VGAENABLE)
 	.DW	VGA_INIT
 #ENDIF
-#IF (NECENABLE)
-	.DW	NEC_INIT
+#IF (GDCENABLE)
+	.DW	GDC_INIT
 #ENDIF
 #IF (TMSENABLE)
 	.DW	TMS_INIT
@@ -2944,6 +3026,12 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
+#IF (PIOENABLE)
+	.DW	PIO_INIT
+#ENDIF
+#IF (CENENABLE)
+	.DW	CEN_INIT
+#ENDIF
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_INIT
 #ENDIF
@@ -3675,6 +3763,11 @@ SYS_RESINT:
 ; GO BACK TO ROM BOOT LOADER
 ;
 SYS_RESWARM:
+;
+#IF (ROMSIZE == 0)
+	JR	SYS_RESCOLD
+#ENDIF
+;
 	CALL	SYS_RESINT
 ;
 #IF (MEMMGR == MM_Z280)
@@ -3691,6 +3784,14 @@ SYS_RESWARM:
 ; RESTART SYSTEM AS THOUGH POWER HAD JUST BEEN TURNED ON
 ;
 SYS_RESCOLD:
+;
+#IF (ROMSIZE == 0)
+	LD	DE,STR_RESTART
+	CALL	Z,WRITESTR
+	DI
+	HALT
+#ENDIF
+;
 #IF (MEMMGR == MM_Z280)
 	JP	Z280_RESTART
 #ELSE
@@ -4001,19 +4102,33 @@ SYS_GETCPUSPD1:
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
-	IN0	A,(Z180_CMR)		; GET CLOCK MULTIPLIER
-	RLCA				; ROTATE BIT TO BIT 0
-	AND	%00000001		; ISOLATE IT
-	LD	H,A			; SAVE IN H
+	LD	HL,0			; INIT CPU SPEED TO HALF
+	LD	A,(HB_CPUTYPE)		; LOAD CPUTYPE
+	CP	2			; S-CLASS OR ABOVE?
+	JR	C,SYS_GETCPUSPD1	; IF NOT, NO CCR/CMR
+;
+	; GET CCR BIT
 	IN0	A,(Z180_CCR)		; GET CLOCK CONTROL
 	RLCA				; ROTATE BIT TO BIT 0
 	AND	%00000001		; ISOLATE IT
 	LD	L,A			; SAVE IN L
+;
+	LD	A,(HB_CPUTYPE)		; LOAD CPUTYPE
+	CP	3			; REV. N?
+	JR	C,SYS_GETCPUSPD1	; IF NOT, NO CMR
+;
+	; GET CMR BIT
+	IN0	A,(Z180_CMR)		; GET CLOCK MULTIPLIER
+	RLCA				; ROTATE BIT TO BIT 0
+	AND	%00000001		; ISOLATE IT
+	LD	H,A			; SAVE IN H
+;
+SYS_GETCPUSPD1:
+	; CALC FINAL MULTIPLIER TO L
 	XOR	A			; CLEAR ACCUM
 	ADD	A,H			; ADD IN CMR BIT
 	ADD	A,L			; ADD IN CCR BIT
 	LD	L,A			; SAVE RESULT IN L
-;
 	; DCNTL = MMII????
 	IN0	A,(Z180_DCNTL)		; GET WAIT STATES
 	RLCA				; ROTATE MEM WS BITS
@@ -4277,6 +4392,29 @@ SYS_SETCPUSPD3:
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
+	; VERIFY THAT REQUESTED SETTINGS ARE ALLOWED BY HARDWARE
+	LD	A,L			; GET SPEED REQUESTED
+	CP	$FF			; NO CHANGE?
+	JR	Z,SYS_SETCPUSPD0A	; SKIP CHECK
+	LD	A,(HB_CPUTYPE)		; 1=ORIG, 2=REVK, 3=REVN
+	INC	L			; 1=HALF,2=FULL,3=DOUBLE
+	CP	L			; TOO HIGH FOR CPU TYPE?
+	JP	C,SYS_SETCPUSPD_ERR	; CPU CAN'T DO SPD MULT
+	DEC	L			; RESTORE ORIG REQUEST
+SYS_SETCPUSPD0A:
+	LD	A,D			; MEM WS
+	CP	$FF			; NO CHANGE?
+	JR	Z,SYS_SETCPUSPD0B	; SKIP CHECK
+	CP	4			; TOO HIGH?
+	JP	NC,SYS_SETCPUSPD_ERR	; >3 IS TOO HIGH
+SYS_SETCPUSPD0B:
+	LD	A,D			; I/O WS
+	CP	$FF			; NO CHANGE?
+	JR	Z,SYS_SETCPUSPD0C	; SKIP CHECK
+	CP	4			; TOO HIGH?
+	JP	NC,SYS_SETCPUSPD_ERR	; >3 IS TOO HIGH
+SYS_SETCPUSPD0C:
+;
 	PUSH	DE			; SAVE WAIT STATES FOR NOW
 	; BEFORE IMPLEMENTING THE NEW CPU SPEED, WE SWITCH THE
 	; WAIT STATES TO MAXIMUM BECAUSE WE MAY BE IMPLEMENTING
@@ -4303,11 +4441,11 @@ SYS_SETCPUSPD1:
 	LD	C,%10000000		; SET CCR BIT
 SYS_SETCPUSPD2:
 ;
+	; IMPLEMENT THE NEW CPU SPEED
 	IN0	A,(Z180_CMR)
 	AND	~%10000000
 	OR	B
 	OUT0	(Z180_CMR),A
-;
 	IN0	A,(Z180_CCR)
 	AND	~%10000000
 	OR	C
@@ -5701,12 +5839,12 @@ SIZ_TMS		.EQU	$ - ORG_TMS
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
-#IF (NECENABLE)
-ORG_NEC	.EQU	$
-  ;#INCLUDE "nec.asm"
-SIZ_NEC	.EQU	$ - ORG_NEC
-		.ECHO	"NEC occupies "
-		.ECHO	SIZ_NEC
+#IF (GDCENABLE)
+ORG_GDC	.EQU	$
+  #INCLUDE "gdc.asm"
+SIZ_GDC	.EQU	$ - ORG_GDC
+		.ECHO	"GDC occupies "
+		.ECHO	SIZ_GDC
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
@@ -5770,7 +5908,7 @@ SIZ_FONTS	.EQU	$ - ORG_FONTS
 		.ECHO	SIZ_FONTS
 		.ECHO	" bytes.\n"
 ;
-#IF (CVDUENABLE | VGAENABLE) | (TMSENABLE & (TMSMODE == TMSMODE_RCKBD))
+#IF (CVDUENABLE | VGAENABLE) | GDCENABLE | (TMSENABLE & ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC)))
 ORG_KBD		.EQU	$
   #INCLUDE "kbd.asm"
 SIZ_KBD		.EQU	$ - ORG_KBD
@@ -5897,6 +6035,24 @@ SIZ_SPK	.EQU	$ - ORG_SPK
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (PIOENABLE)
+ORG_PIO		.EQU	$
+  #INCLUDE "pio.asm"
+SIZ_PIO		.EQU	$ - ORG_PIO
+		.ECHO	"PIO occupies "
+		.ECHO	SIZ_PIO
+		.ECHO	" bytes.\n"
+#ENDIF
+;
+#IF (CENENABLE)
+ORG_CEN		.EQU	$
+  #INCLUDE "cen.asm"
+SIZ_CEN		.EQU	$ - ORG_CEN
+		.ECHO	"CEN occupies "
+		.ECHO	SIZ_CEN
+		.ECHO	" bytes.\n"
+#ENDIF
+;
 #IF (PIO_4P | PIO_ZP | PIO_SBC)
 ORG_PIO		.EQU	$
   #INCLUDE "pio.asm"
@@ -5977,7 +6133,7 @@ SIZ_AY38910	.EQU	$ - ORG_AY38910
 ;
 ; INCLUDE LZSA2 decompression engine if required.
 ;
-#IF ((VGAENABLE | CVDUENABLE | TMSENABLE) & USELZSA2)
+#IF ((VGAENABLE | CVDUENABLE | TMSENABLE | GDCENABLE) & USELZSA2)
 #INCLUDE "unlzsa2s.asm"
 #ENDIF
 ;
@@ -6738,7 +6894,7 @@ PS_FLP_DSTR:	.TEXT	"SD$"		; PS_FLPSD
 ;
 PS_SDSTRREF:
 	.DW	PS_SDUART, PS_SDASCI, PS_SDTERM, PS_SDPRPCON, PS_SDPPPCON
-	.DW	PS_SDSIO, PS_SDACIA, PS_SDPIO, PS_SDUF, PS_SDDUART, PS_SDZ2U
+	.DW	PS_SDSIO, PS_SDACIA, PS_SDPIO, PS_SDUF, PS_SDDUART, PS_SDZ2U, PS_SDCEN
 ;
 PS_SDUART	.TEXT	"UART$"
 PS_SDASCI	.TEXT	"ASCI$"
@@ -6747,10 +6903,11 @@ PS_SDPRPCON	.TEXT	"PRPCON$"
 PS_SDPPPCON	.TEXT	"PPPCON$"
 PS_SDSIO	.TEXT	"SIO$"
 PS_SDACIA	.TEXT	"ACIA$"
-PS_SDPIO	.TEXT	"PORT$"
+PS_SDPIO	.TEXT	"PIO$"
 PS_SDUF		.TEXT	"UF$"
 PS_SDDUART	.TEXT	"DUART$"
 PS_SDZ2U	.TEXT	"Z2U$"
+PS_SDCEN	.TEXT	"CEN$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;
@@ -6770,11 +6927,11 @@ PIO_MODE_STR:	.TEXT	"Output$"
 ; VIDEO DEVICE STRINGS
 ;
 PS_VDSTRREF:
-	.DW	PS_VDVDU, PS_VDCVDU, PS_VDNEC, PS_VDTMS, PS_VDVGA
+	.DW	PS_VDVDU, PS_VDCVDU, PS_VDGDC, PS_VDTMS, PS_VDVGA
 ;
 PS_VDVDU	.TEXT	"VDU$"
 PS_VDCVDU	.TEXT	"CVDU$"
-PS_VDNEC	.TEXT	"NEC$"
+PS_VDGDC	.TEXT	"GDC$"
 PS_VDTMS	.TEXT	"TMS$"
 PS_VDVGA	.TEXT	"VGA$"
 ;
@@ -6984,6 +7141,7 @@ STR_LOWBAT	.DB	"\r\n\r\n+++ LOW BATTERY +++$"
 STR_PANIC	.TEXT	"\r\n>>> PANIC: $"
 STR_SYSCHK	.TEXT	"\r\n>>> SYSCHK: $"
 STR_CONTINUE	.TEXT	"\r\nContinue (Y/N)? $"
+STR_RESTART	.TEXT	"\r\n\r\n>>> Press hardware reset button to restart system\r\n\r\n$"
 ;
 #IF (DSKYENABLE)	;	'H','B','I','O',' ',' ',' ',' '
   #IF (DSKYMODE == DSKYMODE_V1)
@@ -7010,7 +7168,9 @@ SLACK		.EQU	BNKTOP - $
 		.ECHO	" bytes.\n"
 ;
 #IFDEF ROMBOOT
+  #IF (ROMSIZE > 0)
 		.FILL	SLACK
+  #ENDIF
 #ENDIF
 ;
 		.END

Source/HBIOS/hbios.inc

@@ -136,6 +136,7 @@ PLT_SCZ180	.EQU	10		; SCZ180
 PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
 PLT_RCZ280	.EQU	12		; RC2014 W/ Z280
 PLT_MBC		.EQU	13		; MULTI BOARD COMPUTER
+PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -182,6 +183,7 @@ CIODEV_PIO	.EQU	$70
 CIODEV_UF	.EQU	$80
 CIODEV_DUART	.EQU	$90
 CIODEV_Z2U	.EQU	$A0
+CIODEV_CEN	.EQU	$B0
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
@@ -216,7 +218,7 @@ RTCDEV_RP5	.EQU	$50		; RP5C01
 ;
 VDADEV_VDU	.EQU	$00		; ECB VDU - MOTOROLA 6545
 VDADEV_CVDU	.EQU	$10		; ECB COLOR VDU - MOS 8563
-VDADEV_NEC	.EQU	$20		; ECB UPD7220 - NEC UPD7220
+VDADEV_GDC	.EQU	$20		; GRAPHICS DISPLAY CTLR - UPD7220
 VDADEV_TMS	.EQU	$30		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
 VDADEV_VGA	.EQU	$40		; ECB VGA3 - HITACHI HD6445
 ;VDADEV_V9958	.EQU	$50		; V9958 VDU

Source/HBIOS/pio_ps.asm

@@ -0,0 +1,999 @@
+; PIO driver sets up the parallel port as a subtype of Serial/Char device.
+;
+;
+; HBIOS initializes driver by:
+;
+; 1) Calling Pre-initialization
+;
+;    This involves setting up all the data structures describing the devices.
+;    If possible, do a hardware test to verify it is available for adding to available devices.
+;
+; 2) Calling device initialization.
+;
+;    Hardware initialization.
+;    Configure to initial state or to a new state.
+;
+; Implementation limitations:
+;
+; The fully functionality of the Z80 PIO can only be realized by using Z80 interrupt mode 2.
+; Registers cannot be interrogated for interrupts status and the originating interrupt
+; device cannot be determine.
+;
+; Full implementation of IM2 functionality for an ECB-ZP and ECB-4P board would require the 
+; allocation of an interrupt handler for each chip channel. Thus, 12 interrupt handlers
+; would be required to support this configuration. As the HBIOS only has an allocation of
+; 16, a full implmentation is impractical.
+;
+; The compromise solution is to allow 4 interrupts for the PIO driver. All remaining PIO's
+; are limited to Bit mode or blind read and write to the input/output ports.
+;
+; Zilog PIO reset state:
+;
+;	Both port mask registers are reset to inhibit All port data bits.
+;	Port data bus lines are set to a high-impedance state and the Ready "handshake"
+;	Mode 1 (output) is automatically selected.
+;	The vector address registers are not reset.
+;	Both port interrupt enable flip-flops are reset.
+;	Both port output registers are reset.
+;
+; Register addressing example for ECB-ZP and ECB-4P assuming base address 90h and 88h respectively.
+;
+; PIO ----ZP---- ----4P----
+;  0  DATA 0 90h DATA 0 B8h
+;  0  DATA 1 91h DATA 1 B9h
+;  0  CMD  0 92h CMD  0 BAh
+;  0  CMD  1 93h CMD  1 BBh
+;  1  DATA 0 94h DATA 0 BCh
+;  1  DATA 1 95h DATA 1 BDh
+;  1  CMD  0 96h CMD  0 BEh
+;  1  CMD  1 97h CMD  1 BFh
+;  2             DATA 0 C0h
+;  2             DATA 1 C1h
+;  2             CMD  0 C2h
+;  2             CMD  1 C3h
+;  3             DATA 0 C4h
+;  3             DATA 1 C5h
+;  3             CMD  0 C6h
+;  3             CMD  1 C7h
+;
+PIODEBUG	.EQU	1
+;
+M_Output	.EQU	$00 << 6
+M_Input		.EQU	$01 << 6
+M_Bidir		.EQU	$02 << 6
+M_BitCtrl	.EQU	$03 << 6
+M_BitAllIn	.EQU	$FF
+M_BitAllOut	.EQU	$00
+;
+PIO_NONE	.EQU	0
+PIO_ZPIO	.EQU	1
+PIO_8255	.EQU	2
+PIO_PORT	.EQU	3
+
+; SET MAXIMUM NUMBER OF INTERRUPTS AVAILABLE FOR ALL
+; ENSURE INTERRUPTS ARE NOT TURNED ON IF IM2 IS NOT SET.
+
+INT_ALLOC	.DB	0
+INT_N		.EQU	00000000B
+#IF	(INTMODE == 2)
+INT_Y		.EQU	00000100B
+INT_ALLOW	.EQU	4
+#ELSE
+INT_Y		.EQU	INT_N
+INT_ALLOW	.EQU	0
+#ENDIF
+;
+INT0		.EQU	00000000B
+INT1		.EQU	00000001B
+INT2		.EQU	00000010B
+INT3		.EQU	00000011B
+
+;
+; SETUP THE DISPATCH TABLE ENTRIES
+;
+; PIO_CNT HOLDS THE NUMBER OF DEVICED CALCULATED FROM THE NUMBER OF DEFPIO MACROS
+; PIO_CNT SHOULD INCREASE BY 2 FOR EVERY PIO CHIP ADDED.
+;
+; PIO_PREINIT WILL READ THROUGH ALL PIOCFG TABLES AND CONFIGURE EACH TABLE.
+; IT WITH THEN CALL PIO_INITUNIT TO INITIALIZE EACH DEVICE TO ITS DEFAULT STATE
+; 
+; EXPECTS NOTHING ON ENTRY
+;
+PIO_PREINIT:
+	CALL	NEWLINE		;D
+	LD	B,PIO_CNT		; LOOP CONTROL
+	LD	C,0			; PHYSICAL UNIT INDEX
+	XOR	A			; ZERO TO ACCUM
+;	LD	(PIO_DEV),A		; CURRENT DEVICE NUMBER
+	LD	(INT_ALLOC),A		; START WITH NO INTERRUPTS ALLOCATED
+PIO_PREINIT0:	
+	PUSH	BC			; SAVE LOOP CONTROL
+;	LD	A,C			; INITIALIZE THE UNIT
+
+;	PUSH	AF		;D
+;	LD	A,'u'		;D
+;	CALL	COUT		;D
+;	POP	AF		;D
+;	CALL	PRTHEXBYTE	;D	UNIT
+;	CALL	PC_SPACE	;D
+
+;	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+;	RLCA				; ...
+;	RLCA				; ... TO GET OFFSET INTO CFG TABLE
+;	RLCA
+;;	RLCA
+;	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+;	PUSH	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	POP	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	PUSH	HL			; SAVE IT
+;	POP	IY			; ... TO IY
+
+	CALL	IDXCFG			
+
+	LD	(HL),C
+
+	PUSH	AF		;D
+	LD	A,'c'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	PUSH	BC		;D
+	PUSH	HL		;D
+	POP	BC		;D
+	CALL	PRTHEXWORD	;D	CONFIG TABLE
+	CALL	PC_SPACE	;D
+	POP	BC		;D
+
+	LD	A,(IY+1)		; GET THE PIO TYPE DETECTED
+	CP	PIO_PORT		; SET FLAGS
+
+	PUSH	AF		;D
+	LD	A,'t'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	CALL	PRTHEXBYTE	;D	TYPE
+	CALL	PC_SPACE	;D
+
+;	JR	Z,BADINIT
+
+;	PUSH	BC			; SAVE LOOP CONTROL
+;	LD	BC,PIO_FNTBL		; BC := FUNCTION TABLE ADDRESS	
+;	DEC	A
+;	JR	Z,TYPFND		; SKIP IT IF NOTHING FOUND
+;	LD	BC,PPI_FNTBL		; BC := FUNCTION TABLE ADDRESS
+;	DEC	A
+;	JR	Z,TYPFND		; ADD ENTRY IF PIO FOUND, BC:DE
+;	LD	BC,PRT_FNTBL
+;	DEC	A
+;	JR	Z,TYPFND
+;	POP	BC
+;	JR	BADINIT
+
+	PUSH	HL
+	LD	DE,-1			; INITIALIZE THIS DEVICE WITH
+	CALL	PIO_INITDEV		; DEFAULT VALUES
+	POP	HL
+
+;	JR	NZ,SKPINIT
+
+	; AT THIS POINT WE KNOW WE
+	; HAVE A VALID DEVICE SO ADD IT
+	
+	LD	A,8			; CALCULATE THE FUNCTION TABLE 
+	CALL	ADDHLA			; POSITION WHICH FOLLOWS THE
+	PUSH	HL			; CONFIGURATION TABLE OF EACH
+	POP	BC			; DEVICE
+
+TYPFND:	PUSH	AF		;D
+	LD	A,'f'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	PUSH	BC		;D
+	CALL	PRTHEXWORD	;D	FUNCTION TABLE
+	POP	BC		;D
+	CALL	NEWLINE		;D
+
+	PUSH	IY			; ADD ENTRY IF PIO FOUND, BC:DE
+	POP	DE			; BC: DRIVER FUNCTION TABLE
+	CALL	CIO_ADDENT		; DE: ADDRESS OF UNIT INSTANCE DATA
+
+BADINIT:POP	BC			; RESTORE LOOP CONTROL
+
+	INC	C			; NEXT PHYSICAL UNIT
+SKPINIT:DJNZ	PIO_PREINIT0		; LOOP UNTIL DONE
+
+	PUSH	AF		;D
+	PRTS("INTS=$")		;D
+	LD	A,(INT_ALLOC)	;D
+	CALL	PRTHEXBYTE	;D
+	POP	AF		;D
+	PUSH	DE		;D
+	LD	DE,CIO_TBL-3	;D
+	CALL	DUMP_BUFFER	;D
+	POP	DE		;D
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; INDEX INTO THE CONFIG TABLE
+; ON ENTRY C = UNIT NUMBER
+; ON EXIT IY = CONFIG DATA POINTER
+; ON EXIT DE = CONFIG TABLE START
+;
+; EACH CONFIG TABLE IS 24 BYTES LONG
+;
+CFG_SIZ		.EQU	24
+;
+IDXCFG:	LD	A,C
+	RLCA				; X 2
+	RLCA				; X 4
+	RLCA				; X 8
+	LD	H,0
+	LD	L,A			; HL = X 8
+	PUSH	HL
+	ADD	HL,HL			; HL = X 16
+	POP	DE
+	ADD	HL,DE			; HL = X 24
+	LD	DE,PIO_CFG
+	ADD	HL,DE
+	PUSH	HL			; COPY CFG DATA PTR
+	POP	IY			; ... TO IY
+	RET
+	
+; PIO_INITDEV - INITIALIZE DEVICE
+;
+; IF DE = FFFF THEN THE SETUP PARAMETER WORD WILL BE READ FROM THE DEVICE CONFIGURATION  
+; TABLE POINTED TO BY IY AND THE PIO PORT WILL BE PROGRAMMED BASED ON THAT CONFIGURATION. 
+;
+; OTHERWISE THE PIO PORT WILL BE PROGRAMMED BY THE SETUP PARAMETER WORD IN DE AND THIS 
+; WILL BE SAVED IN THE DEVICE CONFIGURATION TABLE POINTED TO BY IY.
+;
+; ALL OTHER CONFIGURATION OF THE DEVICE CONFIGURATION TABLE IS DONE UPSTEAM BY PIO_PREINIT 
+
+PIO_INITDEV:
+	; TEST FOR -1 (FFFF) WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
+	LD	A,D			; TEST DE FOR
+	AND	E			; ... VALUE OF -1
+	INC	A			; ... SO Z SET IF -1
+	JR	NZ,PIO_INITDEV1		; IF DE == -1, REINIT CURRENT CONFIG
+PIO_INITDEV0:
+	; LOAD EXISTING CONFIG (DCW) TO REINIT
+	LD	E,(IY+4)		; LOW BYTE
+	LD	D,(IY+5)		; HIGH BYTE	
+;
+PIO_INITDEV1:				; WHICH DEVICE TYPE?
+	LD	A,(IY+1)
+	CP	PIO_ZPIO		
+	JR	Z,SETPIO0
+	CP	PIO_8255
+	JP	Z,SET_8255
+	CP	PIO_PORT
+	JP	Z,SET_PORT
+BAD_SET:OR	$FF			; UNKNOWN DEVICE
+	RET
+
+SETPIO0:LD	A,E			; GET MODE 
+	AND	11000000B		; BITS (B7B6)
+	CP	10000000B		; IS IT BIDIR?
+	JR	NZ,SETPIO1
+	LD	A,(IY+2)		; GET CHANNEL
+	OR	A
+	JR	NZ,BAD_SET		; CAN'T DO ON CH1
+
+	; VALIDATE INTERRUPT REQUEST
+	; GRANT INTERRUPT IF THERE IS A FREE INTERRUPT
+	; GRANT INTERRUPT IF AN INTERRUPT IS ALREADY ALLOCATED TO THIS UNIT
+
+SETPIO1:PUSH	AF		;D
+	LD	A,'['		;D
+	CALL	COUT		;D
+	LD	A,(IY)		;D
+	CALL	PRTHEXBYTE	;D
+	LD	A,']'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+
+	BIT	2,E			; SKIP IF WE ARE NOT REQUESTING 
+	JP	Z,SETPIO2		; AN INTERRUPT
+
+	PRTS("[INTREQ]$")	;D
+
+;	LD	A,(IY+4)		; GET CURRENT INTERRUPT SETTING
+;	BIT	2,A			; SKIP IF IT IS ALREADY
+;	JP	NZ,SETPIO2		; ALLOCATED TO THIS UNIT
+
+	LD	A,(INT_ALLOC)		; WE NEED TO ALLOCATE AN
+	CP	INT_ALLOW		; INTERRUPT. DO WE HAVE 
+	JR	NC,BAD_SET		; ONE FREE?
+
+	PRTS("[ALLOCINT]$")	;D
+
+	; WHICH INTERRUPT IS FREE ?
+	; SCAN THROUGH THE CFG TABLES
+	; AND FIND A FREE ONE
+
+	PUSH	AF			; NESTED LOOP
+	LD	DE,CFG_SIZ		; OUTSIDE LOOP IS INTERRUPT
+	LD	B,INT_ALLOW		; INSIDE LOOP IS DEVICE
+SETPIOP: LD	C,B 
+	 DEC	C
+	 PUSH	BC
+	 LD	B,PIO_CNT
+	 LD	HL,PIO_CFG+4
+SETPIOX: LD	A,(HL)
+	 BIT	2,A			; JUMP TO NEXT DEVICE
+	 JR	Z,SETPIOY		; IF NO INTERRUPT ON 
+	 AND	00000011B		; THIS DEVICE
+
+	 CP	C			; IF WE MATCH AN INTERRUPT HERE THEN IT IS NOT FREE.
+	 JR	NZ,SETPIOY		; SO EXIT INSIDE LOOP AND TRY NEXT INTERRUPT
+
+	 XOR	A			; WE MATCH INT 0 - IF WE ARE CHECKING FOR IT THEN
+	 OR	C			; WE REGARD IS AS FREE.
+	 JR	NZ,SETPIOZ
+
+SETPIOY: ADD	HL,DE			
+	 DJNZ	SETPIOX
+
+	 JR	SETPIOQ			; WE GET HERE IF THE CURRENT INTERRUPT
+					; WAS NOT MATCHED SO IT IS FREE
+SETPIOZ: POP	BC
+	DJNZ	SETPIOP
+	POP	AF
+
+	PRTS("[NONEFREE]$")
+	RET
+
+SETPIOQ:PUSH	AF			; AVAILABLE INTERRUPT IS IN C
+	PRTS("[FREE]=$")
+	LD	A,C
+	CALL	PRTHEXBYTE
+	POP	AF
+
+	POP	AF			
+	POP	AF
+
+SETPIOR:LD	HL,INT_ALLOC		; INCREASE THE COUNT
+	INC	(HL)			; OF USED INTERRUPTS
+	LD	A,(HL)
+
+;	LD	A,(IY)			; IS THIS UNIT 
+;	INC	A			; UNITIALIZED?
+;	JR	Z,SETPIO6
+
+	LD	A,(IY+4)		; IT IS UNITIALIZED SO
+	OR	C			; SAVE THE ALLOCATES 
+	LD	(IY+4),A		; INTERRUPT
+;
+; FOR THIS DEVICE AND INTERRUPT, UPDATE THE CONFIG TABLE FOR THIS DEVICE.
+; PIO_IN, PIO_OUT, PIO_IST, PIO_OST ENTRIES NEED TO BE REDIRECTED.
+; INTERRUPT VECTOR NEEDS TO BE UPDATED
+;
+	LD	A,(IY+0)
+	LD	HL,0
+	; SETUP PIO INTERRUPT VECTOR IN IVT
+	LD	HL,HBX_IV09+1
+
+;	CALL	SPK_BEEP
+;
+SETPIO6:RET	
+
+	; EXIT WITH FREE INTERRUPT IN C
+
+	LD	A,C
+	LD	(INT_ALLOC),A
+
+	LD	A,E
+	AND	11000000B
+	OR	00000100B
+	OR	C
+	LD	E,A
+	LD	(IY+5),A
+;
+	; TODO: DEALLOCATE AN INTERRUPT
+;
+;	LD	A,(INT_ALLOC)
+;	DEC	A
+;	LD	(INT_ALLOC),A
+;
+SETPIO2:
+
+;	DE CONTAINS THE MODE IF INTERRUPT ROUTINE SKIPPED
+
+	PRTS("[NOINTREQ]$")	;D
+
+;	LD	A,(IY+4)
+	LD	A,E			; GET MODE AND CREATE COMMAND
+	AND	11000000B		; $B0
+	OR	00001111B		; $0F	
+
+	LD	C,(IY+3)		; GET DATA PORT
+	INC	C			; POINT TO CMD
+	INC	C			; PORT	
+	OUT	(C),A			; SET MODE
+	CP	(M_BitCtrl | $0F)	; IF MODE 3
+	JR	NZ,SETPIO3		
+	LD	A,(IY+5)		; SET I/O DIRECTION
+	OUT	(C),A			; FOR MODE 3
+
+SETPIO3:; INTERUPT HANDLING
+
+	JP	SETPIO4
+
+	; SETUP THE INTERRUPT VECTOR
+
+	LD	A,E
+	AND	00000011B
+;	DEC	A			; INDEX INTO THE
+	ADD	A,A			; THE VECTOR TABLE
+	ADD	A,A			; 
+	LD	C,A
+	LD	B,0
+	LD	HL,HBX_IV09+1
+	ADD	HL,BC			; GET THE ADDRESS OF
+	PUSH	DE
+	LD	D,(HL)			; THAT INTERRUPT
+	INC	HL			; HANDLER
+	LD	E,(HL)
+	LD	HL,0	;HBX_IVT+IVT_PIO0	; POPULATE THE
+	LD	A,L			; GET LOW BYTE OF IVT ADDRESS
+	ADD	HL,BC			; INTERRUPT TABLE
+	LD	(HL),D			; WITH THE INTERRUPT
+	INC	HL			; HANDLER ADDRESS FOR
+	LD	(HL),E			; THIS UNIT
+	POP	DE
+	LD	HL,INT_ALLOC
+	LD	C,(HL)
+	LD	B,0
+	LD	HL,PRTTAB-1		; SAVE THE DATA	
+	ADD	HL,BC			; PORT FOR EACH INTERRUPT
+	LD	C,(IY+3)		
+	LD	(HL),C
+
+	INC	C			; POINT TO CMD PORT
+	INC	C
+	DI				; SET THE VECTOR ADDRESS
+	OUT	(C),A
+
+;	LD	A,10000011B		; ENABLE INTERRUPTS ON
+	OUT	(C),A			; THIS UNIT
+	EI	
+;	JR	GUD_SET
+;
+SETPIO4:LD	A,00000111B		; $07 
+	OUT	(C),A			; NO INTERRUPTS
+;
+;	SUCCESSFULL SO SAVE DEVICE CONFIGURATION WORD (DCW)
+;
+GUD_SET:LD	(IY+4),E		; LOW BYTE
+	LD	(IY+5),D		; HIGH BYTE	
+;
+;	UPDATE THE DEVICE TABLE WITH THE ADDRESSES FOR THE CORRECT ROUTINE.
+;
+	LD	A,E
+	AND	00000111B
+	LD	HL,INTMATRIX		; POINT TO EITHER THE INTERRUPT
+	JR	NZ, USEIM
+	LD	HL,POLMATRIX		; MATRIX OR THE POLLED MATRIX
+USEIM:	PUSH	HL	
+
+	PUSH	IY			; CALCULATE THE DESTINATION
+	POP	HL			; ADDRESS IN THE PIO_CFG TABLE
+	LD	BC,8			; FOR THE FOUR ADDESSES TO BE 
+	ADD	HL,BC			; COPIED TO 
+
+;	LD	B,0			; 00000000 CALCULATE THE SOURCE ADDRESS
+	LD	C,E			; XX?????? FROM THE MATRIX. EACH ENTRY 
+	SRL	C			; 0XX????? IN THE MATRIX IS 8 BYTES SO
+	SRL	C			; 00XX???? SOURCE = MATRIX BASE + (8 * MODE)
+	SRL	C			; 000XX???
+	POP	DE			; LOAD THE MATRIX BASE
+;	LD	DE,POLMATRIX
+	EX	DE,HL
+	ADD	HL,BC			; HL = SOURCE
+
+	LD	C,8			; COPY 8 BYTES
+	LDIR
+
+;	PUSH	IY
+;	POP	DE
+;	CALL	DUMP_BUFFER
+
+	XOR	A
+	RET
+
+PRTTAB:	.DB	0
+	.DB	0
+	.DB	0
+	.DB	0
+;
+;-----------------------------------------------------------------------------
+;
+; INPUT INTERRUPT VECTOR MACRO AND DEFINITION FOR FOUR PORTS
+;
+#DEFINE	PIOMIVT(PIOIN,PIOIST,PIOPRT) 		\
+#DEFCONT ;\
+#DEFCONT ;	RETURN WITH ERROR IF THERE IS	\
+#DEFCONT ;	ALREADY	A CHARACTER IN BUFFER	\
+#DEFCONT ;\
+#DEFCONT ;	OTHERWISE CHANGE THE STATUS TO	\
+#DEFCONT ;	SHOW THERE IS ONE CHARACTER IN	\
+#DEFCONT ;	THE BUFFER AND READ IT IN AND	\
+#DEFCONT ;	AND STORE IT.RETURN GOOD STATUS.\
+#DEFCONT ;\
+#DEFCONT \	LD	A,(_CIST)
+#DEFCONT \	OR	A
+#DEFCONT \	JR	NZ,_OVFL
+#DEFCONT \	LD	A,(PIOPRT)
+#DEFCONT \	LD	C,A
+#DEFCONT \	LD	A,1
+#DEFCONT \	LD	(_CIST),A
+#DEFCONT \	IN	A,(C)
+#DEFCONT \	LD	(_CICH),A
+#DEFCONT \	OR	$FF
+#DEFCONT \	RET
+#DEFCONT \_OVFL:XOR	A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT \PIOIN:CALL	PIOIST
+#DEFCONT \	JR	Z,PIOIN
+#DEFCONT \	LD	A,(_CICH)
+#DEFCONT \	LD	E,A
+#DEFCONT \	XOR	A
+#DEFCONT \	LD	(_CIST),A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	If THERE A CHARACTER		\
+#DEFCONT ;	AVAILABLE? RETURN NUMBER	\
+#DEFCONT ;	IN A - 0 OR 1			\
+#DEFCONT ;\
+#DEFCONT \PIOIST:LD	A,(_CIST)
+#DEFCONT \	AND	00000001B
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	CIST :	01 = CHARACTER READY ELSE NOT READY	\
+#DEFCONT ;	CISH :	CHARACTER STORED BY INTERRUPT		\
+#DEFCONT ;\
+#DEFCONT \_CIST	.DB	00
+#DEFCONT \_CICH	.DB	00
+;
+PIOIVT0:.MODULE	PIOIVT0
+PIOMIVT(PIO0IN,PI0_IST,PRTTAB+0)
+PIOIVT1:.MODULE PIOIVT1
+PIOMIVT(PIO1IN,PI1_IST,PRTTAB+1)
+PIOIVT2:.MODULE PIOIVT2
+PIOMIVT(PIO2IN,PI2_IST,PRTTAB+2)
+PIOIVT3:.MODULE PIOIVT3
+PIOMIVT(PIO3IN,PI3_IST,PRTTAB+3)
+;
+;-----------------------------------------------------------------------------
+;
+; OUTPUT INTERRUPT VECTOR MACRO AND DEFINITION FOR FOUR PORTS
+;
+; AN INTERRUPT IS GENERATED WHEN THE RECEIVING DEVICE CAN ACCEPT A CHARACTER
+;
+#DEFINE	PIOMOVT(PIOOUT,PIOOST,PIOPRT) 		\
+#DEFCONT ;\
+#DEFCONT ;	RETURN IF WE ARE WAITING FOR A	\
+#DEFCONT ;	CHARACTER (COST = 00)		\
+#DEFCONT ;\
+#DEFCONT ;	IF ZERO CHARACTERS READY 
+#DEFCONT ;	(COST = 01) CHANGE STATUS TO	\
+#DEFCONT ;	WAITING FOR CHARACTER (COST 00)	\
+#DEFCONT ;\
+#DEFCONT ;	IF A CHARACTER IS READY THEN	\
+#DEFCONT ;	OUTPUT AND CHANGE STATUS TO	\
+#DEFCONT ;	ZERO CHARACTERS READY		\
+#DEFCONT ;\
+#DEFCONT \	LD	A,(_COST)
+#DEFCONT \ 	DEC	A
+#DEFCONT \	RET	M
+#DEFCONT \	JR	Z,_WFC
+#DEFCONT \	LD	A,(_COCH)
+#DEFCONT \	LD	E,A
+#DEFCONT \_ONOW:LD	A,(PIOPRT)
+#DEFCONT \	LD	C,A
+#DEFCONT \	OUT	(C),E
+#DEFCONT \ 	LD	A,1
+#DEFCONT \_WFC:	LD	(_COST),A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	WAIT FOR SPACE FOR THE CHARACTER\
+#DEFCONT ;	IF WE ARE WAITING FOR A		\
+#DEFCONT ;	CHARACTRE THEN OUTPUT IT NOW	\
+#DEFCONT ;	OTHERWISE STORE IT UNTIL THE	\
+#DEFCONT ;	INTERRUPT CALLS FOR IT		\
+#DEFCONT ;\
+#DEFCONT \PIOOUT:LD	A,(_COST)
+#DEFCONT \	CP	2
+#DEFCONT \	JR	C,_ONOW
+#DEFCONT \	LD	A,E
+#DEFCONT \	LD	(_COCH),A
+#DEFCONT \	LD	A,2
+#DEFCONT \	LD	(_COST),A
+#DEFCONT \	JR	PIOOUT
+#DEFCONT ;\
+#DEFCONT ;	RETURN WITH NUMBER OF		\
+#DEFCONT ;	CHARACTERS AVAILABLE 0 or 1	\
+#DEFCONT ;\
+#DEFCONT \PIOOST:LD	A,(_COST)
+#DEFCONT \	DEC	A
+#DEFCONT \	DEC	A
+#DEFCONT \	RET	Z
+#DEFCONT \	LD	A,1
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	COST :	00 WAITING FOR CHARACTER\
+#DEFCONT ;		01 ZERO CHARACTERS READY\
+#DEFCONT ;		02 ONE CHARACTER READY	\
+#DEFCONT ;	COCH :	CHARACTER TO OUTPUT	\
+#DEFCONT ;\
+#DEFCONT \_COST	.DB	01
+#DEFCONT \_COCH	.DB	00
+;
+PIOOVT0:.MODULE	PIOOVT0
+PIOMOVT(PIO0OUT,PI0_OST,PRTTAB+0)
+PIOOVT1:.MODULE PIOOVT1
+PIOMOVT(PIO1OUT,PI1_OST,PRTTAB+1)
+PIOOVT2:.MODULE PIOOVT2
+PIOMOVT(PIO2OUT,PI2_OST,PRTTAB+2)
+PIOOVT3:.MODULE PIOOVT3
+PIOMOVT(PIO3OUT,PI3_OST,PRTTAB+3)
+;
+;-----------------------------------------------------------------------------
+;
+; NON INTERRUPT OUTPUT ROUTINE - SHARED
+;
+; INPUT WILL ALWAYS RETURN ERROR, CHARACTER RETURNED IS UNDEFINED.
+; OUTPUT WILL ALWAYS RETURN SUCCESS
+; INPUT-STATUS WILL ALWAYS RETURN 0 CHARACTERS IN BUFFER.
+; OUTPUT-STATUS WILL ALWAYS RETURN 1 CHARACTER SPACE IN BUFFER.
+
+PIOSHO_IN:
+	LD	A,1
+	RET
+;
+PIOSHO_OUT:	
+	LD	C,(IY+3)
+	OUT	(C),E
+	XOR	A
+	RET
+;
+PIOSHO_IST:	XOR	A
+	RET
+;
+PIOSH_OST:	
+	LD	A,1
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; NON INTERRUPT INPUT ROUTINE - SHARED
+;
+; INPUT WILL ALWAYS A CHARACTER AND SUCCESS.
+; OUTPUT WILL ALWAYS RETURN FAILURE
+; INPUT STATUS WILL ALWAYS RETURN 1 CHARACTER IN BUFFER.
+;OUTPUT-STATUS WILL ALWAYS RETURN 0 CHARACTER SPACE IN BUFFER.
+;
+PIOSHI_IN:
+	LD	C,(IY+3)
+	IN	A,(C)
+	LD	E,A
+	XOR	A
+	RET
+;
+PIOSHI_OUT:
+	LD	A,1
+	RET
+;
+PIOSH_IST:
+	LD	A,1
+	RET
+;
+PIOSHI_OST:
+	XOR	A
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; ON ENTRY IY POINTS TO THE DEVICE RECORD. GET AND RETURN THE CONFIGURATION WORD IN DE
+;
+PIO_QUERY:
+PPI_QUERY:
+	LD	E,(IY+4)		; FIRST CONFIG BYTE TO E
+	LD	D,(IY+5)		; SECOND CONFIG BYTE TO D
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; ON ENTRY IY POINTS TO THE DEVICE RECORD. FOR CHARACTER DEVICES BIT 6 OF ATTRIBUTE
+; INDICATES PARALLEL PORT IF 1 SO WE SET IT. COMMON TO ALL PORTS
+;
+PIO_DEVICE:
+PPI_DEVICE:
+	LD	D,CIODEV_PIO		; D := DEVICE TYPE
+	LD	E,(IY)			; E := PHYSICAL UNIT
+	LD	C,$40			; C := ATTRIBUTE
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,(IY+3)		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+INTMATRIX:
+	.DW	PIO0IN,	PIO0OUT, PI0_IST, PI0_OST
+	.DW	PIO1IN,	PIO1OUT, PI1_IST, PI1_OST
+	.DW	PIO2IN,	PIO2OUT, PI2_IST, PI2_OST
+	.DW	PIO3IN,	PIO3OUT, PI3_IST, PI3_OST
+POLMATRIX:
+	.DW	PIOSHO_IN, PIOSHO_OUT, PIOSHO_IST, PIOSH_OST	; OUTPUT
+	.DW	PIOSHI_IN, PIOSHI_OUT, PIOSH_IST,  PIOSHI_OST	; INPUT
+	.DW	0,0,0,0						; BIDIR	
+	.DW	0,0,0,0						; BIT MODE
+
+SET_8255:
+	RET	
+;
+SET_BYE:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; ------------------------------------
+; i8255 FUNCTION TABLE ROUTINES
+;-------------------------------------
+	
+PPI_IN:
+	XOR	A			; SIGNAL SUCCESS
+	RET	
+;
+PPI_OUT:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;	
+PPI_IST:
+	RET	
+;	
+PPI_OST:
+	RET
+;
+; PIO_INITDEV - Configure device.
+; If DE = FFFF then extract the configuration information from the table of devices and program the device using those settings.
+; Otherwise use the configuration information in DE to program those settings and save them in the device table
+
+PPI_INITDEV:
+	XOR	A			; SIGNAL SUCCESS
+	RET	
+PPI_INT:OR	$FF			; NZ SET TO INDICATE INT HANDLED
+	RET
+;	
+PIO_PRTCFG:
+	; ANNOUNCE PORT
+	CALL	NEWLINE			; FORMATTING
+	PRTS("PIO$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": IO=0x$")		; FORMATTING
+	LD	A,(IY+3)		; GET BASE PORT
+	CALL	PRTHEXBYTE		; PRINT BASE PORT
+;
+	; PRINT THE PIO TYPE
+	CALL	PC_SPACE		; FORMATTING
+	LD	A,(IY+1)		; GET PIO TYPE BYTE
+	LD	DE,PIO_TYPE_STR		; POINT HL TO TYPE MAP TABLE
+	CALL	PRTIDXDEA
+
+	; ALL DONE IF NO PIO WAS DETECTED
+	LD	A,(IY+1)		; GET PIO TYPE BYTE
+	OR	A			; SET FLAGS
+	RET	Z			; IF ZERO, NOT PRESENT
+;
+	PRTS(" MODE=$")			; FORMATTING
+	LD	E,(IY+4)		; LOAD CONFIG
+	LD	D,(IY+5)		; ... WORD TO DE
+	CALL	PS_PRTPC0		; PRINT CONFIG
+;
+	LD	A,(IY+4)		; PRINT
+	BIT	2,A			; ALLOCATED
+	JR	Z,NOINT			; INTERRUPT
+	PRTS("/i$")
+	LD	A,(IY+4)
+	AND	00000011B
+	CALL	PRTDECB
+NOINT:	XOR	A
+	RET
+;
+; WORKING VARIABLES
+;
+PIO_DEV		.DB	0		; DEVICE NUM USED DURING INIT
+;	
+; DESCRIPTION OF DIFFERENT PORT TYPES
+;
+PIO_TYPE_STR:
+		.TEXT	"<NOT PRESENT>$"	; IDX 0
+		.TEXT	"Zilog PIO$"		; IDX 1
+		.TEXT	"i8255 PPI$"		; IDX 2
+		.TEXT	"IO Port$"		; IDX 3
+;
+; Z80 PIO PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. TWO PORTS
+;
+;	32 BYTE DATA STRUCTURE FOR EACH PORT
+;
+;	.DB	0		; IY+0 CIO DEVICE NUMBER 			(SET DURING PRE-INIT, THEN FIXED)
+;	.DB	0		; IY+1 PIO TYPE 				(SET AT ASSEMBLY, FIXED)
+;	.DB	0		; IY+2 PIO CHANNEL				(SET AT ASSEMBLY, FIXED)
+;	.DB	PIOBASE+2	; IY+3 BASE DATA PORT				(SET AT ASSEMBLY, FIXED)
+;	.DB	0		; IY+4 SPW - MODE 3 I/O DIRECTION BYTE		(SET AT ASSEMBLE, SET WITH INIT)
+;	.DB	0		; IY+5 SPW - MODE, INTERRUPT			(SET AT ASSEMBLY, SET WITH INIT)
+;	.DW	0		; IY+6/7 FUNCTION TABLE				(SET AT ASSEMBLY, SET DURING PRE-INIT AND AT INIT)
+;	.DW	PIO_IN		; IY+8  ADDR FOR DEVICE INPUT			(SET WITH INIT)
+;	.DW	PIO_OUT		; IY+10 ADDR FOR DEVICE OUTPUT			(SET WITH INIT)
+;	.DW	PIO_IST		; IY+12 ADDR FOR DEVICE INPUT STATUS		(SET WITH INIT)
+;	.DW	PIO_OST		; IY+14 ADDR FOR DEVICE OUTPUT STATUS		(SET WITH INIT)
+;	.DW	PIO_INITDEV	; IY+16 ADDR FOR INITIALIZE DEVICE ROUTINE	(SET AT ASSEMBLY, FIXED)
+;	.DW	PIO_QUERY	; IY+18 ADDR FOR QUERY DEVICE RECORD ROUTINE	(SET AT ASSEMBLY, FIXED)
+;	.DW	PIO_DEVICE	; IY+20 ADDR FOR DEVICE TYPE ROUTINE		(SET AT ASSEMBLY, FIXED)
+;	.FILL	10
+;
+;	SETUP PARAMETER WORD:
+;
+;	+-------------------------------+ +-------+-----------+---+-------+
+;	|         BIT CONTROL           | | MODE  |           | A |  INT  |
+;	+-------------------------------+ --------------------+-----------+
+;	 F   E   D   C   B   A   9   8     7   6   5   4   3   2   1   0
+;	-- MSB (D REGISTER) --           -- LSB (E REGISTER) --
+;
+;
+; 	MSB = BIT CONTROL MAP USE IN MODE 3 
+;
+; 	MODE B7 B6 =	00 Mode 0 Output
+;			01 Mode 1 Input
+;			10 Mode 2 Bidir
+;			11 Mode 3 Bit Mode
+;
+;	INTERRUPT ALLOCATED B2	= 0 NOT ALLOCATED
+;				= 1 IS ALLOCATED
+;
+;	WHICH IVT IS ALLOCATES B1 B0	00 IVT_PIO0
+;					01 IVT_PIO1
+;					10 IVT_PIO2
+;					11 IVT_PIO3
+;	
+#DEFINE	DEFPIO(MPIOBASE,MPIOCH0,MPIOCH1,MPIOCH0X,MPIOCH1X,MPIOIN0,MPIOIN1) \
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_ZPIO
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	MPIOBASE
+#DEFCONT \ .DB	(MPIOCH0|MPIOIN0)
+#DEFCONT \ .DB	MPIOCH0X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
+#DEFCONT \ .FILL 2	
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_ZPIO
+#DEFCONT \ .DB	1
+#DEFCONT \ .DB	MPIOBASE+1
+#DEFCONT \ .DB	(MPIOCH1|MPIOIN1)
+#DEFCONT \ .DB	MPIOCH1X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
+#DEFCONT \ .FILL 2	
+;
+; i8255 PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. THREE PORTS
+;
+#DEFINE	DEFPPI(MPPIBASE,MPPICH1,MPPICH2,MPPICH3,MPPICH1X,MPPICH2X,MPPICH3X) \
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_8255
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	MPPIBASE
+#DEFCONT \ .DB	(MPPICH1|00001000B)
+#DEFCONT \ .DB	MPPICH1X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 2
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_8255
+#DEFCONT \ .DB	1
+#DEFCONT \ .DB	MPPIBASE+2
+#DEFCONT \ .DB	(MPPICH2|00010000B)
+#DEFCONT \ .DB	MPPICH2X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 2
+#DEFCONT \ .DB	0
+#DEFCONT \ .DB	PIO_8255
+#DEFCONT \ .DB	2
+#DEFCONT \ .DB	MPPIBASE+4
+#DEFCONT \ .DB	(MPPICH3|00100000B)
+#DEFCONT \ .DB	MPPICH3X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 2
+;
+; HERE WE ACTUALLY DEFINE THE HARDWARE THAT THE HBIOS CAN ACCESS
+; THE INIT ROUTINES READ AND SET THE INITIAL MODES FROM THIS INFO
+;
+PIO_CFG:
+;
+#IF	PIO_4P
+DEFPIO(PIO4BASE+0,M_Output,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+4,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+8,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+12,M_Output,M_Output,M_BitAllOut,M_Output,INT_N,INT_N)
+#ENDIF
+#IF	PIO_ZP
+DEFPIO(PIOZBASE+0,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIOZBASE+4,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+#ENDIF
+; PIO_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC))
+
+#IF 	PIO_SBC
+DEFPPI(PIOSBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut)
+#ENDIF
+;
+PIO_CNT	.EQU	($ - PIO_CFG) / CFG_SIZ 	
+;
+;-------------------------------------------------------------------
+; WHEN WE GET HERE IY POINTS TO THE PIO_CFG TABLE WE ARE WORKING ON.
+; C IS THE UNIT NUMBER
+;-------------------------------------------------------------------
+;
+;PIO_INITUNIT:
+;	LD	A,C			; SET THE UNIT NUMBER
+;	LD	(IY),A	
+;
+;	LD	DE,-1			; LEAVE CONFIG ALONE
+;	CALL	PIO_INITDEV		; IMPLEMENT IT AND RETURN
+;	XOR	A			; SIGNAL SUCCESS
+;	RET				; AND RETURN
+;
+PIO_INIT:
+;	CALL	SPK_BEEP
+	LD	B,PIO_CNT		; COUNT OF POSSIBLE PIO UNITS
+	LD	C,0			; INDEX INTO PIO CONFIG TABLE
+PIO_INIT1:
+	PUSH	BC			; SAVE LOOP CONTROL
+	
+;	LD	A,C			; PHYSICAL UNIT TO A
+;	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+;	RLCA				; ...
+;	RLCA				; ... TO GET OFFSET INTO CFG TABLE
+;	RLCA
+;;	RLCA
+;	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+;	PUSH	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	POP	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	PUSH	HL			; COPY CFG DATA PTR
+;	POP	IY			; ... TO IY
+;	POP	IY			; ... TO IY
+
+	CALL	IDXCFG
+
+	LD	A,(IY+1)		; GET PIO TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,PIO_PRTCFG		; PRINT IF NOT ZERO
+	
+;	PUSH	DE	
+;	LD	DE,$FFFF		; INITIALIZE DEVICE/CHANNEL
+;	CALL	PIO_INITDEV		; BASED ON DPW
+;	POP	DE
+
+	POP	BC			; RESTORE LOOP CONTROL
+	INC	C			; NEXT UNIT
+	DJNZ	PIO_INIT1		; LOOP TILL DONE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+SET_PORT:
+	; DEVICE TYPE IS I/O PORT SO JUST WRITE $00 TO IT
+	LD	C,(IY+3)
+	OUT	(C),A
+	XOR	A
+	RET

Source/HBIOS/std.asm

@@ -15,6 +15,7 @@
 ; 11. DYNO	Steve Garcia's Dyno Micro-ATX Motherboard
 ; 12. RCZ280	Z280 CPU on RC2014 or ZZ80MB
 ; 13. MBC	Andrew Lynch's Multi Board Computer
+; 14. RPH	Andrew Lynch's RHYOPHYRE Graphics Computer
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -70,6 +71,7 @@ MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
 MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
 MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
 MM_MBC		.EQU	7		; MBC MEMORY MANAGER
+MM_RPH		.EQU	8		; Z180 WITH RPH EXTENSIONS
 ;
 ; BOOT STYLE
 ;
@@ -170,6 +172,7 @@ PPIDEMODE_MFP	.EQU	3		; MULTIFUNCTION / PIC
 PPIDEMODE_N8	.EQU	4		; MULTIFUNCTION / PIC
 PPIDEMODE_RC	.EQU	5		; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
 PPIDEMODE_DYNO	.EQU	6		; DYNO PPIDE @ $4C
+PPIDEMODE_RPH	.EQU	7		; RHYOPHYRE (RPH)
 ;
 ; SD MODE SELECTIONS
 ;
@@ -193,9 +196,10 @@ AYMODE_RCZ80	.EQU	3		; RC2014 SOUND MODULE BY ED BRINDLEY ON Z80
 AYMODE_RCZ180	.EQU	4		; RC2014 SOUND MODULE BY ED BRINDLEY ON Z180
 AYMODE_MSX	.EQU	5		; RC2014 SOUND MODULE REV6 BY ED BRINDLEY ON Z80/Z180 AT MSX PORTS
 AYMODE_LINC	.EQU	6		; LINC Z50 AY SOUND CARD
+AYMODE_MBC	.EQU	7		; MBC SOUND BOARD
 ;
 ; SN SOUND CHIP MODE SELECTIONS
-; 
+;
 SNMODE_NONE	.EQU	0
 SNMODE_RCZ80	.EQU	1		; RC2014 SOUND MODULE
 SNMODE_VGM	.EQU	2		; VGM ECB BOARD
@@ -208,6 +212,7 @@ TMSMODE_N8	.EQU	2		; N8 BUILT-IN VIDEO
 TMSMODE_RC	.EQU	3		; RC2014 TMS9918 VIDEO BOARD
 TMSMODE_RCV9958	.EQU	4		; RC2014 V9958 VIDEO BOARD
 TMSMODE_RCKBD	.EQU	5		; RC2014 TMS9918 + PS2 KEYBOARD
+TMSMODE_MBC	.EQU	6		; MBC V9938/58 VIDEO BOARD
 ;
 ; CVDU VIDEO MODE SELECTIONS
 ;
@@ -221,6 +226,18 @@ CVDUMON_NONE	.EQU	0
 CVDUMON_CGA	.EQU	1		; CGA MONITOR TIMING (16.000 MHZ OSC)
 CVDUMON_EGA	.EQU	2		; EGA MONITOR TIMING (16.257 MHZ OSC)
 ;
+; GDC VIDEO MODE SELECTIONS
+;
+GDCMODE_NONE	.EQU	0
+GDCMODE_ECB	.EQU	1		; ECB GDC
+GDCMODE_RPH	.EQU	2		; RPH GDC
+;
+; GDC MONITOR SELECTIONS
+;
+GDCMON_NONE	.EQU	0
+GDCMON_CGA	.EQU	1		; CGA MONITOR TIMING (16.000 MHZ OSC)
+GDCMON_EGA	.EQU	2		; EGA MONITOR TIMING (16.257 MHZ OSC)
+;
 ; DMA MODE SELECTIONS
 ;
 DMAMODE_NONE	.EQU	0
@@ -528,6 +545,10 @@ BID_IMG2	.EQU	BID_ROM0 + 3	; NETWORK BOOT				-+ ROM BANKS
 BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK			 |  ROM
 BID_ROMDN	.EQU	BID_ROMN	; LAST ROM DRIVE BANK			 V  DRIVE
 ;
+#IF (ROMSIZE == 0)
+BID_BOOT	.SET	BID_RAM0	; SPECIAL CASE ROM-LESS SYSTEM
+#ENDIF
+;
 #IF (BIOS == BIOS_WBW)
 ;
   #IF (!MDRAM)
@@ -547,22 +568,22 @@ BID_ROMDN	.SET	$FF		; ROM DRIVE DISABLED
 	.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
 	.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
 	.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
-	
+
 	.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
 	.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
 	.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
 	.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
-	
+
 	.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
 	.ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
 	.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
 	.ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
-	
+
 	.ECHO "BID_ROM0: " \ .ECHO BID_ROM0 \ .ECHO "\n"
 	.ECHO "BID_ROMN: " \ .ECHO BID_ROMN \ .ECHO "\n"
 	.ECHO "BID_RAM0: " \ .ECHO BID_RAM0 \ .ECHO "\n"
 	.ECHO "BID_RAMN: " \ .ECHO BID_RAMN \ .ECHO "\n"
-#ENDIF		
+#ENDIF
 ;
 ; MEMORY LAYOUT
 ;
@@ -700,7 +721,7 @@ INT_CTC0D	.EQU	15	; ZILOG CTC 0, CHANNEL D
 ;INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
 ;INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 ;INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
-    
+
     #ELSE
 
 INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A

Source/HBIOS/tms.asm

@@ -63,9 +63,22 @@ TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 
 #ENDIF
 ;
+#IF (TMSMODE == TMSMODE_MBC)
+
+TMS_DATREG	.EQU	$98		; READ/WRITE DATA
+TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
+TMS_ACR		.EQU	$9C		; AUX CONTROL REGISTER
+TMS_PPIA	.EQU	0		; PPI PORT A
+TMS_PPIB	.EQU	0		; PPI PORT B
+TMS_PPIC	.EQU	0		; PPI PORT C
+TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+TMS_KBDDATA	.EQU	$E2		; KBD CTLR DATA PORT
+TMS_KBDST	.EQU	$E3		; KBD CTLR STATUS/CMD PORT
+#ENDIF
+
 TMS_ROWS	.EQU	24
 
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958) | (TMSMODE == TMSMODE_MBC))
 TMS_FNTVADDR	.EQU	$1000		; VRAM ADDRESS OF FONT DATA
 TMS_COLS	.EQU	80
 #ELSE
@@ -86,7 +99,7 @@ TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 #DEFINE		TMS_IODELAY	EX (SP),HL \ EX (SP),HL	; 38 W/S
 #ELSE
 ; BELOW WAS TUNED FOR SBC AT 8MHZ
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958) | (TMSMODE == TMSMODE_MBC))
 #DEFINE		TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP ; V9958 NEEDS AT WORST CASE, APPROX 4us (28T) DELAY BETWEEN I/O (WHEN IN TEXT MODE)
 #ELSE
 #DEFINE		TMS_IODELAY	NOP \ NOP ; 8 W/S
@@ -110,18 +123,28 @@ TMS_INIT:
 	CALL	TMS_Z180IO
 #ENDIF
 ;
-#IF (TMSMODE == TMSMODE_SCG)
+#IF ((TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_MBC))
 	LD	A,$FF
 	OUT	(TMS_ACR),A		; INIT AUX CONTROL REG
 #ENDIF
-;
-	LD	IY,TMS_IDAT		; POINTER TO INSTANCE DATA
 ;
 	CALL	NEWLINE			; FORMATTING
 	PRTS("TMS: MODE=$")
+
+#IF ((TMSMODE == TMSMODE_MBC))
+	LD	A,$FE
+	OUT	(TMS_ACR),A		; INIT AUX CONTROL REG
+#ENDIF
+
+
+	LD	IY,TMS_IDAT		; POINTER TO INSTANCE DATA
+;
 #IF (TMSMODE == TMSMODE_SCG)
 	PRTS("SCG$")
 #ENDIF
+#IF (TMSMODE == TMSMODE_MBC)
+	PRTS("MBC$")
+#ENDIF
 #IF (TMSMODE == TMSMODE_N8)
 	PRTS("N8$")
 #ENDIF
@@ -153,7 +176,7 @@ TMS_INIT1:
 #IF (TMSMODE == TMSMODE_N8)
 	CALL	PPK_INIT		; INITIALIZE PPI KEYBOARD DRIVER
 #ENDIF
-#IF (TMSMODE == TMSMODE_RCKBD)
+#IF ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC))
 	CALL	KBD_INIT		; INITIALIZE 8242 KEYBOARD DRIVER
 #ENDIF
 #IF MKYENABLE
@@ -208,7 +231,7 @@ TMS_FNTBL:
 	.DW	PPK_FLUSH
 	.DW	PPK_READ
 #ELSE
-  #IF  (TMSMODE == TMSMODE_RCKBD)
+  #IF  ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC))
   	.DW	KBD_STAT
   	.DW	KBD_FLUSH
   	.DW	KBD_READ
@@ -217,7 +240,7 @@ TMS_FNTBL:
   	.DW	MKY_STAT
   	.DW	MKY_FLUSH
   	.DW	MKY_READ
-  
+
     #ELSE
   	.DW	TMS_STAT
   	.DW	TMS_FLUSH
@@ -412,7 +435,7 @@ TMS_SET:
 ;----------------------------------------------------------------------
 ;
 TMS_WR:
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958)  | (TMSMODE == TMSMODE_MBC))
         ; CLEAR R#14 FOR V9958
         XOR     A
         OUT     (TMS_CMDREG), A
@@ -903,12 +926,13 @@ TMS_IDAT:
 	.DB	TMS_PPIC        ; PPI PORT C
 	.DB	TMS_PPIX        ; PPI CONTROL PORT
 #ENDIF
-#IF (TMSMODE == TMSMODE_RCKBD)
+#IF ((TMSMODE == TMSMODE_RCKBD) | (TMSMODE == TMSMODE_MBC))
 	.DB	TMS_KBDST	; 8242 CMD/STATUS PORT
 	.DB	TMS_KBDDATA	; 8242 DATA PORT
+	.DB	0		; FILLER
+	.DB	0		; FILER
 #ENDIF
-
-TMS_PORTS:
+;
 	.DB	TMS_DATREG
 	.DB	TMS_CMDREG
 ;
@@ -954,7 +978,7 @@ TMS_PORTS:
 ; 5S		Fifth sprite (not displayed) detected. Value in FS* is valid.
 ; INT		Set at each screen update, used for interrupts.
 ;
-#IF (TMSMODE == TMSMODE_RCV9958)
+#IF ((TMSMODE == TMSMODE_RCV9958)  | (TMSMODE == TMSMODE_MBC))
 TMS_INITVDU:
 	.DB	$04		; REG 0 - NO EXTERNAL VID, SET M4 = 1
 TMS_INITVDU_REG_1:
@@ -989,7 +1013,3 @@ TMS_INITVDULEN	.EQU	$ - TMS_INITVDU
 #IF (CPUFAM == CPU_Z180)
 TMS_DCNTL	.DB	$00	; SAVE Z180 DCNTL AS NEEDED
 #ENDIF
-;
-	.ECHO	"TMS instance data occupies "
-	.ECHO	$ - TMS_IDAT
-	.ECHO	" bytes\n"

Source/Images/Build.cmd

@@ -23,6 +23,7 @@ call BuildDisk.cmd nzcom hd wbw_hd512 ..\zsdos\zsys_wbw.sys || exit /b
 call BuildDisk.cmd cpm3 hd wbw_hd512 ..\cpm3\cpmldr.sys || exit /b
 call BuildDisk.cmd zpm3 hd wbw_hd512 ..\zpm3\zpmldr.sys || exit /b
 call BuildDisk.cmd ws4 hd wbw_hd512 || exit /b
+call BuildDisk.cmd dos65 hd wbw_hd512 ..\zsdos\zsys_wbw.sys || exit /b
 
 if exist ..\BPBIOS\bpbio-ww.rel call BuildDisk.cmd bp hd wbw_hd512 || exit /b
 

Source/Images/Makefile

@@ -16,7 +16,7 @@ HD512PREFIX =
 HD1024PREFIX = hd1024_prefix.dat
 
 OBJECTS = $(FDIMGS)
-OBJECTS += $(HD512IMGS) hd512_combo.img $(HD512PREFIX)
+OBJECTS += $(HD512IMGS) hd512_dos65.img hd512_combo.img $(HD512PREFIX)
 OBJECTS += $(HD1024IMGS) hd1024_combo.img $(HD1024PREFIX)
 
 OTHERS = blank144 blankhd512 blankhd1024
@@ -71,7 +71,7 @@ blankhd1024:
 	@sys= ; \
 	case $@ in \
 		(*cpm22*) sys=../CPM22/cpm_wbw.sys;; \
-		(*zsdos* | *nzcom*) sys=../ZSDOS/zsys_wbw.sys;; \
+		(*zsdos* | *nzcom* | *dos65*) sys=../ZSDOS/zsys_wbw.sys;; \
 		(*cpm3*) sys=../CPM3/cpmldr.sys;; \
 		(*zpm3*) sys=../ZPM3/zpmldr.sys;; \
 	esac ; \

Source/Images/d_dos65/u0/dos65.hex

@@ -0,0 +1,321 @@
+:203800004C21CED84820FCBB682000BCAD92CC4A4A4A4A8DF6BFAD43BFD03CA2FF9AD8A946
+:203820001120F0BB2069BCA93E20F0BBAD8BBEAC8CBE20F4BBA000AE43BFF0DFB944BFC956
+:20384000619009C97BB005295F9944BFC8CAD0EC8A9944BF8DE7BF20A4BD202BBC8DE8BFEE
+:2038600020A5BCD064ADE9BFF004A915D02EA900AA8DECBFA001BD1DBFF01AD9C3BFD00490
+:20388000E8C8D0F2E8BD1DBFD0FAE8EEECBFADECBFC907D0DFADECBF0A6DECBFAAE8BD96B4
+:2038A000BEBC97BE8DEABF8CEBBFAD8FBE48AD8EBE486CEABF2034BC20A5BCADC4BF38E953
+:2038C000200DE9BFD0034C1BB820E1BBACEDBFB944BFF00AC920F0062072BCC8D0F1A93FB9
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Source/Images/hd_dos65.txt

@@ -0,0 +1,3 @@
+#
+# Nothing to add for now
+#

Source/ZRC/Build.cmd

@@ -1,8 +1,38 @@
 @echo off
 setlocal
 
-if not exist ..\..\Binary\RCZ80_zrc.rom goto :eof
+set TOOLS=../../Tools
 
-copy /b zrc_cfldr.bin + zrc_ptbl.bin + zrc_fill_1.bin + zrc_mon.bin + zrc_fill_2.bin + ..\..\Binary\RCZ80_zrc.rom + zrc_fill_3.bin ..\..\Binary\hd1024_zrc_prefix.dat || exit /b
+set PATH=%TOOLS%\srecord;%PATH%
 
-copy /b ..\..\Binary\hd1024_zrc_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_combo.img || exit /b
+if exist ..\..\Binary\RCZ80_zrc.rom call :build_zrc
+
+if exist ..\..\Binary\RCZ80_zrc_ram.rom call :build_zrc_ram
+
+goto :eof
+
+:build_zrc
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1024_zrc_prefix.dat
+
+copy /b ..\..\Binary\hd1024_zrc_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_combo.img || exit /b
+
+goto :eof
+
+:build_zrc_ram
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1024_zrc_ram_prefix.dat
+
+copy /b ..\..\Binary\hd1024_zrc_ram_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_ram_combo.img || exit /b
+
+goto :eof

Source/ZRC/Makefile

@@ -1,6 +1,9 @@
 HD1024ZRCPREFIX = hd1024_zrc_prefix.dat
 HD1024ZRCCOMBOIMG = hd1024_zrc_combo.img
+HD1024ZRCRAMPREFIX = hd1024_zrc_ram_prefix.dat
+HD1024ZRCRAMCOMBOIMG = hd1024_zrc_ram_combo.img
 ZRCROM = ../../Binary/RCZ80_zrc.rom
+ZRCRAMROM = ../../Binary/RCZ80_zrc_ram.rom
 HD1024IMGS = ../../Binary/hd1024_cpm22.img ../../Binary/hd1024_zsdos.img ../../Binary/hd1024_nzcom.img \
 	../../Binary/hd1024_cpm3.img ../../Binary/hd1024_zpm3.img ../../Binary/hd1024_ws4.img
 
@@ -10,6 +13,10 @@ ifneq ($(wildcard $(ZRCROM)),)
 	OBJECTS += $(HD1024ZRCPREFIX) $(HD1024ZRCCOMBOIMG)
 endif
 
+ifneq ($(wildcard $(ZRCRAMROM)),)
+	OBJECTS += $(HD1024ZRCRAMPREFIX) $(HD1024ZRCRAMCOMBOIMG)
+endif
+
 DEST=../../Binary
 
 TOOLS = ../../Tools
@@ -19,7 +26,23 @@ include $(TOOLS)/Makefile.inc
 DIFFPATH = $(DIFFTO)/Binary
 
 $(HD1024ZRCPREFIX):
-	cat zrc_cfldr.bin zrc_ptbl.bin zrc_fill_1.bin zrc_mon.bin zrc_fill_2.bin $(ZRCROM) zrc_fill_3.bin >$@
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1024ZRCRAMPREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
 
 $(HD1024ZRCCOMBOIMG): $(HD1024ZRCPREFIX) $(HD1024IMGS)
-	cat $^ > $@
+	cat $^ > $@
+
+$(HD1024ZRCRAMCOMBOIMG): $(HD1024ZRCRAMPREFIX) $(HD1024IMGS)
+	cat $^ > $@

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.159"
+#DEFINE BIOSVER	"3.1.1-pre.171"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.159"
+	db	"3.1.1-pre.171"
 	endm

Tools/Makefile.inc

@@ -97,10 +97,10 @@ CPM=$(TOOLS)/cpm/bin80/
 %.rel: %.z80
 	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/MF
 
-%.hex: %.z80
-	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF
+#%.hex: %.z80
+#	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF
 
-%.hex: %.180
+%.hex: %.z80
 	$(ZXCC) $(CPM)/SLR180 -$(basename $<)/HF
 
 %.rel: %.azm