Final Round of User Guide Updates per Martin R

Documentation Updates Inspired by Martin R
- Implemented a crude mechanism to output config settings during a build which can be imported into the User Guide appendix.
2026-02-06 22:43:15 -06:00 · 2023-11-30 12:52:11 -08:00 · 2023-11-29 18:54:51 -08:00 · 2023-11-27 19:15:19 -08:00 · 2023-11-27 17:58:24 -08:00 · 2023-11-27 17:44:53 -08:00
197 changed files with 20795 additions and 1724 deletions
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -26,7 +26,7 @@ jobs:
        run: |
          export TZ='America/Los_Angeles'
          sudo apt-get install srecord
-          make dist
+          make distlog
          rm -rf .git*

      - name: List Output
@@ -58,7 +58,7 @@ jobs:
        run: |
          export TZ='America/Los_Angeles'
          brew install srecord
-          make dist
+          make distlog
          rm -rf .git*

      - name: List Output
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -19,7 +19,7 @@ jobs:
          export TZ='America/Los_Angeles'
          sudo apt-get install libncurses-dev
          sudo apt-get install srecord
-          make dist
+          make distlog
          rm -rf .git*
      
      - name: Create Package Archive
--- a/.gitignore
+++ b/.gitignore
@@ -95,8 +95,8 @@ Tools/unix/zx/zx
 !Source/ZPM3/*.[Cc][Oo][Mm]
 !Source/ZSDOS/*.[Cc][Oo][Mm]
 !Source/ZRC/*.bin
-!Source/ZZRC/*.bin
-!Source/ZZRC/*.hex
+!Source/Z1RCC/*.bin
+!Source/ZZRCC/*.bin
 !Tools/cpm/**
 !Tools/unix/zx/*
 !Tools/zx/*
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -2,6 +2,9 @@ Version 3.4
 -----------
 NOTE: Changes require HBIOS/CBIOS/Apps sync, version bump to 3.4 to ensure integrity
 - WBW: Device type number moved from upper nibble to full byte
+- A?C: Support for EP ITX-Mini Z180 Platform
+- M?R: Significant improvement in User Guide document
+

 Version 3.3
 -----------
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Catalog.pdf
+++ b/Catalog.pdf
--- a/Errata.pdf
+++ b/Errata.pdf
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/10
+++ b/10
@@ -1,5 +1,8 @@
 .PHONY: tools source clean clobber diff dist

+.ONESHELL:
+.SHELLFLAGS = -cex
+
 all: tools source

 tools:
@@ -20,6 +23,9 @@ diff:
 	$(MAKE) --directory Source diff

 dist:
-	$(MAKE) ROM_PLATFORM=dist 2>&1 | tee make.log
-	$(MAKE) --directory Source clean
+	$(MAKE) ROM_PLATFORM=dist
 	$(MAKE) --directory Tools clean
+	$(MAKE) --directory Source clean
+
+distlog:
+	$(MAKE) dist 2>&1 | tee make.log
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.4 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-09 Oct 2023
+30 Nov 2023

 # Overview

@@ -14,15 +14,24 @@ platforms are supported including those produced by these developer
 communities:

 - [RetroBrew Computers](https://www.retrobrewcomputers.org)
- [RC2014](https://rc2014.co.uk),
+  (<https://www.retrobrewcomputers.org>)
+- [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>),  
  [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
- [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://groups.google.com/g/rc2014-z80>)
+- [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 - [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+\[Installation\] section.

 General features include:

+- Z80 Family CPUs including Z80, Z180, and Z280
 - Banked memory services for several banking designs
- Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+- Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+  Iomega
 - Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 - Video drivers including TMS9918, SY6545, MOS8563, HD6445
 - Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -42,11 +51,11 @@ ROM firmware itself:

 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.

 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -66,7 +75,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.

 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -76,18 +85,19 @@ OSes such as Windows, MacOS, and Linux very easy.

 # Acquiring RomWBW

-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation. The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository. On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the “Assets” drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official
+distribution location for all project source and documentation. The
+fully-built distribution releases are available on the [RomWBW Releases
+Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository. On
+this page, you will normally see a Development Snapshot as well as
+recent stable releases. Unless you have a specific reason, I suggest you
+stick to the most recent stable release. Expand the “Assets” drop-down
+for the release you want to download, then select the asset named
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
+and Disk images as well as full source code. The other assets contain
+only source code and do not have the pre-built ROM or disk images.

 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-09 Oct 2023
+30 Nov 2023



@@ -13,15 +13,21 @@ Z80/180/280 retro-computing hardware systems. A wide variety of
 platforms are supported including those produced by these developer
 communities:

-   RetroBrew Computers
-   RC2014, RC2014-Z80
-   retro-comp
-   Small Computer Central
+-   RetroBrew Computers (https://www.retrobrewcomputers.org)
+-   RC2014 (https://rc2014.co.uk),
+    RC2014-Z80 (https://groups.google.com/g/rc2014-z80)
+-   Retro Computing (https://groups.google.com/g/retro-comp)
+-   Small Computer Central (https://smallcomputercentral.com/)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.

 General features include:

+-   Z80 Family CPUs including Z80, Z180, and Z280
 -   Banked memory services for several banking designs
-   Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+-   Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip,
+    Iomega
 -   Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 -   Video drivers including TMS9918, SY6545, MOS8563, HD6445
 -   Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -41,11 +47,11 @@ ROM firmware itself:

 A dynamic disk drive letter assignment mechanism allows mapping
 operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains a
-complete CP/M filesystem and can be mapped independently to any drive
-letter. This overcomes the inherent size limitations in legacy OSes and
-allows up to 2GB of accessible storage on a single device.
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.)
+support the use of multiple slices (up to 256 per device). Each slice
+contains a complete CP/M filesystem and can be mapped independently to
+any drive letter. This overcomes the inherent size limitations in legacy
+OSes and allows up to 2GB of accessible storage on a single device.

 The pre-built ROM firmware images are generally suitable for most users.
 However, it is also very easy to modify and build custom ROM images that
@@ -65,7 +71,7 @@ changing media.
 By design, RomWBW isolates all of the hardware specific functions in the
 ROM chip itself. The ROM provides a hardware abstraction layer such that
 all of the operating systems and applications on a disk will run on any
-RomWBW-based system. To put it simply, you can take a disk (or CF/SD
+RomWBW-based system. To put it simply, you can take a disk (or CF/SD/USB
 Card) and move it between systems transparently.

 A tool is provided that allows you to access a FAT-12/16/32 filesystem.
@@ -78,16 +84,18 @@ OSes such as Windows, MacOS, and Linux very easy.
 ACQUIRING ROMWBW


-The RomWBW Repository on GitHub is the official distribution location
-for all project source and documentation. The fully-built distribution
-releases are available on the RomWBW Releases Page of the repository. On
-this page, you will normally see a Development Snapshot as well as
-recent stable releases. Unless you have a specific reason, I suggest you
-stick to the most recent stable release. Expand the “Assets” drop-down
-for the release you want to download, then select the asset named
-RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM
-and Disk images as well as full source code. The other assets contain
-only source code and do not have the pre-built ROM or disk images.
+The RomWBW Repository (https://github.com/wwarthen/RomWBW) on GitHub is
+the official distribution location for all project source and
+documentation. The fully-built distribution releases are available on
+the RomWBW Releases Page (https://github.com/wwarthen/RomWBW/releases)
+of the repository. On this page, you will normally see a Development
+Snapshot as well as recent stable releases. Unless you have a specific
+reason, I suggest you stick to the most recent stable release. Expand
+the “Assets” drop-down for the release you want to download, then select
+the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
+all pre-built ROM and Disk images as well as full source code. The other
+assets contain only source code and do not have the pre-built ROM or
+disk images.

 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
--- a/Source/Apps/FAT/ReadMe.txt
+++ b/Source/Apps/FAT/ReadMe.txt
@@ -1,7 +1,7 @@
 RomWBW HBIOS CP/M FAT Utility ("FAT.COM")

 Author: Wayne Warthen
-Updated: 12-Apr-2021
+Updated: 12-Oct-2023

 Application to manipulate and exchange files with a FAT (DOS)
 filesystem.  Runs on any HBIOS hosted CP/M implementation.
@@ -101,4 +101,5 @@ HISTORY:
  11-Oct-2019: v0.9.7 (beta) fix FORMAT to use existing partition table entries
                             add attributes to directory listing
  12-Apr-2021: v0.9.8 (beta) support CP/NET drives
+  12-Oct-2023: v0.9.9 (beta) handle updated HBIOS Disk Device call
 		      
--- a/Source/Apps/FAT/fat.com
+++ b/Source/Apps/FAT/fat.com
--- a/Source/Apps/Test/ps2info/ps2info.asm
+++ b/Source/Apps/Test/ps2info/ps2info.asm
@@ -7,20 +7,24 @@
 ; keyboard, and mouse.
 ;
 ; WBW 2022-03-28: Add menu driven port selection
-;                 Add support for RHYOPHYRE
+;                 Add support for Rhyophyre
 ; WBW 2022-04-01: Add menu for test functions
 ; WBW 2022-04-02: Fix prtchr register saving/recovery
+; WBW 2023-10-19: Add support for Duodyne
 ;
 ;=======================================================================
 ;
 ; PS/2 Keyboard/Mouse controller port addresses (adjust as needed)
 ;
-; MBC:
+; Nhyodyne:
 iocmd_mbc	.equ	$E3	; PS/2 controller command port address
 iodat_mbc	.equ	$E2	; PS/2 controller data port address
-; RPH:
+; Rhyophyre:
 iocmd_rph	.equ	$8D	; PS/2 controller command port address
 iodat_rph	.equ	$8C	; PS/2 controller data port address
+; Duodyne:
+iocmd_duo	.equ	$4D	; PS/2 controller command port address
+iodat_duo	.equ	$4C	; PS/2 controller data port address
 ;
 cpumhz	.equ	8	; for time delay calculations (not critical)
 ;
@@ -77,10 +81,12 @@ setup1:
 	jr	z,setup1
 	call	upcase
 	call	prtchr
-	cp	'1'			; MBC
+	cp	'1'			; Nhyodyne
 	jr	z,setup_mbc
-	cp	'2'			; RHYOPHYRE
+	cp	'2'			; Rhyophyre
 	jr	z,setup_rph
+	cp	'3'			; Duodyne
+	jr	z,setup_duo
 	cp	'X'
 	jr	z,exit
 	jr	setup
@@ -101,6 +107,14 @@ setup_rph:
 	ld	de,str_rph
 	jr	setup2
 ;
+setup_duo:
+	ld	a,iocmd_duo
+	ld	(iocmd),a
+	ld	a,iodat_duo
+	ld	(iodat),a
+	ld	de,str_duo
+	jr	setup2
+;
 setup2:
 	call	prtstr
 	call	crlf2
@@ -181,6 +195,12 @@ test_kbd:
 ;
 	call	ctlr_test
 	jr	nz,test_kbd_fail
+;
+	ld	a,$20			; kbd enabled, mse disabled, no ints
+	call	ctlr_setup
+	jr	nz,test_kbd_fail
+;
+	call	ctlr_flush
 ;
 	call	test_kbd_basic
 	jr	nz,test_kbd_fail
@@ -228,9 +248,13 @@ test_mse:
 	ld	a,$10			; kbd disabled, mse enabled, no ints
 	call	ctlr_setup
 	jr	nz,test_mse_fail
+;
+	call	ctlr_flush
 ;
 	call	mse_reset
 	jr	nz,test_mse_fail
+;
+	call	ctlr_flush
 ;
 	call	mse_ident
 	jr	nz,test_mse_fail
@@ -262,15 +286,21 @@ test_kbdmse:
 	ld	a,$00			; kbd enabled, mse enabled, no ints
 	call	ctlr_setup
 	jr	nz,test_kbdmse_fail
+;
+	call	ctlr_flush
 ;
 	call	kbd_reset
 	jr	nz,test_kbdmse_fail
+;
+	call	ctlr_flush
 ;
 	ld	a,2
 	call	kbd_setsc
 ;
 	call	mse_reset
 	jr	nz,test_kbdmse_fail
+;
+	call	ctlr_flush
 ;
 	call	mse_stream
 	jr	nz,test_kbdmse_fail
@@ -290,15 +320,13 @@ test_kbdmse_fail:
 ; inventory the supported scan code sets.
 ;
 test_kbd_basic:
-	ld	a,$20			; Xlat off for this checking
-	call	ctlr_setup
-	ret	nz
-;
 	call	kbd_reset
 	ret	nz
+;
+	call	ctlr_flush
 ;
 	call	kbd_ident
-	;ret	nz
+	ret	nz
 ;
 	ld	b,3			; Loop control, 3 scan code sets
 	ld	c,1			; Current scan code number
@@ -436,6 +464,19 @@ ctlr_setup:
 	xor	a
 	ret
 ;
+; Flush incoming data buffer
+;
+ctlr_flush:
+	call	crlf2
+	ld	de,str_ctlr_flush
+	call	prtstr
+ctlr_flush1:
+	call	delay			; small delay
+	call	check_read		; data pending?
+	ret	nz			; return if nothing there
+	call	get_data_dbg		; get and discard byte
+	jr	ctlr_flush1		; loop
+;
 ; Perform a keyboard reset
 ;
 kbd_reset:
@@ -612,13 +653,17 @@ mse_reset:
 	call	crlf2
 	ld	de,str_mse_reset
 	call	prtstr
-	ld	a,$f2			; Identify mouse command
+	ld	a,$ff			; Identify mouse command
 	call	put_data_mse_dbg
 	jp	c,err_ctlr_to		; handle controller error
 	call	get_data_dbg
 	jp	c,err_ctlr_to		; handle controller error
 	cp	$fa			; Is it an ack as expected?
 	jp	nz,err_mse_reset
+	call	get_data_dbg
+	jp	c,err_ctlr_to		; handle controller error
+	cp	$aa			; Success?
+	jp	nz,err_mse_reset
 	call	crlf
 	ld	de,str_mse_reset_ok
 	call	prtstr
@@ -634,18 +679,61 @@ mse_ident:
 	ld	a,$f2			; Identify mouse command
 	call	put_data_mse_dbg
 	jp	c,err_ctlr_to		; handle controller error
+mse_ident0:
 	call	get_data_dbg
 	jp	c,err_ctlr_to		; handle controller error
+
+	;cp	$00			; extraneous?
+	;jr	z,mse_ident0		; ignore it, get another
+
 	cp	$fa			; Is it an ack as expected?
 	jp	nz,err_mse_ident
-	call	get_data_dbg
-	jp	c,err_ctlr_to		; handle controller error
+	; Now we need to receive 0-2 bytes.  There is no way to know
+	; how many are coming, so we receive bytes until there is a
+	; timeout error.  Timeout is shortened here so that we don't
+	; have to wait seconds for the routine to complete normally.
+	; A short timeout is more than sufficient here.
+	ld	ix,workbuf
+	ld	a,(timeout)		; save current timeout
 	push	af
+	ld	a,stimout		; set a short timeout
+	ld	(timeout),a
+	ld	b,8			; buf max
+	ld	c,0			; buf len
+mse_ident1:
+	push	bc
+	call	get_data_dbg
+	pop	bc
+	jr	c,mse_ident2
+	ld	(ix),a
+	inc	ix
+	inc	c
+	djnz	mse_ident1
+mse_ident2:
+	pop	af			; restore original timeout
+	ld	(timeout),a
 	call	crlf
 	ld	de,str_mse_ident_disp
 	call	prtstr
-	pop	af
-	call	prtdecb
+	ld	a,'['
+	call	prtchr
+	ld	ix,workbuf
+	ld	a,c			; bytes to print
+	or	a			; check for zero
+	jr	z,mse_ident4		; handle zero
+	ld	b,a			; setup loop counter
+	jr	mse_ident3a
+mse_ident3:
+	ld	a,','
+	call	prtchr
+mse_ident3a:
+	ld	a,(ix)
+	call	prthex
+	inc	ix
+	djnz	mse_ident3
+mse_ident4:
+	ld	a,']'
+	call	prtchr
 	xor	a
 	ret
 ;
@@ -658,8 +746,13 @@ mse_stream:
 	ld	a,$f4			; Stream packets cmd
 	call	put_data_mse_dbg
 	jp	c,err_ctlr_to		; handle controller error
+mse_stream0:
 	call	get_data_dbg
 	jp	c,err_ctlr_to		; handle controller error
+
+	;cp	$00			; extraneous?
+	;jr	z,mse_stream0		; ignore it, get another
+
 	cp	$FA			; Is it an ack as expected?
 	jp	nz,err_mse_stream
 	xor	a
@@ -1344,14 +1437,16 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"PS/2 Keyboard/Mouse Information v0.6a, 2-Apr-2022",0
+str_banner		.db	"PS/2 Keyboard/Mouse Information v0.8, 6-Nov-2023",0
 str_hwmenu		.db	"PS/2 Controller Port Options:\r\n\r\n"
-			.db	"  1 - MBC\r\n"
-			.db	"  2 - RHYOPHYRE\r\n"
+			.db	"  1 - Nhyodyne\r\n"
+			.db	"  2 - Rhyophyre\r\n"
+			.db	"  3 - Duodyne\r\n"
 			.db	"  X - Exit Application\r\n"
 			.db	"\r\nSelection? ",0
-str_mbc			.db	"MBC",0
-str_rph			.db	"RHYOPHYRE",0
+str_mbc			.db	"Nhyodyne",0
+str_rph			.db	"Rhyophyre",0
+str_duo			.db	"Duodyne",0
 str_menu		.db	"PS/2 Testing Options:\r\n\r\n"
 			.db	"  C - Test PS/2 Controller\r\n"
 			.db	"  K - Test PS/2 Keyboard\r\n"
@@ -1382,6 +1477,7 @@ str_trans_off		.db	"***** Testing Keyboard with Scan Code Translation DISABLED *
 str_trans_on		.db	"***** Testing Keyboard with Scan Code Translation ENABLED *****",0
 str_basic_mse		.db	"***** Basic Mouse Tests *****",0
 str_kbdmse			.db	"***** Test All Devices Combined *****",0
+str_ctlr_flush		.db	"Flushing controller input buffer",0
 str_kbd_reset		.db	"Attempting Keyboard Reset",0
 str_kbd_reset_ok	.db	"Keyboard Reset OK",0
 str_err_kbd_reset	.db	"Keyboard Reset Failed",0
--- a/Source/Apps/assign.asm
+++ b/Source/Apps/assign.asm
@@ -32,6 +32,7 @@
 ;                    Use CPM3 BDOS direct BIOS call to get DRVTBL adr
 ;   2023-06-19 [WBW] Update for revised DIODEVICE API
 ;   2023-09-19 [WBW] Added CHUSB & CHSD device support
+;   2023-10-13 [WBW] Fixed DPH creation to select correct DPB
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -665,10 +666,10 @@ makdphwbw:	; determine appropriate dpb (WBW mode, unit number in A)
 	jr	makdph0		; jump ahead
 makdph00:	
 	ld	e,6		; assume floppy
-	cp	$10		; floppy?
+	cp	$01		; floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,3		; assume ram floppy
-	cp	$20		; ram floppy?
+	cp	$02		; ram floppy?
 	jr	z,makdph0	; yes, jump ahead
 	ld	e,4		; everything else is assumed to be hard disk
 	jr	makdph0		; yes, jump ahead
@@ -1935,13 +1936,13 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v1.7 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v1.8 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 19-Sep-2023",0
+msbban2	.db	", 13-Oct-2023",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
-msgban3	.db	"Copyright 2021, Wayne Warthen, GNU GPL v3",0
+msgban3	.db	"Copyright 2023, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"Usage: ASSIGN D:[=[{D:|<device>[<unitnum>]:[<slicenum>]}]][,...]",13,10
 	.db	"  ex. ASSIGN           (display all active assignments)",13,10
 	.db	"      ASSIGN /?        (display version and usage)",13,10
--- a/Source/Build.cmd
+++ b/Source/Build.cmd
@@ -8,6 +8,7 @@ call BuildShared || exit /b
 call BuildImages || exit /b
 call BuildROM %* || exit /b
 call BuildZRC || exit /b
+call BuildZ1RCC || exit /b
 call BuildZZRCC || exit /b

 if "%1" == "dist" (
--- a/Source/BuildZ1RCC.cmd
+++ b/Source/BuildZ1RCC.cmd
@@ -0,0 +1,4 @@
+@echo off
+setlocal
+
+pushd Z1RCC && call Build || exit /b & popd
--- a/Source/CPM3/biosldr.z80
+++ b/Source/CPM3/biosldr.z80
@@ -346,8 +346,7 @@ read:
 	ld	b,17h			; HBIOS DEVICE function
 	rst	08			; Do it, D=device type
 	ld	a,d			; put in accum
-	and	0F0h			; isolate high bits
-	cp	10h			; floppy?
+	cp	01h			; floppy?
 	jr	nz,read2		; if not, do LBA i/o
 	
 	; Floppy I/O
--- a/Source/CPM3/boot.z80
+++ b/Source/CPM3/boot.z80
@@ -13,7 +13,7 @@
 	extrn	@dtbl,@ctbl
 	extrn	@date,@hour,@min,@sec
 	extrn	@srch1
-	extrn	@hbbio
+	extrn	@hbbio,@hbusr
 	extrn	addhla
 	extrn	phex16, phex8
 	extrn	cin, cout
@@ -46,7 +46,7 @@ tpa$bank	equ 0
 	; Clone page zero from bank 0 to additional banks
 	ld	b,2			; last bank
 	ld	c,0			; src bank
-init$2:
+init$1:
 	push	bc			; save bank id's
 	call	?xmove			; set src/dest banks
 	ld	bc,0100h		; size is one page
@@ -54,7 +54,7 @@ init$2:
 	ld	de,0			; src adr is 0
 	call	?move			; do it
 	pop	bc			; restore bank id's
-	djnz	init$2			; loop till done
+	djnz	init$1			; loop till done
 	
 	endif

@@ -62,6 +62,35 @@ init$2:
 	ld	hl,signon$msg		; signon message
 	call	?pmsg			; print it

+	if banked
+	
+	; Confirm that HBIOS is configured with enough RAM banks
+	; to accommodate banked version of CP/M 3.  We use 2
+	; additional banks which live below the user bank.  So we
+	; check that the these don't overlap with the RomWBW HBIOS
+	; bank.
+
+	ld	bc,0F8F2h	; HBIOS GET BNKINFO
+	call	0FFF0h		; D: BIOS Bank, E: User Bank
+	ld	a,d
+	ld	(@hbbio),a
+	ld	a,e
+	ld	(@hbusr),a
+	
+	sub	3		; 2 extra banks (+1 for compare)
+	cp	d		; lowest cpm bank - hbios bank
+	jr	nc,init$2	; continue if space available
+	
+	ld	hl,noram$msg	; signon message
+	call	?pmsg		; print it
+
+	ld	b,0F0h		; HBIOS system reset
+	ld	c,1h		; reset type warm (back to loader)
+	call	0FFFFh		; do it
+
+	endif
+
+init$2:
 	; Check for HBIOS/CBIOS mismatch
 	ld	b,0F1h			; hbios version
 	rst	08			; do it, de=maj/min/up/pat
@@ -731,6 +760,10 @@ clrflg		db	0		; RAM disk cleared flag
 clr$msg		db	'RAM Disk Initialized',13,10,13,10,0
 vermis$msg	db	7,'*** WARNING: HBIOS/CBIOS Version Mismatch ***',13,10,13,10,0

+	if banked
+noram$msg	db	7,'*** ERROR: Insufficient RAM for banked CP/M 3 ***',13,10,13,10,0
+	endif
+
 	if zpm

 signon$msg	db	13,10,'ZPM3'
--- a/Source/Clean.cmd
+++ b/Source/Clean.cmd
@@ -22,4 +22,5 @@ pushd Prop && call Clean & popd
 pushd RomDsk && call Clean & popd
 pushd Doc && call Clean & popd
 pushd ZRC && call Clean & popd
+pushd Z1RCC && call Clean & popd
 pushd ZZRCC && call Clean & popd
--- a/Source/Doc/Book.h
+++ b/Source/Doc/Book.h
@@ -30,7 +30,9 @@ header-includes:
      {\scshape \bfseries \fontsize{48pt}{56pt} \selectfont $doc_product$ \par}
      {\bfseries \fontsize{32pt}{36pt} \selectfont $doc_title$ \par}
      \vspace{24pt}
-      {\huge $doc_ver$ \\ $doc_date$ \par}
+      {\huge $doc_ver$ \par}
+      \vspace{12pt}
+      {\large Updated $doc_date$ \par}
      \vspace{24pt}
      {\large \itshape $doc_orgname$ \\ \href{http://$doc_orgurl$}{$doc_orgurl$} \par}
      \vspace{12pt}
--- a/Source/Doc/ReadMe.md
+++ b/Source/Doc/ReadMe.md
@@ -10,14 +10,23 @@ A wide variety of platforms are supported including those
 produced by these developer communities:

 * [RetroBrew Computers](https://www.retrobrewcomputers.org)
-* [RC2014](https://rc2014.co.uk), [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
-* [retro-comp](https://groups.google.com/forum/#!forum/retro-comp)
+  (<https://www.retrobrewcomputers.org>)
+* [RC2014](https://rc2014.co.uk) (<https://rc2014.co.uk>), \
+  [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
+  (<https://groups.google.com/g/rc2014-z80>)
+* [Retro Computing](https://groups.google.com/g/retro-comp)
+  (<https://groups.google.com/g/retro-comp>)
 * [Small Computer Central](https://smallcomputercentral.com/)
+  (<https://smallcomputercentral.com/>)
+
+A complete list of the currently supported platforms is found in the
+[Installation] section.

 General features include:

+* Z80 Family CPUs including Z80, Z180, and Z280
 * Banked memory services for several banking designs
-* Disk drivers for RAM, ROM, Floppy, IDE, CF, and SD
+* Disk drivers for RAM, ROM, Floppy, IDE ATA/ATAPI, CF, SD, USB, Zip, Iomega
 * Serial drivers including UART (16550-like), ASCI, ACIA, SIO
 * Video drivers including TMS9918, SY6545, MOS8563, HD6445
 * Keyboard (PS/2) drivers via VT8242 or PPI interfaces
@@ -34,12 +43,12 @@ ROM firmware itself:
 * ROM BASIC (Nascom BASIC and Tasty BASIC)
 * ROM Forth

-A dynamic disk drive letter assignment mechanism allows mapping
-operating system drive letters to any available disk media.
-Additionally, mass storage devices (IDE Disk, CF Card, SD Card) support
-the use of multiple slices (up to 256 per device). Each slice contains
-a complete CP/M filesystem and can be mapped independently to any
-drive letter. This overcomes the inherent size limitations in legacy
+A dynamic disk drive letter assignment mechanism allows mapping 
+operating system drive letters to any available disk media. 
+Additionally, mass storage devices (IDE Disk, CF Card, SD Card, etc.) 
+support the use of multiple slices (up to 256 per device). Each slice 
+contains a complete CP/M filesystem and can be mapped independently to 
+any drive letter. This overcomes the inherent size limitations in legacy
 OSes and allows up to 2GB of accessible storage on a single device.

 The pre-built ROM firmware images are generally suitable for most
@@ -61,7 +70,7 @@ By design, RomWBW isolates all of the hardware specific functions in
 the ROM chip itself.  The ROM provides a hardware abstraction layer
 such that all of the operating systems and applications on a disk
 will run on any RomWBW-based system.  To put it simply, you can take
-a disk (or CF/SD Card) and move it between systems transparently.
+a disk (or CF/SD/USB Card) and move it between systems transparently.

 A tool is provided that allows you to access a FAT-12/16/32 filesystem. 
 The FAT filesystem may be coresident on the same disk media as RomWBW 
@@ -70,18 +79,19 @@ OSes such as Windows, MacOS, and Linux very easy.

 # Acquiring RomWBW

-The [RomWBW Repository](https://github.com/wwarthen/RomWBW) on GitHub is
-the official distribution location for all project source and
-documentation.  The fully-built distribution releases are available on
-the [RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
-of the repository.  On this page, you will normally see a Development
-Snapshot as well as recent stable releases. Unless you have a specific
-reason, I suggest you stick to the most recent stable release. Expand
-the "Assets" drop-down for the release you want to download, then select
-the asset named RomWBW-vX.X.X-Package.zip. The Package asset includes
-all pre-built ROM and Disk images as well as full source code. The other
-assets contain only source code and do not have the pre-built ROM or
-disk images.
+The [RomWBW Repository](https://github.com/wwarthen/RomWBW)
+(<https://github.com/wwarthen/RomWBW>) on GitHub is the official 
+distribution location for all project source and documentation.  The 
+fully-built distribution releases are available on the
+[RomWBW Releases Page](https://github.com/wwarthen/RomWBW/releases)
+(<https://github.com/wwarthen/RomWBW/releases>) of the repository.  On 
+this page, you will normally see a Development Snapshot as well as 
+recent stable releases. Unless you have a specific reason, I suggest you
+ stick to the most recent stable release. Expand the "Assets" drop-down 
+for the release you want to download, then select the asset named 
+RomWBW-vX.X.X-Package.zip. The Package asset includes all pre-built ROM 
+and Disk images as well as full source code. The other assets contain 
+only source code and do not have the pre-built ROM or disk images.

 All source code and distributions are maintained on GitHub. Code
 contributions are very welcome.
--- a/Source/Doc/UserGuide.md
+++ b/Source/Doc/UserGuide.md
--- a/Source/HBIOS/Build.cmd
+++ b/Source/HBIOS/Build.cmd
@@ -33,6 +33,16 @@ PowerShell -ExecutionPolicy Unrestricted .\Build.ps1 %* || exit /b

 call build_env.cmd

+::
+:: Start of the actual build process for a given ROM.
+::
+
+echo.
+echo ============================================================
+echo %ROMName% for Z%CPUType% CPU
+echo ============================================================
+echo.
+
 ::
 :: Create a small app that is used to export key build variables of the build.
 :: Then run the app to output a file with the variables.  Finally, read the
@@ -43,12 +53,6 @@ tasm -t80 -g3 -dCMD hbios_env.asm hbios_env.com hbios_env.lst || exit /b
 zxcc hbios_env >hbios_env.cmd
 call hbios_env.cmd

-::
-:: Start of the actual build process for a given ROM.
-::
-
-echo Building %ROMSize%K ROM %ROMName% for Z%CPUType% CPU...
-
 ::
 :: UNA is a special case, check for it and jump if needed.
 ::
@@ -216,6 +220,7 @@ call Build RCZ80 zrc || exit /b
 call Build RCZ80 zrc_ram || exit /b
 call Build RCZ180 ext || exit /b
 call Build RCZ180 nat || exit /b
+call Build RCZ180 z1rcc || exit /b
 call Build RCZ280 ext || exit /b
 call Build RCZ280 nat || exit /b
 call Build RCZ280 zz80mb || exit /b
@@ -234,5 +239,6 @@ call Build Z80RETRO std || exit /b
 call Build S100 std || exit /b
 call Build DUO std || exit /b
 call Build HEATH std || exit /b
+call Build EPITX std || exit /b

 goto :eof
--- a/Source/HBIOS/Build.ps1
+++ b/Source/HBIOS/Build.ps1
@@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
 #

 $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
 $PlatformListZ280 = "RCZ280"

 #
--- a/Source/HBIOS/Build.sh
+++ b/Source/HBIOS/Build.sh
@@ -15,6 +15,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; bash Build.sh
 	ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
 	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
@@ -46,6 +47,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi

--- a/Source/HBIOS/Config/EPITX_std.asm
+++ b/Source/HBIOS/Config/EPITX_std.asm
@@ -0,0 +1,64 @@
+;
+;==================================================================================================
+;   Z180 Mini ITX STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	PLATFORM_NAME	"Z180 MiniITX"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_epitx.asm"
+;
+CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+;
+LEDENABLE	.SET	FALSE		; ENABLE STATUS LED (SINGLE LED)
+;
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+FDMODE		.SET	FDMODE_EPFDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
+;
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/RCZ180_z1rcc.asm
+++ b/Source/HBIOS/Config/RCZ180_z1rcc.asm
@@ -0,0 +1,76 @@
+;
+;==================================================================================================
+;   RCBUS Z180 Z1RCC CONFIGURATION (ROMLESS)
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "Z1RCC", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz180.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/RCZ280_zzrcc.asm
+++ b/Source/HBIOS/Config/RCZ280_zzrcc.asm
@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	29491200	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
--- a/Source/HBIOS/Config/RCZ280_zzrcc_ram.asm
+++ b/Source/HBIOS/Config/RCZ280_zzrcc_ram.asm
@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz280.asm"
 ;
-CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	29491200	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
--- a/Source/HBIOS/Config/RCZ80_zrc.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc.asm
@@ -27,13 +27,15 @@
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
 #include "cfg_rcz80.asm"
+;
 CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPSW_ENABLE     .SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	256		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
--- a/Source/HBIOS/Config/RCZ80_zrc_ram.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc_ram.asm
@@ -28,7 +28,7 @@
 ;
 #include "cfg_rcz80.asm"
 ;
-CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
@@ -50,7 +50,7 @@ TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
--- a/Source/HBIOS/Config/ZETA_std.asm
+++ b/Source/HBIOS/Config/ZETA_std.asm
@@ -26,7 +26,7 @@
 ;
 #include "cfg_zeta.asm"
 ;
-CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -178,10 +178,26 @@ ACIA1_INT:
 ;
 ACIA_INTRCV:
        ; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
+	CALL	DELAY
        LD      C,(IY+3)                ; CMD/STAT PORT TO C
        IN      A,(C)                   ; GET STATUS
-        RRA                             ; READY BIT TO CF
-        RET     NC                      ; NOTHING AVAILABLE ON CURRENT CHANNEL
+	LD	B,A
+	AND	$01			; ISOLATE READY BIT
+	JR	NZ,ACIA_INTRCV1
+;
+#IF FALSE
+	CALL	PC_LT
+	LD	A,B
+	CALL	PRTHEXBYTE
+	INC	C
+	IN	A,(C)
+	CALL	PRTHEXBYTE
+	CALL	PC_GT
+	OR	$FF
+#ENDIF
+;
+	RET
+	
 ;
 ACIA_INTRCV1:
        ; RECEIVE CHARACTER INTO BUFFER
@@ -701,6 +717,13 @@ ACIA0_CFG:
        .DW     ACIA0_INT                ; INT HANDLER POINTER
        .DW     (ACIA0CLK / ACIA0DIV) & $FFFF   ; CLOCK FREQ AS
        .DW     (ACIA0CLK / ACIA0DIV) >> 16     ; ... DWORD VALUE
+;
+	.ECHO	"ACIA: IO="
+	.ECHO	ACIA0BASE
+#IF (INTMODE == 1)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ACIA_CFGSIZ     .EQU    $ - ACIA_CFG    ; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -717,6 +740,13 @@ ACIA1_CFG:
        .DW     ACIA1_INT                ; INT HANDLER POINTER
        .DW     (ACIA1CLK / ACIA1DIV) & $FFFF   ; CLOCK FREQ AS
        .DW     (ACIA1CLK / ACIA1DIV) >> 16     ; ... DWORD VALUE
+;
+	.ECHO	"ACIA: IO="
+	.ECHO	ACIA1BASE
+#IF (INTMODE == 1)
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/asci.asm
+++ b/Source/HBIOS/asci.asm
@@ -836,6 +836,13 @@ ASCI1_CFG:
 	.DB	ASCI1_BASE		; BASE PORT
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI1_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -847,6 +854,13 @@ ASCI0_CFG:
 	.DB	ASCI0_BASE		; BASE PORT
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI0_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ELSE
 ;
@@ -858,6 +872,13 @@ ASCI0_CFG:
 	.DB	ASCI0_BASE		; BASE PORT
 	.DW	ASCI0CFG		; LINE CONFIGURATION
 	.DW	ASCI0_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI0_BASE
+#IF ((ASCIINTS) & (INTMODE >0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 ASCI_CFGSIZ	.EQU	$ - ASCI_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -869,8 +890,14 @@ ASCI1_CFG:
 	.DB	ASCI1_BASE		; BASE PORT
 	.DW	ASCI1CFG		; LINE CONFIGURATION
 	.DW	ASCI1_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"ASCI: IO="
+	.ECHO	ASCI1_BASE
+#IF ((ASCIINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
-;
 ASCI_CFGCNT	.EQU	($ - ASCI_CFG) / ASCI_CFGSIZ
--- a/Source/HBIOS/ay38910.asm
+++ b/Source/HBIOS/ay38910.asm
@@ -19,12 +19,15 @@
 ;  VOLTAGE LEVEL OUTPUT ON A AY-3-8910 IS LOW AND AROUND 2V ON YM2149.
 ;
 AY_RCSND	.EQU	0		; 0 = EB MODULE, 1=MF MODULE
+;
+	.ECHO	"AY38910: MODE="
 ;
 #IF (AYMODE == AYMODE_SCG)
 AY_RSEL		.EQU	$9A
 AY_RDAT		.EQU	$9B
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$9C
+		.ECHO	"SCG"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_N8)
@@ -32,30 +35,35 @@ AY_RSEL		.EQU	$9C
 AY_RDAT		.EQU	$9D
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	N8_DEFACR
+		.ECHO	"N8"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ80)
 AY_RSEL		.EQU	$D8
 AY_RDAT		.EQU	$D0
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
+		.ECHO	"RCZ80"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ180)
 AY_RSEL		.EQU	$68
 AY_RDAT		.EQU	$60
 AY_RIN		.EQU	AY_RSEL+AY_RCSND
+		.ECHO	"RCZ180"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MSX)
 AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	$A2
+		.ECHO	"MSX"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_LINC)
 AY_RSEL		.EQU	$33
 AY_RDAT		.EQU	$32
 AY_RIN		.EQU	$32
+		.ECHO	"LINC"
 #ENDIF
 ;
 #IF (AYMODE == AYMODE_MBC)
@@ -63,7 +71,14 @@ AY_RSEL		.EQU	$A0
 AY_RDAT		.EQU	$A1
 AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	$A2
+		.ECHO	"MBC"
 #ENDIF
+;
+	.ECHO	", IO="
+	.ECHO	AY_RSEL
+	.ECHO	", CLOCK="
+	.ECHO	AY_CLK
+	.ECHO	" HZ\n"
 ;
 ;======================================================================
 ;
@@ -107,10 +122,6 @@ AY_NOISECNT	.EQU	1		; COUNT NUMBER OF NOISE CHANNELS
 ;#ELSE					; PRESCALE THE TONE PERIOD
 ;AY_SCALE	.EQU	3		; DATA TO MAINTAIN MAXIMUM
 ;#ENDIF					; RANGE AND ACCURACY
-;
-	.ECHO	"AY38910 CLOCK: "
-	.ECHO	AY_CLK
-	.ECHO	"\n"
 ;
 #INCLUDE "audio.inc"
 ;
--- a/Source/HBIOS/bqrtc.asm
+++ b/Source/HBIOS/bqrtc.asm
@@ -91,6 +91,10 @@ BQRTC_UTI	.EQU	%00001000

 BQRTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)

+		.ECHO	"BQRTC: IO="
+		.ECHO	BQRTC_BASE
+		.ECHO	"\n"
+
 ; RTC Device Initialization Entry

 BQRTC_INIT:
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -46,15 +46,15 @@ RTCIO		.EQU	$94		; RTC LATCH REGISTER ADR
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
+CTCBASE		.EQU	$60		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
 CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
+CTCOSC		.EQU	(7372800/8)	; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
@@ -88,6 +88,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -122,17 +123,18 @@ DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	TRUE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
 UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -140,18 +142,18 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACTCC	.EQU	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	(7372800/4)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCTCC	.EQU	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
@@ -229,14 +231,14 @@ SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0BASE		.EQU	$4E		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH0SDENABLE	.EQU	TRUE		; CH 0: ENABLE SD DISK
 CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
 CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
@@ -254,16 +256,16 @@ ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIO0BASE	.EQU	$68		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$6C		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.EQU	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 LPTMODE		.EQU	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
 LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
+LPT0BASE	.EQU	$48		; LPT 0: REGISTERS BASE ADR
 LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
 ;
 PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@@ -0,0 +1,330 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "MiniITX"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|EPITX]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR - TODO
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
+DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+; TODO - ADD PS/2 BITBANGER
+VDAEMU_SERKBD	.EQU	$00		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	2		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_EPFDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|EPITX]
+SDPPIBASE	.EQU	$40		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+SDTRACE		.EQU	2		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$BE		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -119,6 +119,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -166,6 +167,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -85,6 +85,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -125,6 +126,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -130,6 +131,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -92,6 +92,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -132,6 +133,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -96,6 +96,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -142,6 +143,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -130,6 +131,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -136,6 +137,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -85,6 +85,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -125,6 +126,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -90,6 +90,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -135,6 +136,7 @@ UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
 UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -88,6 +88,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -122,6 +123,7 @@ UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -28,7 +28,7 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
@@ -77,6 +77,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -112,6 +113,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -88,6 +88,7 @@ PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
 CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
@@ -123,6 +124,7 @@ UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
 UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
 UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
 UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
--- a/Source/HBIOS/ch.asm
+++ b/Source/HBIOS/ch.asm
@@ -18,9 +18,8 @@
 ;    added to the RESET routine when using CH376.
 ;
 ; TODO:
-;  - Implement auto-recovery on error status.
-;
-CHUSB_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;  - Implement auto-recovery on error status?
+;  - !!! Move CH_MODE to config variable !!!
 ;
 ; PORT OFFSETS FROM BASE PORT
 ;
@@ -33,6 +32,12 @@ CHTYP_NONE	.EQU	0		; NONE
 CHTYP_375	.EQU	1		; CH375
 CHTYP_376	.EQU	2		; CH376
 ;
+; CH MODE MANAGEMENT
+;
+CH_MODE_UNK	.EQU	0		; CURRENT MODE UNKNOWN
+CH_MODE_USB	.EQU	1		; CURRENT MODE = USB
+CH_MODE_SD	.EQU	2		; CURRENT MODE = SD
+;
 ; CH375/376 COMMANDS
 ;
 CH_CMD_VER	.EQU	$01		; GET IC VER
@@ -41,6 +46,7 @@ CH_CMD_EXIST	.EQU	$06		; CHECK EXISTS
 CH_CMD_MAXLUN	.EQU	$0A		; GET MAX LUN NUMBER
 CH_CMD_PKTSEC	.EQU	$0B		; SET PACKETS PER SECTOR
 CH_CMD_SETRETRY	.EQU	$0B		; SET RETRIES
+CH_CMD_FILESIZE	.EQU	$0C		; GET FILE SIZE (376)
 CH_CMD_MODE	.EQU	$15		; SET USB MODE
 CH_CMD_TSTCON	.EQU	$16		; TEST CONNECT
 CH_CMD_ABRTNAK	.EQU	$17		; ABORT DEVICE NAK RETRIES
@@ -49,7 +55,16 @@ CH_CMD_RD6	.EQU	$27		; READ USB DATA (375 & 376)
 CH_CMD_RD5	.EQU	$28		; READ USB DATA (375)
 CH_CMD_WR5	.EQU	$2B		; WRITE USB DATA (375)
 CH_CMD_WR6	.EQU	$2C		; WRITE USB DATA (376)
+CH_CMD_WRREQDAT	.EQU	$2D		; WRITE REQUESTED DATA (376)
+CH_CMD_SET_FN	.EQU	$2F		; SET FILENAME (376)
 CH_CMD_DSKMNT	.EQU	$31		; DISK MOUNT
+CH_CMD_FOPEN	.EQU	$32		; FILE OPEN (376)
+CH_CMD_FCREAT	.EQU	$34		; FILE CREATE (376)
+CH_CMD_BYTE_LOC	.EQU	$39		; BYTE LOCATE
+CH_CMD_BYTERD	.EQU	$3A		; BYTE READ
+CH_CMD_BYTERDGO	.EQU	$3B		; BYTE READ GO
+CH_CMD_BYTEWR	.EQU	$3C		; BYTE WRITE
+CH_CMD_BYTEWRGO	.EQU	$3D		; BYTE WRITE GO
 CH_CMD_DSKCAP	.EQU	$3E		; DISK CAPACITY
 CH_CMD_AUTOSET	.EQU	$4D		; USB AUTO SETUP
 CH_CMD_DSKINIT	.EQU	$51		; DISK INIT
@@ -87,6 +102,10 @@ CH_CFG0:	; DEVICE 0
 	.DW	CHUSB_CFG0		; USB SUB-DRIVER INIT ADR
 	.DB	CH0SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG0		; SD CARD SUB-DRIVER INIT ADR
+;
+	.ECHO	"CH: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -98,6 +117,10 @@ CH_CFG1:	; DEVICE 1
 	.DW	CHUSB_CFG1		; USB SUB-DRIVER INIT ADR
 	.DB	CH1SDENABLE		; ENABLE SD CARD SUB-DRIVER
 	.DW	CHSD_CFG1		; SD CARD SUB-DRIVER INIT ADR
+;
+	.ECHO	"CH: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - CH_CFGTBL) != (CHCNT * CH_CFGSIZ)
@@ -129,6 +152,8 @@ CH_INIT2:
 	LD	A,(IY+CH_IOBASE)	; GET IO BASE ADDRES
 	CALL	PRTHEXBYTE		; DISPLAY IT
 ;
+	XOR	A			; UNKNOWN MODE
+	LD	(CH_MODE),A		; SAVE IT
 	;CALL	CH_FLUSH		; FLUSH DEVICE OUTPUT QUEUE
 	CALL	CH_RESET		; FULL CH37X RESET
 	CALL	CH_DETECT		; DETECT CHIP PRESENCE
@@ -347,18 +372,63 @@ CH_GETVER:
 	CALL	CH_RD			; GET VERSION BYTE
 	RET				; DONE
 ;
+; SET MODE TO VALUE IN A
+; AVOID CHANGING MODES IF CURRENT MODE = NEW MODE
+; THE CH376 DOES NOT SEEM TO MAINTAIN SEPARATE OPERATING CONTEXTS FOR
+; THE USB AND SD DEVICES.  IF BOTH ARE IN OPERATION, THEN A MODE
+; SWITCH REQUIRES A COMPLETE REINITIALIZATION OF THE REQUESTED
+; DEVICE.
+;
+CH_SETMODE:
+	PUSH	BC			; SAVE BC
+	PUSH	DE			; SAVE DE
+	PUSH	HL			; SAVE HL
+	;PRTS("\r\nSETMODE:$")		; *DEBUG*
+	LD	L,A			; SAVE REQUESTED MODE
+	LD	A,(CH_MODE)		; GET CURRENT MODE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	L			; COMPARE
+	JR	Z,CH_SETMODE_Z		; IF EQUAL, DONE
+;
+	; NEED TO CHANGE MODES
+	LD	A,L			; GET REQUESTED MODE
+	CP	CH_MODE_USB		; USB?
+	JR	Z,CH_SETMODE_USB	; IF SO, DO IT
+	CP	CH_MODE_SD		; SD?
+	JR	Z,CH_SETMODE_SD		; IF SO, DO IT
+	OR	$FF			; SIGNAL ERROR
+	JR	CH_SETMODE_Z		; BAIL OUT
+;
+CH_SETMODE_USB:
+	CALL	CHUSB_RESET		; FULL USB STACK RESET
+	JR	CH_SETMODE_Z		; MOVE ON
+;
+CH_SETMODE_SD:
+	CALL	CHSD_RESET		; FULL SD STACK RESET
+	JR	CH_SETMODE_Z		; MOVE ON
+;
+CH_SETMODE_Z:
+	POP	HL			; RECOVER HL
+	POP	DE			; RECOVER DE
+	POP	BC			; RECOVER BC
+	RET				; DONE
 ;
 ;
-CH_STR_NOHW		.TEXT	" NOT PRESENT$"
-CH_STR_UPGRADE		.TEXT	" !!!UPGRADE REQUIRED!!!$"
 ;
-CH_STR_375		.TEXT	"CH375$"
-CH_STR_376		.TEXT	"CH376$"
+CH_MODE		.DB	CH_MODE_UNK
+;
+CH_STR_NOHW	.TEXT	" NOT PRESENT$"
+;
+CH_STR_375	.TEXT	"CH375$"
+CH_STR_376	.TEXT	"CH376$"
 ;
 ;==================================================================================================
 ; CH375/376 USB SUB-DRIVER
 ;==================================================================================================
 ;
+CHUSB_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;
 ; CHUSB DEVICE STATUS
 ;
 CHUSB_STOK	.EQU	0
@@ -368,7 +438,7 @@ CHUSB_STIOERR	.EQU	-3
 CHUSB_STTO	.EQU	-4
 CHUSB_STNOTSUP	.EQU	-5
 ;
-; CH DEVICE CONFIGURATION
+; CHUSB DEVICE CONFIGURATION
 ;
 CHUSB_CFGSIZ	.EQU	12		; SIZE OF USB CFG TBL ENTRIES
 ;
@@ -389,6 +459,12 @@ CHUSB_CFG0:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH0USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -399,6 +475,12 @@ CHUSB_CFG1:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH1USBENABLE)
+	.ECHO	"CHUSB: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF ($ - CHUSB_CFGTBL) != (CHCNT * CHUSB_CFGSIZ)
@@ -481,6 +563,10 @@ CHUSB_DEFMED:
 ;
 ;
 CHUSB_READ:
+	LD	A,CH_MODE_USB		; REQUEST USB MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHUSB_CMDERR		; HANDLE ERROR
+;
 	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
 	LD	(CHUSB_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
 	LD	A,CH_CMD_DSKRD		; DISK READ COMMAND
@@ -542,6 +628,10 @@ CHUSB_READ2:
 ;
 ;
 CHUSB_WRITE:
+	LD	A,CH_MODE_USB		; REQUEST USB MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHUSB_CMDERR		; HANDLE ERROR
+;
 	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
 	LD	(CHUSB_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
 	LD	A,CH_CMD_DSKWR		; DISK READ COMMAND
@@ -631,7 +721,7 @@ CHUSB_STATUS:
 ; RESET THE INTERFACE AND REDISCOVER MEDIA
 ;
 CHUSB_RESET:
-	;PRTS("\n\rRESET:$")		; *DEBUG*
+	;PRTS("\n\rRES USB:$")		; *DEBUG*
 	;CALL	CH_FLUSH		; DISCARD ANY GARBAGE
 	;CALL	CH_RESET		; FULL CH37X RESET
 ;
@@ -656,6 +746,9 @@ CHUSB_RESET:
 	;CALL	PC_SPACE		; *DEBUG*
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	CALL	CH_NAP			; SMALL WAIT
+;
+	LD	A,CH_MODE_USB		; WE ARE NOW IN USB MODE
+	LD	(CH_MODE),A		; SAVE IT
 ;
 	; INITIALIZE DISK
 	LD	B,24			; TRY A FEW TIMES
@@ -671,29 +764,28 @@ CHUSB_RESET1:
 	;CALL	PC_SPACE		; *DEBUG*
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	CP	$14			; SUCCESS?
-	JR	Z,CHUSB_RESET2		; IF SO, CONTINUE
-	;JR	Z,CHUSB_RESET1A		; IF SO, CHECK READY
+	JR	Z,CHUSB_RESET1A		; IF SO, CHECK READY
 	CP	$16			; NO MEDIA
 	JP	Z,CHUSB_NOMEDIA		; HANDLE IT
 	CALL	CH_NAP			; SMALL DELAY
 	DJNZ	CHUSB_RESET1		; LOOP AS NEEDED
 	JP	CHUSB_TO		; HANDLE TIMEOUT
-;;;;
-;;;CHUSB_RESET1A:
-;;;	CALL	CHUSB_DSKRES		; DISK RESET
-;;;	CP	$14			; GOOD?
-;;;	JR	Z,CHUSB_RESET2
-;;;	CALL	CHUSB_DSKRDY		; CHECK IF DISK READY
-;;;	CP	$14			; GOOD?
-;;;	JR	Z,CHUSB_RESET2		; IF SO, MOVE ON
-;;;	DJNZ	CHUSB_RESET1		; KEEP TRYING
+;
+CHUSB_RESET1A:
+	;CALL	CHUSB_DSKRES		; DISK RESET
+	;CP	$14			; GOOD?
+	;JR	Z,CHUSB_RESET2
+	;CALL	CHUSB_DSKRDY		; CHECK IF DISK READY
+	;CP	$14			; GOOD?
+	;JR	Z,CHUSB_RESET2		; IF SO, MOVE ON
+	;DJNZ	CHUSB_RESET1		; KEEP TRYING
 ;
 CHUSB_RESET2:
 	; USE OF CH376 DISK_MOUNT COMMAND SEEMS TO IMPROVE
 	; COMPATIBILITY WITH SOME OLDER USB THUMBDRIVES.
 	LD	A,(IY+CH_TYPE)		; CH37X TYPE?
 	CP	CHTYP_376		; IS CH376?
-	CALL	Z,CHUSB_DSKMNT		; IF SO, ISSUE MOUNT
+	CALL	Z,CHUSB_DSKMNT		; IF SO, TRY MOUNT, IGNORE ERRS
 	;CALL	CHUSB_AUTOSET		; *DEBUG*
 	;CALL	CHUSB_TSTCON		; *DEBUG*
 	;CALL	CHUSB_MAXLUN		; *DEBUG*
@@ -714,7 +806,7 @@ CHUSB_RESET2:
 CHUSB_DEVICE:
 	LD	D,DIODEV_CHUSB		; D := DEVICE TYPE
 	LD	E,(IY+CH_DEV)		; E := PHYSICAL DEVICE NUMBER
-	LD	C,%01110011		; USB HARD DISK ATTRIBUTES
+	LD	C,%00110011		; USB HARD DISK ATTRIBUTES
 	LD	H,(IY+CH_TYPE)		; H := MODE
 	LD	L,(IY+CH_IOBASE)	; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
@@ -791,28 +883,34 @@ CHUSB_DSKMNT:
 	;CALL	PRTHEXBYTE		; *DEBUG*
 	CP	$14			; SUCCESS?
 	RET	NZ			; ABORT IF NOT
+;
+#IF FALSE
 	CALL	CH_CMD_RD		; SEND READ COMMAND
 	CALL	CH_RD			; GET LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	LD	B,A			; LOOP COUNTER
 	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
-DSKMNT1:
+CHUSB_DSKMNT1:
 	CALL	CH_RD			; GET A BYTE
 	LD	(HL),A			; SAVE IT
 	INC	HL			; BUMP BUF PTR
-	DJNZ	DSKMNT1			; LOOP FOR ALL DATA
+	DJNZ	CHUSB_DSKMNT1		; LOOP FOR ALL DATA
 ;
 	;LD	DE,HB_WRKBUF		; *DEBUG*
 	;CALL	DUMP_BUFFER		; *DEBUG*
 ;
-	;CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
-	;LD	HL,HB_WRKBUF + 8
-	;LD	B,28
-DSKMNT2:
-	;LD	A,(HL)
-	;INC	HL
-	;CALL	COUT
-	;DJNZ	DSKMNT2
+	CALL	CHUSB_PRTPREFIX		; PRINT DEVICE PREFIX
+	LD	HL,HB_WRKBUF + 8
+	LD	B,28
+CHUSB_DSKMNT2:
+	LD	A,(HL)
+	INC	HL
+	CALL	COUT
+	DJNZ	CHUSB_DSKMNT2
+#ENDIF
 ;
+	XOR	A
 	RET
 ;
 ; PERFORM DISK SIZE
@@ -1081,17 +1179,30 @@ CHUSB_STR_ST_MAP:
 CHUSB_STR_STOK		.TEXT	"OK$"
 CHUSB_STR_STNOMEDIA	.TEXT	"NO MEDIA$"
 CHUSB_STR_STCMDERR	.TEXT	"COMMAND ERROR$"
-CHUSB_STR_STIOERR		.TEXT	"IO ERROR$"
+CHUSB_STR_STIOERR	.TEXT	"IO ERROR$"
 CHUSB_STR_STTO		.TEXT	"TIMEOUT$"
 CHUSB_STR_STNOTSUP	.TEXT	"NOT SUPPORTED$"
 CHUSB_STR_STUNK		.TEXT	"UNKNOWN ERROR$"
-
 ;
 ;==================================================================================================
 ; CH375/376 SD CARD SUB-DRIVER
 ;==================================================================================================
 ;
-; CH DEVICE CONFIGURATION
+#DEFINE	CHSD_IMGFILE "DISK.IMG"
+;
+CHSD_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+;
+; CHUSB DEVICE STATUS
+;
+CHSD_STOK	.EQU	0
+CHSD_STNOMEDIA	.EQU	-1
+CHSD_STCMDERR	.EQU	-2
+CHSD_STIOERR	.EQU	-3
+CHSD_STTO	.EQU	-4
+CHSD_STNOTSUP	.EQU	-5
+CHSD_STNOFILE	.EQU	-6
+;
+; CHSD DEVICE CONFIGURATION
 ;
 CHSD_CFGSIZ	.EQU	12		; SIZE OF USB CFG TBL ENTRIES
 ;
@@ -1112,6 +1223,12 @@ CHSD_CFG0:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH0SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH0BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF (CHCNT >= 2)
@@ -1122,6 +1239,12 @@ CHSD_CFG1:
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+  #IF (CH1SDENABLE)
+	.ECHO	"CHSD: IO="
+	.ECHO	CH1BASE
+	.ECHO	"\n"
+  #ENDIF
 #ENDIF
 ;
 #IF ($ - CHSD_CFGTBL) != (CHCNT * CHSD_CFGSIZ)
@@ -1144,36 +1267,581 @@ CHSD_INIT:
 	INC	A			; BUMP TO NEXT UNIT NUM TO ASSIGN
 	LD	(CHSD_DEVNUM),A		; SAVE IT
 ;
-	CALL	NEWLINE			; FORMATTING
-	PRTS("CHSD$")			; LABEL FOR IO ADDRESS
-	LD	A,(IY+CH_DEV)		; GET DEVICE NUM
-	CALL	PRTDECB			; PRINT IT
-	CALL	PC_COLON		; FORMATTING
+	; ADD UNIT TO GLOBAL DISK UNIT TABLE
+	LD	BC,CHSD_FNTBL		; BC := FUNC TABLE ADR
+	PUSH	IY			; CFG ENTRY POINTER
+	POP	DE			; COPY TO DE
+	CALL	DIO_ADDENT		; ADD ENTRY TO GLOBAL DISK DEV TABLE
 ;
+	CALL	CHSD_RESET		; RESET & DISCOVER MEDIA
+#IF (CHSDTRACE <= 1)
+	CALL	NZ,CHSD_PRTSTAT
+#ENDIF
+	RET	NZ			; ABORT ON FAILURE
+;
+	; START PRINTING DEVICE INFO
+	CALL	CHSD_PRTPREFIX		; PRINT DEVICE PREFIX
+;
+	; PRINT STORAGE CAPACITY (BLOCK COUNT)
+	PRTS(" BLOCKS=0x$")		; PRINT FIELD LABEL
+	LD	A,CHSD_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CAPACITY VALUE
+	CALL	PRTHEX32		; PRINT HEX VALUE
+;
+	; PRINT STORAGE SIZE IN MB
+	PRTS(" SIZE=$")			; PRINT FIELD LABEL
+	LD	B,11			; 11 BIT SHIFT TO CONVERT BLOCKS --> MB
+	CALL	SRL32			; RIGHT SHIFT
+	CALL	PRTDEC32		; PRINT DWORD IN DECIMAL
+	PRTS("MB$")			; PRINT SUFFIX
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+CHSD_FNTBL:
+	.DW	CHSD_STATUS
+	.DW	CHSD_RESET
+	.DW	CHSD_SEEK
+	.DW	CHSD_READ
+	.DW	CHSD_WRITE
+	.DW	CHSD_VERIFY
+	.DW	CHSD_FORMAT
+	.DW	CHSD_DEVICE
+	.DW	CHSD_MEDIA
+	.DW	CHSD_DEFMED
+	.DW	CHSD_CAP
+	.DW	CHSD_GEOM
+#IF (($ - CHSD_FNTBL) != (DIO_FNCNT * 2))
+	.ECHO	"*** INVALID CHSD FUNCTION TABLE ***\n"
+#ENDIF
+;
+CHSD_VERIFY:
+CHSD_FORMAT:
+CHSD_DEFMED:
+	SYSCHKERR(ERR_NOTIMPL)		; NOT IMPLEMENTED
+	RET
+;
+;
+;
+CHSD_READ:
+	LD	A,CH_MODE_SD		; REQUEST SD MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
+	LD	(CHSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	CALL	CHSD_RWSTART		; SET LBA OFFSET
+	RET	NZ
+;
+	;PRTS("\n\rREAD:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTERD		; BYTE READ
+	CALL	CH_CMD			; SEND COMMAND
+	CALL	CH_NAP
+	LD	A,0			; LSB
+	CALL	CH_WR			; SEND IT
+	LD	A,2			; MSB
+	CALL	CH_WR			; SEND IT
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1D			; DATA READY TO READ?
+	JP	NZ,CHSD_IOERR		; HANDLE I/O ERROR
+;
+	LD	HL,(CHSD_DSKBUF)
+CHSD_READ1:
+	CALL	CH_CMD_RD		; SEND READ USB DATA CMD
+	CALL	CH_RD			; GET DATA LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+#IF (CHSD_FASTIO)
+	LD	B,A			; BYTE COUNT TO READ
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	INIR				; DO IT FAST
+#ELSE
+	LD	B,A			; SAVE IT
+CHSD_READ2:
+	CALL	CH_RD			; GET DATA BYTE
+	LD	(HL),A			; SAVE IN BUFFER
+	INC	HL			; INC BUF PTR
+	DJNZ	CHSD_READ2		; LOOP TILL DONE W/ ALL BYTES
+#ENDIF
+;
+	LD	A,CH_CMD_BYTERDGO	; BYTE READ GO COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1D			; MORE?
+	JR	Z,CHSD_READ1		; IF SO, GET MORE
+	CP	$14			; GOOD FINISH?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHSD_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+CHSD_WRITE:
+	LD	A,CH_MODE_SD		; REQUEST SD MODE
+	CALL	CH_SETMODE		; DO IT
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
+	LD	(CHSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
+	CALL	CHSD_RWSTART		; SET LBA OFFSET'
+	RET	NZ
+;
+	;PRTS("\n\rWRITE:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTEWR		; BYTE WRITE
+	CALL	CH_CMD			; SEND COMMAND
+	LD	A,0			; LSB
+	CALL	CH_WR			; SEND IT
+	LD	A,2			; MSB
+	CALL	CH_WR			; SEND IT
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1E			; DATA READY TO GO?
+	JP	NZ,CHSD_IOERR		; HANDLE I/O ERROR
+;
+	LD	HL,(CHSD_DSKBUF)
+CHSD_WRITE1:
+	LD	A,CH_CMD_WRREQDAT	; WRITE REQUESTED DATA CMD
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_RD			; GET DATA LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+#IF (CHSD_FASTIO)
+	LD	B,A			; BYTE COUNT TO WRITE
+	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	OTIR				; DO IT FAST
+#ELSE
+	LD	B,A			; SAVE IT
+CHSD_WRITE2:
+	CALL	CH_WR			; WRITE DATA BYTE
+	LD	(HL),A			; SAVE IN BUFFER
+	INC	HL			; INC BUF PTR
+	DJNZ	CHSD_WRITE2		; LOOP TILL DONE W/ ALL BYTES
+#ENDIF
+;
+	LD	A,CH_CMD_BYTEWRGO	; BYTE WRITE GO COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	CALL	CH_POLL			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$1E			; MORE?
+	JR	Z,CHSD_WRITE1		; IF SO, SEND MORE
+	CP	$14			; GOOD FINISH?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+;
+	; INCREMENT LBA
+	PUSH	HL			; SAVE HL
+	LD	A,CHSD_LBA		; LBA OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+	POP	HL			; RESTORE HL
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; SEEK TO CURRENT LBA
+;
+CHSD_RWSTART:
+	;PRTS("\n\rRWST:$")		; *DEBUG*
+	LD	A,CH_CMD_BYTE_LOC	; BYTE LOCATE COMMAND (SEEK)
+	CALL	CH_CMD			; SEND IT
+;
+	; GET CURRENT LBA OFFSET
+	LD	A,CHSD_LBA		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; OFFSET = DE:HL
+;
+	; CONVERT OFFSET FROM LBA TO BYTE
+	LD	B,9
+CHSD_RWSTART1:
+	SLA	L
+	RL	H
+	RL	E
+	RL	D
+	DJNZ	CHSD_RWSTART1
+	;CALL	PRTHEX32		; *DEBUG*
+;
+	; SEND THE BYTE OFFSET (LSB FIRST)
+	LD	A,L
+	CALL	CH_WR
+	LD	A,H
+	CALL	CH_WR
+	LD	A,E
+	CALL	CH_WR
+	LD	A,D
+	CALL	CH_WR
+;
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$14			; CHECK RESULT
+	JP	NZ,CHUSB_CMDERR		; HANDLE CMD ERROR
+;
+	XOR	A
+	RET
+;
+;
+;
+CHSD_STATUS:
+	; RETURN UNIT STATUS
+	LD	A,(IY+CHSD_STAT)	; GET STATUS OF SELECTED DEVICE
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+; RESET THE INTERFACE AND REDISCOVER MEDIA
+;
+CHSD_RESET:
+	;PRTS("\n\rRES SD:$")		; *DEBUG*
+;
+	; ACTIVATE SD MODE
+	LD	A,CH_CMD_MODE		; SET MODE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,3			; SD MODE
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP			; SMALL WAIT
+	CALL	CH_RD			; GET RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CALL	CH_NAP			; SMALL WAIT
+;
+	LD	A,CH_MODE_SD		; WE ARE NOW IN SD MODE
+	LD	(CH_MODE),A		; SAVE IT
+;
+	CALL	CHSD_DSKMNT		; MOUNT DISK
+	RET	NZ
+;
+	; OPEN DISK IMAGE FILE
+	LD	DE,CHSD_FNAME
+	CALL	CHSD_FOPEN
+	RET	NZ
+;
+	; GET FILESIZE
+	CALL	CHSD_FILESIZE
+	RET	NZ
+;
+	; SET STATUS AND RETURN
+	XOR	A			; CLEAR STATUS
+	LD	(IY+CHSD_STAT),A	; RECORD STATUS
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_DEVICE:
+	LD	D,DIODEV_CHSD		; D := DEVICE TYPE
+	LD	E,(IY+CH_DEV)		; E := PHYSICAL DEVICE NUMBER
+	LD	C,%00110010		; SD HARD DISK ATTRIBUTES
+	LD	H,(IY+CH_TYPE)		; H := MODE
+	LD	L,(IY+CH_IOBASE)	; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; CHSD_GETMED
+;
+CHSD_MEDIA:
+	LD	A,E			; GET FLAGS
+	OR	A			; SET FLAGS
+	JR	Z,CHSD_MEDIA1		; JUST REPORT CURRENT STATUS AND MEDIA
+	CALL	CHSD_RESET		; RESET CHSD INTERFACE
+;
+CHSD_MEDIA1:
+	LD	A,(IY+CHSD_STAT)	; GET STATUS
+	OR	A			; SET FLAGS
+	LD	D,0			; NO MEDIA CHANGE DETECTED
+	LD	E,MID_HD		; ASSUME WE ARE OK
+	RET	Z			; RETURN IF GOOD INIT
+	LD	E,MID_NONE		; SIGNAL NO MEDIA
+	LD	A,ERR_NOMEDIA		; NO MEDIA ERROR
+	OR	A			; SET FLAGS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_SEEK:
+	BIT	7,D			; CHECK FOR LBA FLAG
+	CALL	Z,HB_CHS2LBA		; CLEAR MEANS CHS, CONVERT TO LBA
+	RES	7,D			; CLEAR FLAG REGARDLESS (DOES NO HARM IF ALREADY LBA)
+	LD	(IY+CHSD_LBA+0),L	; SAVE NEW LBA
+	LD	(IY+CHSD_LBA+1),H	; ...
+	LD	(IY+CHSD_LBA+2),E	; ...
+	LD	(IY+CHSD_LBA+3),D	; ...
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+;
+;
+CHSD_CAP:
+	LD	A,(IY+CHSD_STAT)	; GET STATUS
+	PUSH	AF			; SAVE IT
+	LD	A,CHSD_MEDCAP		; OFFSET TO CAPACITY FIELD
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	LD32			; GET THE CURRENT CAPACITY INTO DE:HL
+	LD	BC,512			; 512 BYTES PER BLOCK
+	POP	AF			; RECOVER STATUS
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHSD_GEOM:
+	; FOR LBA, WE SIMULATE CHS ACCESS USING 16 HEADS AND 16 SECTORS
+	; RETURN HS:CC -> DE:HL, SET HIGH BIT OF D TO INDICATE LBA CAPABLE
+	CALL	CHSD_CAP		; GET TOTAL BLOCKS IN DE:HL, BLOCK SIZE TO BC
+	LD	L,H			; DIVIDE BY 256 FOR # TRACKS
+	LD	H,E			; ... HIGH BYTE DISCARDED, RESULT IN HL
+	LD	D,16 | $80		; HEADS / CYL = 16, SET LBA CAPABILITY BIT
+	LD	E,16			; SECTORS / TRACK = 16
+	RET				; DONE, A STILL HAS CHSD_CAP STATUS
+;
+; CH37X HELPER ROUTINES
+;
+;
+; PERFORM DISK MOUNT
+;
+CHSD_DSKMNT:
+	;PRTS("\n\rMOUNT:$")		; *DEBUG*
+	LD	A,CH_CMD_DSKMNT		; DISK QUERY
+	CALL	CH_CMD			; DO IT
+	CALL	CH_POLL			; WAIT FOR RESPONSE
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$82			; NO DISK?
+	JP	Z,CHSD_NOMEDIA		; HANDLE NO MEDIA ERROR
+	CP	$14			; SUCCESS?
+	JP	NZ,CHSD_CMDERR		; HANDLE ERROR
+;
+#IF FALSE
+	CALL	CH_CMD_RD		; SEND READ COMMAND
+	CALL	CH_RD			; GET LENGTH
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	B,A			; LOOP COUNTER
+	LD	HL,HB_WRKBUF		; USE WORK BUFFER FOR DATA
+CHSD_DSKMNT1:
+	CALL	CH_RD			; GET A BYTE
+	LD	(HL),A			; SAVE IT
+	INC	HL			; BUMP BUF PTR
+	DJNZ	CHSD_DSKMNT1		; LOOP FOR ALL DATA
+;
+	;LD	DE,HB_WRKBUF		; *DEBUG*
+	;CALL	DUMP_BUFFER		; *DEBUG*
+;
+	CALL	CHSD_PRTPREFIX		; PRINT DEVICE PREFIX
+	LD	HL,HB_WRKBUF + 8
+	LD	B,28
+CHSD_DSKMNT2:
+	LD	A,(HL)
+	INC	HL
+	CALL	COUT
+	DJNZ	CHSD_DSKMNT2
+#ENDIF
+;
+	XOR	A
+	RET
+;
+; SET FILE NAME
+;
+CHSD_SETFNAME:
+	;PRTS("\n\rSETFNAME:$")		; *DEBUG*
+	LD	A,CH_CMD_SET_FN		; SET FILE NAME COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_NAP
+	;CALL	DELAY			; MAY NOT BE NEEDED
+	;CALL	PC_SPACE		; *DEBUG*
+CHSD_SETFNAME1:
+	;CALL	DELAY
+	LD	A,(DE)			; GET NEXT BYTE
+	INC	DE			; BUMP POINTER
+	CALL	CH_WR			; SEND IT
+	;CALL	COUT			; *DEBUG*
+	OR	A			; CHECK FOR NUL (EOS)
+	RET	Z			; IF NUL, DONE
+	JR	CHSD_SETFNAME1		; SEND MORE CHARACTERS
+;
+; OPEN FILE
+;
+CHSD_FOPEN:
+	CALL	CHSD_SETFNAME
+	;PRTS("\n\rFOPEN:$")		; *DEBUG*
+	LD	A,CH_CMD_FOPEN		; FILE OPEN  COMMAND
+	CALL	CH_CMD			; SEND IT
+	CALL	CH_POLL			; WAIT FOR RESULT
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	CP	$42			; MISSING FILE?
+	JP	Z,CHSD_NOFILE		; HANDLE ERROR
+	CP	$14			; SUCCESS?
+	JP	NZ,CHSD_IOERR		; HANDLE ERROR
+	RET				; RETURN WITH ZF SET APPROPRIATELY
+;
+; GET FILE SIZE
+;
+CHSD_FILESIZE:
+	;PRTS("\n\rFSIZE:$")
+	LD	A,CH_CMD_FILESIZE	; FILE SIZE COMMAND
+	CALL	CH_CMD			; SEND IT
+	LD	A,$68			; REQUIRED CMD PARAMETER
+	CALL	CH_WR			; SEND IT
+	CALL	CH_NAP
+	LD	A,CHSD_MEDCAP		; MEDIA CAPACITY OFFSET
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	PUSH	HL			; SAVE ADDRESS
+	CALL	CH_RD
+	LD	L,A
+	CALL	CH_RD
+	LD	H,A
+	CALL	CH_RD
+	LD	E,A
+	CALL	CH_RD
+	LD	D,A
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEX32		; *DEBUG*
+	LD	B,9			; ROTATE 9 BITS FOR DIV 512
+CHSD_FILESIZE1:
+	SRL	D
+	RR	E
+	RR	H
+	RR	L
+	DJNZ	CHSD_FILESIZE1		; LOOP TILL DONE
+	POP	BC			; RECOVER ADDRESS TO BC
+	;CALL	PC_SPACE		; *DEBUG*
+	;CALL	PRTHEX32		; *DEBUG*
+	CALL	ST32			; STORE IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
+;
+; ERROR HANDLERS
+;
+;
+CHSD_NOFILE:
+	LD	A,CHSD_STNOFILE
+	JR	CHSD_ERR
+;
+CHSD_NOMEDIA:
+	LD	A,CHSD_STNOMEDIA
+	JR	CHSD_ERR
+;
+CHSD_CMDERR:
+	LD	A,CHSD_STCMDERR
+	JR	CHSD_ERR
+;
+CHSD_IOERR:
+	LD	A,CHSD_STIOERR
+	JR	CHSD_ERR
+;
+CHSD_TO:
+	LD	A,CHSD_STTO
+	JR	CHSD_ERR
+;
+CHSD_NOTSUP:
+	LD	A,CHSD_STNOTSUP
+	JR	CHSD_ERR
+;
+CHSD_ERR:
+	LD	(IY+CHSD_STAT),A	; SAVE NEW STATUS
+;
+CHSD_ERR2:
+#IF (CHSDTRACE >= 2)
+	CALL	CHSD_PRTSTAT
+#ENDIF
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+CHSD_PRTERR:
+	RET	Z			; DONE IF NO ERRORS
+	; FALL THRU TO CHSD_PRTSTAT
+;
+; PRINT FULL DEVICE STATUS LINE
+;
+CHSD_PRTSTAT:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHSD_STAT)
+	CALL	CHSD_PRTPREFIX		; PRINT UNIT PREFIX
+	CALL	PC_SPACE		; FORMATTING
+	CALL	CHSD_PRTSTATSTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT STATUS STRING
+;
+CHSD_PRTSTATSTR:
+	PUSH	AF
+	PUSH	DE
+	PUSH	HL
+	LD	A,(IY+CHSD_STAT)
+	NEG
+	LD	HL,CHSD_STR_ST_MAP
+	ADD	A,A
+	CALL	ADDHLA
+	LD	E,(HL)
+	INC	HL
+	LD	D,(HL)
+	CALL	WRITESTR
+	POP	HL
+	POP	DE
+	POP	AF
+	RET
+;
+; PRINT DIAGNONSTIC PREFIX
+;
+CHSD_PRTPREFIX:
+	PUSH	AF
+	CALL	NEWLINE
+	PRTS("CHSD$")
+	LD	A,(IY+CH_DEV)		; GET CURRENT DEVICE NUM
+	CALL	PRTDECB
+	CALL	PC_COLON
+	POP	AF
 	RET
-
-
-CHSD_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
-
-
-
-
-
 ;
-;=============================================================================
 ; DATA STORAGE
-;=============================================================================
 ;
-CH_FWVER		.DW	0,0	; MMNNBBB (M=MAJOR, N=MINOR, B=BUILD)
+CHSD_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
+CHSD_DSKBUF	.DW	0
 ;
-CHSD_IOFNADR		.DW	0	; PENDING IO FUNCTION ADDRESS
+CHSD_FNAME	.DB	"/", CHSD_IMGFILE, 0
 ;
-CHSD_DSKBUF		.DW	0
+CHSD_STR_ST_MAP:
+	.DW		CHSD_STR_STOK
+	.DW		CHSD_STR_STNOMEDIA
+	.DW		CHSD_STR_STCMDERR
+	.DW		CHSD_STR_STIOERR
+	.DW		CHSD_STR_STTO
+	.DW		CHSD_STR_STNOTSUP
+	.DW		CHSD_STR_STNOFILE
 ;
-CHSD_DSKSTAT		.DB	0
-CHSD_ERRCODE		.DW	0,0
-CHSD_CSDBUF		.FILL	16,0
-;
-CHSD_CMD		.DB	0
-;
-CHSD_TIMEOUT		.DW	$0000	; FIX: MAKE THIS CPU SPEED RELATIVE
+CHSD_STR_STOK		.TEXT	"OK$"
+CHSD_STR_STNOMEDIA	.TEXT	"NO MEDIA$"
+CHSD_STR_STCMDERR	.TEXT	"COMMAND ERROR$"
+CHSD_STR_STIOERR	.TEXT	"IO ERROR$"
+CHSD_STR_STTO		.TEXT	"TIMEOUT$"
+CHSD_STR_STNOTSUP	.TEXT	"NOT SUPPORTED$"
+CHSD_STR_STNOFILE	.TEXT	"MISSING "
+			.TEXT	CHSD_IMGFILE
+			.TEXT	" FILE$"
+CHSD_STR_STUNK		.TEXT	"UNKNOWN ERROR$"
--- a/Source/HBIOS/ctc.asm
+++ b/Source/HBIOS/ctc.asm
@@ -28,6 +28,8 @@ CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
 #IF (CTCTIMER & (INTMODE != 2))
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
+	.ECHO	"CTC: IO="
+	.ECHO	CTCBASE
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 ;
@@ -109,13 +111,24 @@ CTC_DIV		.EQU	CTCOSC / CTC_PRESCL / TICKFREQ
 CTC_DIVHI	.EQU	CTCPRE
 CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 ;
-	.ECHO "CTC DIVISOR: "
+
+	.ECHO	", TIMER MODE="
+  #IF (CTCMODE == CTCMODE_CTR)
+		.ECHO	"COUNTER"
+  #ENDIF
+  #IF (CTCMODE == CTCMODE_TIM16)
+		.ECHO	"TIMER/16"
+  #ENDIF
+  #IF (CTCMODE == CTCMODE_TIM256)
+		.ECHO	"TIMER/256"
+  #ENDIF
+	.ECHO ", DIVISOR="
 	.ECHO CTC_DIV
-	.ECHO ", HI: "
+	.ECHO ", HI="
 	.ECHO CTC_DIVHI
-	.ECHO ", LO: "
+	.ECHO ", LO="
 	.ECHO CTC_DIVLO
-	.ECHO "\n"
+	.ECHO ", INTERRUPTS ENABLED"
 ;
  #IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF))
 	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
@@ -134,6 +147,8 @@ CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;
 #ENDIF
+;
+	.ECHO "\n"
 ;
 ;==================================================================================================
 ; CTC PRE-INITIALIZATION
--- a/Source/HBIOS/cvdu.asm
+++ b/Source/HBIOS/cvdu.asm
@@ -17,6 +17,8 @@
 ;======================================================================
 ;
 CVDU_BASE	.EQU	$E0
+;
+		.ECHO	"CVDU: MODE="
 ;
 #IF (CVDUMODE == CVDUMODE_ECB)
 CVDU_KBDDATA	.EQU	CVDU_BASE + $02	; KBD CTLR DATA PORT
@@ -24,6 +26,7 @@ CVDU_KBDST	.EQU	CVDU_BASE + $0A	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $0C	; READ/WRITE M8563 DATA
+		.ECHO	"ECB"
 #ENDIF
 ;
 #IF (CVDUMODE == CVDUMODE_MBC)
@@ -32,7 +35,15 @@ CVDU_KBDST	.EQU	CVDU_BASE + $03	; KBD CTLR STATUS/CMD PORT
 CVDU_STAT	.EQU	CVDU_BASE + $04	; READ M8563 STATUS
 CVDU_REG	.EQU	CVDU_BASE + $04	; SELECT M8563 REGISTER
 CVDU_DATA	.EQU	CVDU_BASE + $05	; READ/WRITE M8563 DATA
+		.ECHO	"MBC"
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	CVDU_BASE
+		.ECHO	", KBD MODE=PS/2"
+		.ECHO	", KBD IO="
+		.ECHO	CVDU_KBDDATA
+		.ECHO	"\n"
 ;
 CVDU_ROWS	.EQU	25
 CVDU_COLS	.EQU	80
--- a/Source/HBIOS/dma.asm
+++ b/Source/HBIOS/dma.asm
@@ -2,17 +2,31 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+;
+	.ECHO	"DMA: MODE="
+;
 #IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 1
 DMA_USEHALF	.EQU	TRUE
+  #IF (DMAMODE == DMAMODE_ECB)
+	.ECHO	"ECB"
+  #ENDIF
+  #IF (DMAMODE == DMAMODE_MBC)
+	.ECHO	"MBC"
+  #ENDIF
 #ENDIF
 ;
 #IF (DMAMODE == DMAMODE_DUO)
 DMA_IO		.EQU	DMABASE
 DMA_CTL		.EQU	DMABASE + 3
 DMA_USEHALF	.EQU	FALSE
+	.ECHO	"DUO"
 #ENDIF
+;S
+	.ECHO	", IO="
+	.ECHO	DMA_IO
+	.ECHO	"\n"
 ;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
--- a/Source/HBIOS/ds1501rtc.asm
+++ b/Source/HBIOS/ds1501rtc.asm
@@ -111,6 +111,12 @@ DS1501RTC_TE	.EQU	%10000000

 DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)

+	.ECHO	"DS1501RTC: RTCIO="
+	.ECHO	DS1501RTC_BASE
+	.ECHO	", NVMIO="
+	.ECHO	DS1501NVM_BASE
+	.ECHO	"\n"
+
 ; RTC Device Initialization Entry

 DS1501RTC_INIT:
--- a/Source/HBIOS/ds7rtc.asm
+++ b/Source/HBIOS/ds7rtc.asm
@@ -22,6 +22,8 @@ DS7_READ   	.EQU    (DS7_DS1307 | DS7_R)	; READ
 DS7_WRITE 	.EQU    (DS7_DS1307 | DS7_W)	; WRITE
 ;
 DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
+;
+		.ECHO	"DS1307: ENABLED\n"
 ;
 ;-----------------------------------------------------------------------------
 ; DS1307 INITIALIZATION
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@@ -88,6 +88,8 @@
 ; D2	--	--	--	--	--	--	--	--	--		--	--
 ; D1	----	--	--	--	--	--	--	--	--		CLKSEL	--
 ; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
+;
+	.ECHO	"DSRTC: MODE="
 ;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
@@ -113,6 +115,8 @@ DS1d8k		.EQU	%10100111	; 1 DOIDE 8K RESISTOR
 DS2d2k		.EQU	%10101001	; 2 DIODES 2K RESISTOR
 DS2d4k		.EQU	%10101010	; 2 DIODES 4K RESISTOR
 DS2d8k		.EQU	%10101011	; 2 DIODES 8K RESISTOR
+;
+		.ECHO	"STD"
 ;
 #ENDIF
 ;
@@ -129,8 +133,14 @@ DSRTC_MASK	.EQU	%00001111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
 DSRTC_IDLE	.EQU	%00001000	; QUIESCENT STATE
 ;
 #DEFINE	DSRTC_OPRVAL	DSRTC_RTCVAL
+;
+		.ECHO	"MFPIC"
 ;
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	DSRTC_IO
+		.ECHO	"\n"
 ;
 DSRTC_BUFSIZ	.EQU	7		; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
 ;
--- a/Source/HBIOS/duart.asm
+++ b/Source/HBIOS/duart.asm
@@ -822,6 +822,10 @@ DUART0A_CFG:
 	.DW	DUART0_ACR		; IY+6	POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART0ACFG		; IY+8	LINE CONFIGURATION
 	.DB	1			; IY+10	MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART0BASE + $00
+	.ECHO	", CHANNEL A\n"
 ;
 DUART_CFGSIZ	.EQU	$ - DUART_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -835,6 +839,10 @@ DUART0B_CFG:
 	.DW	DUART0_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART0BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART0BASE + $08
+	.ECHO	", CHANNEL B\n"
 ;
 #IF (DUARTCNT >= 2)
 ;
@@ -848,6 +856,10 @@ DUART1A_CFG:
 	.DW	DUART1_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART1ACFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART1BASE + $00
+	.ECHO	", CHANNEL A\n"
 ;
 DUART1B_CFG:
 	; 2ND DUART MODULE CHANNEL B
@@ -859,6 +871,10 @@ DUART1B_CFG:
 	.DW	DUART1_ACR		; POINTER TO SHADOW ACR FOR THIS CHIP
 	.DW	DUART1BCFG		; LINE CONFIGURATION
 	.DB	1			; MULTIPLIER WRT 3.6864MHZ CLOCK
+;
+	.ECHO	"DUART: IO="
+	.ECHO	DUART1BASE + $08
+	.ECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/esp.asm
+++ b/Source/HBIOS/esp.asm
@@ -53,6 +53,10 @@ ESP_CFG_IO	.EQU	1		; ESP I/O PORT
 ESP_CFG_ST	.EQU	2		; ESP STATUS PORT
 ESP_CFG_RDYMSK	.EQU	3		; ESP READY MASK
 ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
+;
+	.ECHO	"ESP: IO="
+	.ECHO	ESP_IOBASE
+	.ECHO	"\n"
 ;
 ; GLOBAL ESP INITIALIZATION
 ;
@@ -343,6 +347,8 @@ ESP_STR_UPGRADE		.TEXT	"!!!UPGRADE REQUIRED!!!$"
 ;
 ESPCON_ROWS	.EQU	25		; VGA DISPLAY ROWS
 ESPCON_COLS	.EQU	80		; VGA DISPLAY COLS
+;
+	.ECHO	"ESPCON: ENABLED\n"
 ;
 ;
 ;
@@ -685,7 +691,8 @@ ESPSER0_CFG:
 	.DB	ESP_0_RDY			; ESP READY BIT MASK
 	.DB	ESP_0_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
-
+;
+	.ECHO	"ESPSER: DEVICE=0\n"
 ;
 ESPSER1_CFG:
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
@@ -694,6 +701,8 @@ ESPSER1_CFG:
 	.DB	ESP_1_RDY			; ESP READY BIT MASK
 	.DB	ESP_1_BUSY			; ESP BUSY BIT MASK
 	.DW	ESPSER_LINECFG			; LINE CONFIGURATION
+;
+	.ECHO	"ESPSER: DEVICE=1\n"
 ;
 ;
 ;
--- a/Source/HBIOS/fd.asm
+++ b/Source/HBIOS/fd.asm
@@ -14,6 +14,7 @@ FDC_DATA	.EQU	$37		; 8272 DATA PORT
 FDC_DIR		.EQU	$38		; DATA INPUT REGISTER
 FDC_DOR		.EQU	$3A		; DIGITAL OUTPUT REGISTER (LATCH)
 FDC_DMA		.EQU	$3C		; PSEUDO DMA DATA PORT
+  #DEFINE FDMODE_STR "DIO"
 #ENDIF
 #IF (FDMODE = FDMODE_ZETA2)
 FDC_MSR		.EQU	$30		; 8272 MAIN STATUS REGISTER
@@ -21,6 +22,7 @@ FDC_DATA	.EQU	$31		; 8272 DATA PORT
 FDC_DOR		.EQU	$38		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$28		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$38		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "ZETA2"
 #ENDIF
 #IF (FDMODE == FDMODE_DIDE)
 FDC_BID		.EQU	$20		; IO RANGE 20H-3FH
@@ -31,6 +33,7 @@ FDC_DCR		.EQU	$2D		; DCR
 FDC_DACK	.EQU	$3C		; DACK
 FDC_TC		.EQU	$3D		; TERMINAL COUNT (W/ DACK)
 FDC_DMA		.EQU	$3C		; NOT USED BY DIDE
+  #DEFINE FDMODE_STR "DIDE"
 #ENDIF
 #IF (FDMODE == FDMODE_N8)
 FDC_MSR		.EQU	$8C		; 8272 MAIN STATUS REGISTER
@@ -40,11 +43,13 @@ FDC_DCR		.EQU	$91		; DCR
 FDC_DACK	.EQU	$90		; DACK
 FDC_TC		.EQU	$93		; TERMINAL COUNT (W/ DACK)
 FDC_DMA		.EQU	$3C		; NOT USED BY N8
+  #DEFINE FDMODE_STR "N8"
 #ENDIF
 #IF (FDMODE == FDMODE_RCSMC)
 FDC_MSR		.EQU	$50		; 8272 MAIN STATUS REGISTER
 FDC_DATA	.EQU	$51		; 8272 DATA PORT
 FDC_DOR		.EQU	$58		; DIGITAL OUTPUT REGISTER (LATCH)
+  #DEFINE FDMODE_STR "RCSMC"
 #ENDIF
 #IF (FDMODE == FDMODE_RCWDC)
 FDC_MSR		.EQU	$50		; 8272 MAIN STATUS REGISTER
@@ -52,6 +57,7 @@ FDC_DATA	.EQU	$51		; 8272 DATA PORT
 FDC_DOR		.EQU	$58		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$48		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$58		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "RCWDC"
 #ENDIF
 #IF (FDMODE == FDMODE_DYNO)
 FDC_BASE        .EQU    $84
@@ -60,6 +66,7 @@ FDC_DATA	.EQU	FDC_BASE + $01	; 8272 DATA PORT
 FDC_DOR		.EQU	FDC_BASE + $02	; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	FDC_BASE + $03	; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	FDC_BASE + $02	; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "DYNO"
 #ENDIF
 #IF (FDMODE == FDMODE_EPFDC)
 FDC_MSR		.EQU	$48		; 8272 MAIN STATUS REGISTER
@@ -67,6 +74,7 @@ FDC_DATA	.EQU	$49		; 8272 DATA PORT
 FDC_DOR		.EQU	$4A		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$4B		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$4C		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "EPFDC"
 #ENDIF
 #IF (FDMODE == FDMODE_MBC)
 FDC_MSR		.EQU	$30		; 8272 MAIN STATUS REGISTER
@@ -74,8 +82,10 @@ FDC_DATA	.EQU	$31		; 8272 DATA PORT
 FDC_DOR		.EQU	$36		; DIGITAL OUTPUT REGISTER
 FDC_DCR		.EQU	$35		; CONFIGURATION CONTROL REGISTER
 FDC_TC		.EQU	$37		; TERMINAL COUNT (W/ DACK)
+  #DEFINE FDMODE_STR "MBC"
 #ENDIF
 ;
+;
 ; DISK OPERATIONS
 ;
 DOP_READ	.EQU	0		; READ OPERATION
@@ -133,6 +143,33 @@ FD_CFGTBL:
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
 	.DB	FD0TYPE			; DRIVE TYPE
+;
+	.ECHO	"FD: MODE="
+	.ECHO	FDMODE_STR
+	.ECHO	", IO="
+	.ECHO	FDC_MSR
+	.ECHO	", DRIVE 0"
+	.ECHO	", TYPE="
+  #IF (FD0TYPE == FDT_NONE
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (FD0TYPE == FDT_3DD
+	.ECHO	"3.5\" DD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_3HD
+	.ECHO	"3.5\" HD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_5DD
+	.ECHO	"5.25\" DD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_5HD
+	.ECHO	"5.25\" HD"
+  #ENDIF
+  #IF (FD0TYPE == FDT_8
+	.ECHO	"8\" DD"
+  #ENDIF
+	.ECHO	"\n"
+;
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
 	.DB	1			; DRIVER DEVICE NUMBER
@@ -143,6 +180,32 @@ FD_CFGTBL:
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
 	.DB	FD1TYPE			; DRIVE TYPE
+;
+	.ECHO	"FD: MODE="
+	.ECHO	FDMODE_STR
+	.ECHO	", IO="
+	.ECHO	FDC_MSR
+	.ECHO	", DRIVE 1"
+	.ECHO	", TYPE="
+  #IF (FD1TYPE == FDT_NONE
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (FD1TYPE == FDT_3DD
+	.ECHO	"3.5\" DD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_3HD
+	.ECHO	"3.5\" HD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_5DD
+	.ECHO	"5.25\" DD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_5HD
+	.ECHO	"5.25\" HD"
+  #ENDIF
+  #IF (FD1TYPE == FDT_8
+	.ECHO	"8\" DD"
+  #ENDIF
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)
--- a/Source/HBIOS/gdc.asm
+++ b/Source/HBIOS/gdc.asm
@@ -36,16 +36,33 @@ GDC_COLS	.EQU	80
 ; *** TODO: CGA AND EGA ARE PLACEHOLDERS.  THESE EQUATES SHOULD
 ; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT
 ; DEFINITIONS.
+;
+	.ECHO	"GDC: MODE="
+;
+#IF (GDCMODE == GDCMODE_ECB)
+	.ECHO	"ECB"
+#ENDIF
+#IF (GDCMODE == GDCMODE_RPH)
+	.ECHO	"RPH"
+#ENDIF
+;
+	.ECHO	", DISPLAY="
 ;
 #IF (GDCMON == GDCMON_CGA)
  #DEFINE	USEFONTCGA
  #DEFINE	GDC_FONT FONTCGA
+	.ECHO	"CGA"
 #ENDIF
 ;
 #IF (GDCMON == GDCMON_EGA)
  #DEFINE	USEFONT8X16
  #DEFINE	GDC_FONT FONT8X16
+	.ECHO	"EGA"
 #ENDIF
+;
+	.ECHO	", IO="
+	.ECHO	GDC_BASE
+	.ECHO	"\n"
 ;
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 ;
@@ -70,7 +87,7 @@ GDC_INIT:
 #ENDIF	
 #IF (GDCMON == GDCMON_EGA)
 	PRTS(" EGA$")
-#ENDIF	
+#ENDIF
 ;
 	PRTS(" IO=0x$")
 	LD	A,GDC_BASE
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -71,6 +71,8 @@
 ;
 #DEFINE	HBIOS
 ;
+SUPCTS	.EQU	FALSE		; SUPPRESS CTS DURING HBIOS BOOT
+;
 ; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
 ;
 MODCNT	.EQU	0
@@ -215,6 +217,24 @@ RTCDEF		.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 ;
 ;
 ;
+#IF (FPLED_ENABLE | FPSW_ENABLE)
+	.ECHO	"FP: "
+  #IF (FPLED_ENABLE)
+	.ECHO	"LEDIO="
+	.ECHO	FPLED_IO
+  #ENDIF
+  #IF (FPLED_ENABLE & FPSW_ENABLE)
+	.ECHO	", "
+  #ENDIF
+  #IF (FPSW_ENABLE)
+	.ECHO	"SWIO="
+	.ECHO	FPSW_IO
+  #ENDIF
+	.ECHO	"\n"
+#ENDIF
+;
+;
+;
 #IFNDEF	APPBOOT
 ;
 	.ORG	0
@@ -991,7 +1011,8 @@ HBX_BUF_END	.EQU	$
 	.DW	0			; HB_DSTADR: BNKCPY DESTINATION ADDRESS
 	.DB	BID_USR			; HB_DSTBNK: BNKCPY DESTINATION BANK ID
 	.DW	0			; HB_CPYLEN: BNKCPY LENGTH
-	.FILL	4,0			; FILLER, RESERVED FOR FUTURE HBIOS USE
+	.DW	0			; RESERVED FOR OPTIONAL TICK CTR, PLATFORM DEPENDENT
+	.DW	0			; RESERVED FOR FUTURE HBIOS USE
 	.DB	0			; SHADOW VALUE FOR RTC LATCH PORT
 	.DB	$FE			; HB_LOCK: HBIOS MUTEX LOCK
 	JP	HBX_INVOKE		; HB_INVOKE: FIXED ADR ENTRY FOR HBX_INVOKE (ALT FOR RST 08)
@@ -1114,12 +1135,17 @@ BOOTWAIT:
 	JR	NZ,BOOTWAIT
 #ENDIF
 ;
-;#IF ((PLATFORM == PLT_MBC) | (PLATFORM == PLT_SBC))
-	; INITIALIZE RTC LATCH BYTE
+	; EARLY RTC LATCH BYTE INITIALIZATION
 	; FOR SOME PLATFORMS THIS CONTROLS HI/LO SPEED CIRCUIT
-	LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
+	; NOTE: WE WANT TO USE (RTCDEFVAL) HERE, BUT THE Z2 MEMORY
+	; MANAGER STARTS UP WITH THE FIRST 16K OF ROM MAPPED TO ALL
+	; 4 16K BANKS OF CPU SPACE.  SO, IF RTCDEVFAL IS LOCATED AFTER
+	; PAST 16K, WE DON'T HAVE ACCESS TO IT.  FOR NOW, WE JUST USE
+	; RTCDEF WHICH IS SUBOPTIMAL, BUT PROBABLY DOES NOT CAUSE ANY
+	; PROBLEMS.
+	;LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
+	LD	A,RTCDEF		; DEFAULT VALUE
 	OUT	(RTCIO),A		; SET IT
-;#ENDIF
 ;
 #IF (PLATFORM == PLT_N8)
 	LD	A,N8_DEFACR		; ENSURE N8 ACR
@@ -1141,7 +1167,9 @@ BOOTWAIT:
 	XOR	A			; LED IS INVERTED, TURN IT ON
  #ENDIF
  #IF (LEDMODE == LEDMODE_RTC)
-	LD	A,(RTCDEFVAL)		; DEFAULT LATCH VALUE
+	; CAN'T USE (RTCDEFVAL) YET, SEE COMMENTS ABOVE
+	;LD	A,(RTCDEFVAL)		; DEFAULT LATCH VALUE
+	LD	A,RTCDEF		; DEFAULT LATCH VALUE
 	OR	%00000001		; LED 0 ON
  #ENDIF
 	OUT	(LEDPORT),A
@@ -1347,6 +1375,41 @@ Z280_INITZ:
 	OUT	(FPLED_IO),A
 #ENDIF

+;
+; Z180 MINI-ITX MADNESS TO INITIALIZE THE PPIO. WE HAVE THE MAIN RAM AT
+; $8000 AND ROM AT $0 AT THIS POINT AND THE Z180 MMU SET UP. NOW
+; GET THE 82C55 PROGRAMMED.
+;
+#IF (PLATFORM == PLT_EPITX)
+	; THE 82C55 IS BRAINDEAD AND FLIPS OUTPUT LINES TO 0 WHEN WE SET
+	; THE MODE. WE BOOT WITH THE ROM ENABLED BUT THE RESET WILL ENABLE
+	; LOW RAM. SOME MENTAL BACKFLIPS REQUIRED TO MAKE THIS WORK
+	LD	HL,BOOTFLIP
+	LD	DE,$8000
+	LD	BC,$10
+	LDIR
+	JP	$8000
+;
+BOOTFLIP:
+	; SET THE MODE. ALSO CLEARS ALL THE OUTPUT BITS SO WE BLIP THE
+	; I2C, KEYBOARD ETC BUT NOBODY WILL CARE. HOWEVER WE ALSO FLIP
+	; TO ALL RAM MODE HENCE THIS IS EXECUTED HIGH
+	; A OUT B IN C HIGH IN C LOW IN
+	LD	A,$8B
+	OUT	($43),A
+	LD	A,$FF
+	OUT	($40),A
+	JP	ROMRESUME
+;
+ROMRESUME:
+	; THIS WILL GLITCH EXTRAM ON SO WE MUST NOW BE IN ROM
+	LD	A,$8A		; C LOW NOW OUTPUT
+	OUT	($43),A
+	LD	A,$FF
+	OUT	($42),A		; EXTRAM OFF, RAM BACK IN, SPI 7
+	; AND DONE. MODE REMAINS THIS WAY FOREVER
+;
+#ENDIF
 ;
 ; WE USE THE TWO BYTES IMMEDIATELY BELOW THE PROXY TO STORE A COUPLE
 ; VALUES TEMPORARILY BECAUSE WE MAY BE OPERATING IN ROM AT THIS POINT.
@@ -1432,11 +1495,15 @@ S100MON_SKIP:
 	LD	A,(HB_CURBNK)		; GET HB_CURBNK
 	LD	(HBX_LOC - 2),A		; ... AND SAVE TEMP FOR APPBNK
 ;
-; THE RTCVAL FIELD OF THE PROXY DATA NEEDS TO BE INITIALIZED HERE
-; BECAUSE IT CANNOT BE PRE-INITIALIZED (SEE COMMENTS ABOVE WHERE
-; RTCVAL EQUATE IS DEFINED).
+; WE CAN NOW DO THE REAL INITIALIZATION OF THE RTC LATCH BASED ON
+; (RTCDEFVAL).  AT THIS POINT WE SHOULD HAVE ACCESS TO THE ROM LOCATION
+; WHERE RTCDEFVAL IS STORED AND THE PROXY IS INSTALLED IN UPPER RAM
+; WHERE WE WILL STORE THE WORKING SHADOW COPY (HB_RTCVAL).
+; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS
+; CREATED.
 ;
 	LD	A,(RTCDEFVAL)
+	OUT	(RTCIO),A		; SET IT
 	LD	(HB_RTCVAL),A
 ;
 #IFDEF TESTING
@@ -1599,51 +1666,43 @@ MBC_SINGLE:
 ;
 #ENDIF
 ;
-; IF ALREADY EXECUTING IN RAM, BYPASS RAM BANK INSTALLATION
-;
-	LD	A,(HB_RAMFLAG)
-	OR	A
-	JR	NZ,HB_START1
-;
-; IF BID_BOOT AND BID_BIOS ARE THE SAME, THEN IT IS NEVER APPROPRIATE
-; TO COPY THE HBIOS IMAGE FROM BID_BOOT TO BID_BIOS.  THIS IS TYPICALLY
-; THE CASE FOR A ROMLESS SYSTEM.
-;
-#IF (BID_BOOT != BID_BIOS)
-;
 ; INSTALL HBIOS IN RAM BANK
 ;
 	LD	A,(HB_CURBNK)
+;
+	; CHECK TO SEE IF WE ARE ALREADY RUNNING IN THE HBIOS
+	; BANK AND SKIP THE COPY IF SO (DON'T COPY OVER OURSELVES).
+	; THIS SITUATION OCCURS ON A ROMLESS STARTUP OR WHEN DOING A
+	; FULL RESTART OF A SYSTEM USING THE EXISTING HBIOS COPY.
+	CP	BID_BIOS
+	JR	Z,HB_START1
+;
 	LD	(HB_SRCBNK),A
 	LD	A,BID_BIOS
 	LD	(HB_DSTBNK),A
 	LD	HL,0
 	LD	DE,0
 	LD	BC,$8000
-  #IF (MEMMGR == MM_Z280)
+#IF (MEMMGR == MM_Z280)
 	CALL	Z280_BNKCPY
-  #ELSE
+#ELSE
 	CALL	HBX_BNKCPY
-  #ENDIF
+#ENDIF
 ;
 ; TRANSITION TO HBIOS IN RAM BANK
 ;
-  #IF (MEMMGR == MM_Z280)
+#IF (MEMMGR == MM_Z280)
 	LD	A,BID_BIOS
 	LD	B,$10			; FIRST SYSTEM PDR
 	CALL	Z280_BNKSEL
 	JR	HB_START1
-  #ELSE
+#ELSE
 	LD	A,BID_BIOS		; BIOS BANK ID
 	LD	IX,HB_START1		; EXECUTION RESUMES HERE
 	CALL	HBX_BNKCALL		; CONTINUE IN RAM BANK, DO NOT RETURN
 	HALT				; WE SHOULD NOT COME BACK HERE!
-  #ENDIF
-;
 #ENDIF
 ;
-HB_RAMFLAG	.DB	FALSE		; INITIALLY FALSE, SET TO TRUE BELOW AFTER RAM TRANSITION
-;
 ; EXECUTION RESUMES HERE AFTER SWITCH TO RAM BANK
 ;
 HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
@@ -1857,11 +1916,13 @@ HB_CPU1:
 ;
 ; CLEAR DISPATCH TABLE ENTRIES
 ;
-	XOR	A		; ZERO
-	LD	(CIO_CNT),A	; CIO DEVICES
-	LD	(DIO_CNT),A	; DIO DEVICES
-	LD	(VDA_CNT),A	; VDA DEVICES
-	LD	(SND_CNT),A	; SND DEVICES
+	XOR	A			; ZERO
+	LD	(CIO_CNT),A		; CIO DEVICES
+	LD	(DIO_CNT),A		; DIO DEVICES
+	LD	(VDA_CNT),A		; VDA DEVICES
+	LD	(SND_CNT),A		; SND DEVICES
+	LD	(RTC_DISPACT),A		; RTC DEVICE
+	LD	(DSKY_DISPACT),A	; DSKY DEVICE
 ;
 #IF (DSRTCENABLE)
 	CALL	DSRTC_PREINIT
@@ -2060,7 +2121,7 @@ HB_CPU3:
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
 ;
-#IF (INTMODE == 2)
+#IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180)))
 	; SETUP Z80 IVT AND INT MODE 2
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
 	LD	I,A			; ... AND PLACE IT IN I REGISTER
@@ -2071,7 +2132,9 @@ HB_CPU3:
 	OUT0	(Z180_IL),A		; ... AND PLACE IN Z180 IL REGISTER
  #ENDIF

+  #IF (INTMODE == 2)
 	IM	2			; SWITCH TO INT MODE 2
+  #ENDIF
 #ENDIF
 ;
 #IF (INTMODE == 3)
@@ -2300,8 +2363,36 @@ HB_BOOTDLY:
 	JR	C,HB_CONRDY		; IF TOO HIGH, JUST USE FAILSAFE
 	LD	A,BOOTCON		; GET REQUESTED CONSOLE DEV
 	LD	(CB_CONDEV),A		; SAVE IT
+;
 HB_CONRDY:
 ;
+#IF (SUPCTS)
+;
+; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
+; IF THERE IS A PROBLEM WITH THE CTS SIGNAL, THEN OUTPUT TO THE CONSOLE
+; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
+; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR CTS TO BE ASSERTED.  ALSO,
+; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
+; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT.  SO, HERE
+; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
+; FLOW CONTROL.  THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW
+; PRIOR TO LAUNCING THE ROM LOADER.
+;
+	; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
+	LD	B,BF_CIOQUERY		; HBIOS QUERY CIO CONFIG
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	(HB_BOOTCONSAV),A	; SAVE IT FOR LATER
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+	LD	(HB_CONCFGSAV),DE	; SAVE CONFIG
+	RES	5,D			; CLEAR RTS BIT
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
+#ENDIF
+;
 #IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
 	LD	E,(HL)
@@ -2825,19 +2916,27 @@ HB_FP1:
 ;
 HB_FP2:
 	; IF SEC SWITCH IS SET, WE WANT TO BUMP TO SECONDARY
-	; CRT OR SERIAL DEVICE.  FOR NOW, WE ARE GOING TO CHEAT AND
-	; JUST INCREMENT THE CONSOLE DEVICE UNIT.  THIS SHOULD WORK
-	; ASSUMING NORMAL ORDERING OF THE CHARACTER DEVICE UNITS.
+	; CRT OR SERIAL DEVICE. IF AN OVERRIDE IS SPECIFIED USING
+	; SECCON, USE THAT, OTHERWISE INCREMENT THE DEFAULT UNIT.
+	; THIS SHOULD WORK ASSUMING NORMAL ORDERING OF THE
+	; CHARACTER DEVICE UNITS.
 	LD	A,B			; RECOVER SWITCH SETTINGS
 	AND	SW_SEC			; TEST SEC BIT
 	JR	Z,HB_FPZ		; IF NOT SET, THEN ALL DONE
 ;
-	; INCREMENT CONSOLE UNIT, BUT MAKE SURE IT DOES NOT EXCEED
-	; THE HIGHEST CHAR UNIT IN SYSTEM.
 	LD	A,(CIO_CNT)		; GET CHAR UNIT COUNT
 	LD	B,A			; MOVE TO B
+	LD	A,SECCON		; GET SEC CONSOLE SETTING
+	CP	$FF			; $FF MEANS USE INCREMENT
+	JR	NZ,HB_FP3		; BYPASS IF NOT $FF 
+;
+	; INCREMENT CONSOLE UNIT
 	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT
 	INC	A			; BUMP TO SECONDARY
+;
+HB_FP3:
+	; MAKE SURE NEW CONSOLE UNIT DOES NOT EXCEED THE HIGHEST
+	; CHAR UNIT IN SYSTEM.
 	CP	B			; A (UNIT) >= B (CNT)?
 	JR	NC,HB_FPZ		; ABORT IF UNIT TOO HIGH
 	LD	(HB_NEWCON),A		; UPDATE NEW CONSOLE UNIT
@@ -2848,6 +2947,19 @@ HB_FPZ:
 ;
 INITSYS3:
 ;
+#IF (SUPCTS)
+;
+; RESTORE BOOT CONSOLE CONFIGURATION
+;
+	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(HB_BOOTCONSAV)	; ORIGINAL BOOT CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	LD	DE,(HB_CONCFGSAV)	; SAVED ORIGINAL CONSOLE CFG
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
+#ENDIF
+;
 ; IF WE ARE GOING TO SWITCH CONSOLES, IT IS IMPLEMENTED HERE.  A
 ; MESSAGE IS PRINTED ON THE OLD CONSOLE INDICATING WHERE THE NEW
 ; CONSOLE IS AND THE NEW CONSOLE RECEIVES AN HBIOS BANNER.
@@ -5380,10 +5492,10 @@ HB_BADINTCNT	.DB	0
 	LD	A,L
 	RRCA
 	RRCA
-	CALL PRTHEXBYTE
-	PRTS("H: $")
-
+	;CALL PRTHEXBYTE
+	;PRTS("H: $")
 	CALL	XREGDMP
+	CALL	NEWLINE
 	;CALL	CONTINUE
 	OR	$FF			; SIGNAL INTERRUPT HANDLED
 	RET
@@ -7721,6 +7833,11 @@ HB_BOOTCON	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
 HB_BOOTCFG	.DW	0		; CONSOLE CONFIG SAVE AREA
 HB_NEWCON	.DB	0		; NEW CONSOLE TO SWITCH TO
 ;
+#IF (SUPCTS)
+HB_BOOTCONSAV	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
+HB_CONCFGSAV	.DW	0		; CONSOLE CONFIG SAVE AREA
+#ENDIF
+;
 HB_HASFP	.DB	0		; NON-ZERO MEANS FP EXISTS
 ;
 HB_WRKBUF	.FILL	512,0		; INTERNAL DISK BUFFER
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -153,6 +153,7 @@ PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 PLT_S100	.EQU	16		; S100 COMPUTERS Z180 SYSTEM
 PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
 PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
+PLT_EPITX	.EQU	19		; Z180 MINI-ITX
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
--- a/Source/HBIOS/hdsk.asm
+++ b/Source/HBIOS/hdsk.asm
@@ -21,6 +21,12 @@ HDSK_CFGSIZ	.EQU	6		; SIZE OF CFG TBL ENTRIES
 HDSK_DEV	.EQU	0		; OFFSET OF DEVICE NUMBER (BYTE)
 HDSK_STAT	.EQU	1		; OFFSET OF STATUS (BYTE)
 HDSK_LBA	.EQU	2		; OFFSET OF LBA (DWORD)
+;
+	.ECHO	"HDSK: IO="
+	.ECHO	HDSK_IO
+	.ECHO	", DEVICE COUNT="
+	.ECHO	HDSK_DEVCNT
+	.ECHO	"\n"
 ;
 HDSK_CFGTBL:
 	; DEVICE 0
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@@ -213,6 +213,27 @@ IDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	IDE0DATLO		; IO BASE ADDRESS
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE0MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE0BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -227,6 +248,27 @@ IDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	IDE0DATLO		; IO BASE ADDRESS
 	.DB	IDE0DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV0M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE0MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE0MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE0BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 2)
@@ -244,6 +286,27 @@ IDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	IDE1DATLO		; IO BASE ADDRESS
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE1MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE1BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -258,6 +321,27 @@ IDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	IDE1DATLO		; IO BASE ADDRESS
 	.DB	IDE1DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE1MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE1MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE1BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IDECNT >= 3)
@@ -275,6 +359,27 @@ IDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	IDE2DATLO		; IO BASE ADDRESS
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV2S		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE2MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE2BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -289,6 +394,27 @@ IDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	IDE2DATLO		; IO BASE ADDRESS
 	.DB	IDE2DATHI		; IO BASE ADDRESS
 	.DW	IDE_DEV1M		; PARTNER
+;
+	.ECHO	"IDE: MODE="
+  #IF (IDE2MODE == IDEMODE_NONE)
+	.ECHO	"NONE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIO)
+	.ECHO	"DIO"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_DIDE)
+	.ECHO	"DIDE"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_MK4)
+	.ECHO	"MK4"
+  #ENDIF
+  #IF (IDE2MODE == IDEMODE_RC)
+	.ECHO	"RC"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IDE2BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IDE_CFGTBL) != (IDE_DEVCNT * IDE_CFGSIZ)
--- a/Source/HBIOS/imm.asm
+++ b/Source/HBIOS/imm.asm
@@ -1525,6 +1525,17 @@ IMM0_CFG:	; DEVICE 0
 	.DB	IMM0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"IMM: MODE="
+  #IF (IMMMODE == IMMMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (IMMMODE == IMMMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IMM0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (IMMCNT >= 2)
@@ -1536,6 +1547,17 @@ IMM1_CFG:	; DEVICE 1
 	.DB	IMM1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"IMM: MODE="
+  #IF (IMMMODE == IMMMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (IMMMODE == IMMMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	IMM1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - IMM_CFG) != (IMMCNT * IMM_CFGSIZ)
--- a/Source/HBIOS/intrtc.asm
+++ b/Source/HBIOS/intrtc.asm
@@ -4,6 +4,8 @@
 ;==================================================================================================
 ;
 INTRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+		.ECHO	"INTRTC: ENABLED\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;
--- a/Source/HBIOS/kbd.asm
+++ b/Source/HBIOS/kbd.asm
@@ -55,6 +55,8 @@ KBD_RSTATE	.DB	0	; STATE BITS FOR "RIGHT" KEYS
 KBD_STATUS	.DB	0	; CURRENT STATUS BITS (SEE ABOVE)
 KBD_REPEAT	.DB	0	; CURRENT REPEAT RATE
 KBD_IDLE	.DB	0	; IDLE COUNT
+;
+	.ECHO	"KBD: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION
--- a/Source/HBIOS/lpt.asm
+++ b/Source/HBIOS/lpt.asm
@@ -346,10 +346,10 @@ LPT_DETECT:
 	LD	A,$A5			; TEST VALUE
 	OUT	(C),A			; PUSH VALUE TO PORT
 	IN	A,(C)			; GET PORT VALUE
-#IF (LPTTRACE >= 3)
+  #IF (LPTTRACE >= 3)
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
-#ENDIF
+  #ENDIF
 	CP	$A5			; CHECK FOR TEST VALUE
 	JR	Z,LPT_DETECT1		; FOUND IT
 	LD	A,LPTMODE_NONE		; NOT FOUND
@@ -420,6 +420,17 @@ LPT0_CFG:
 	.DB	0			; MODULE ID
 	.DB	LPT0BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
+;
+	.ECHO	"LPT: MODE="
+  #IF (LPTMODE == LPTMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (LPTMODE == LPTMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	LPT0BASE
+	.ECHO	"\n"
 ;
 LPT_CFGSIZ	.EQU	$ - LPT_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -432,6 +443,17 @@ LPT1_CFG:
 	.DB	1			; MODULE ID
 	.DB	LPT1BASE		; BASE PORT
 	.DW	0			; LINE CONFIGURATION
+;
+	.ECHO	"LPT: MODE="
+  #IF (LPTMODE == LPTMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (LPTMODE == LPTMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	LPT1BASE
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@@ -39,6 +39,8 @@ MD_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	MID_MDRAM		; DEVICE MEDIA ID
 	.DB	MD_ARAM			; DEVICE ATTRIBUTE
+;
+	.ECHO	"MD: TYPE=RAM\n"
 #ENDIF
 ;
 #IF (MDROM)
@@ -48,6 +50,8 @@ MD_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	MID_MDROM		; DEVICE MEDIA ID
 	.DB	MD_AROM			; DEVICE ATTRIBUTE
+;
+	.ECHO	"MD: TYPE=ROM\n"
 #ENDIF
 ;
 MD_DEVCNT	.EQU	($ - MD_CFGTBL) / MD_CFGSIZ
--- a/Source/HBIOS/pcf.asm
+++ b/Source/HBIOS/pcf.asm
@@ -93,6 +93,10 @@ PCF_PINTO	.EQU	65000
 PCF_ACKTO	.EQU	65000
 PCF_BBTO	.EQU	65000
 PCF_LABDLY	.EQU	65000
+;
+	.ECHO	"PCF: IO="
+	.ECHO	PCF_BASE
+	.ECHO	"\n"
 ;
 ; DATA PORT REGISTERS
 ;
--- a/Source/HBIOS/pio.asm
+++ b/Source/HBIOS/pio.asm
@@ -307,6 +307,10 @@ PIO0A_CFG:
 	.DB	PIO0A_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO0BASE
+	.ECHO	", CHANNEL A\n"
 ;
 PIO_CFGSIZ	.EQU	$ - PIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -319,6 +323,10 @@ PIO0B_CFG:
 	.DB	PIO0B_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO0B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO0BASE
+	.ECHO	", CHANNEL B\n"
 ;
 #IF (PIOCNT >= 2)
 ;
@@ -331,6 +339,10 @@ PIO1A_CFG:
 	.DB	PIO1A_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO1BASE
+	.ECHO	", CHANNEL A\n"
 ;
 	; PIO1 CHANNEL B
 PIO1B_CFG:
@@ -341,6 +353,10 @@ PIO1B_CFG:
 	.DB	PIO1B_DAT		; DATA PORT
 	.DW	DEFSERCFG		; LINE CONFIGURATION
 	.DW	PIO1B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"PIO: IO="
+	.ECHO	PIO1BASE
+	.ECHO	", CHANNEL B\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/pkd.asm
+++ b/Source/HBIOS/pkd.asm
@@ -65,6 +65,10 @@ PKD_CMD_CLK	.EQU	%00100000		; SET CLK PRESCALE
 PKD_CMD_FIFO	.EQU	%01000000		; READ FIFO
 ;
 PKD_PRESCL	.EQU	PKDOSC/100000		; PRESCALER
+;
+	.ECHO	"PKD: IO="
+	.ECHO	PKDPPIBASE
+	.ECHO	"\n"
 ;
 ;__PKD_PREINIT_______________________________________________________________________________________
 ;
--- a/Source/HBIOS/ppa.asm
+++ b/Source/HBIOS/ppa.asm
@@ -139,7 +139,7 @@ PPA_LBA		.EQU	8		; OFFSET OF LBA (DWORD)
 ;
 ; INCLUDE MG014 NIBBLE MAP FOR MG014 MODE
 ;
-#IF (IMMMODE == IMMMODE_MG014)
+#IF (PPAMODE == IMMMODE_MG014)
  #DEFINE MG014_MAP
 #ENDIF
 ;
@@ -1385,6 +1385,17 @@ PPA0_CFG:	; DEVICE 0
 	.DB	PPA0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"PPA: MODE="
+  #IF (PPAMODE == PPAMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (PPAMODE == PPAMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	PPA0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (PPACNT >= 2)
@@ -1396,6 +1407,17 @@ PPA1_CFG:	; DEVICE 1
 	.DB	PPA1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"PPA: MODE="
+  #IF (PPAMODE == PPAMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (PPAMODE == PPAMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	PPA1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - PPA_CFG) != (PPACNT * PPA_CFGSIZ)
--- a/Source/HBIOS/ppide.asm
+++ b/Source/HBIOS/ppide.asm
@@ -229,6 +229,11 @@ PPIDE_DEV0M:	; DEVICE 0, MASTER
 	.DB	PPIDE0BASE+2		; CTL
 	.DB	PPIDE0BASE+3		; PPI
 	.DW	PPIDE_DEV0S		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE0BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 PPIDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -242,6 +247,11 @@ PPIDE_DEV0S:	; DEVICE 0, SLAVE
 	.DB	PPIDE0BASE+2		; CTL
 	.DB	PPIDE0BASE+3		; PPI
 	.DW	PPIDE_DEV0M		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE0BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
@@ -259,6 +269,11 @@ PPIDE_DEV1M:	; DEVICE 1, MASTER
 	.DB	PPIDE1BASE+2		; CTL
 	.DB	PPIDE1BASE+3		; PPI
 	.DW	PPIDE_DEV1S		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE1BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 PPIDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -272,6 +287,11 @@ PPIDE_DEV1S:	; DEVICE 1, SLAVE
 	.DB	PPIDE1BASE+2		; CTL
 	.DB	PPIDE1BASE+3		; PPI
 	.DW	PPIDE_DEV1M		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE1BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
@@ -289,6 +309,11 @@ PPIDE_DEV2M:	; DEVICE 2, MASTER
 	.DB	PPIDE2BASE+2		; CTL
 	.DB	PPIDE2BASE+3		; PPI
 	.DW	PPIDE_DEV2S		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE2BASE
+	.ECHO	", MASTER"
+	.ECHO	"\n"
 ;
 PPIDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	$FE			; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY)
@@ -302,6 +327,11 @@ PPIDE_DEV2S:	; DEVICE 2, SLAVE
 	.DB	PPIDE2BASE+2		; CTL
 	.DB	PPIDE2BASE+3		; PPI
 	.DW	PPIDE_DEV2M		; PARTNER
+;
+	.ECHO	"PPIDE: IO="
+	.ECHO	PPIDE2BASE
+	.ECHO	", SLAVE"
+	.ECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/ppk.asm
+++ b/Source/HBIOS/ppk.asm
@@ -59,6 +59,8 @@ PPK_STATUS	.DB	0	; CURRENT STATUS BITS (SEE ABOVE)
 PPK_REPEAT	.DB	0	; CURRENT REPEAT RATE
 PPK_IDLE	.DB	0	; IDLE COUNT
 PPK_WAITTO	.DW	0	; TIMEOUT WAIT LOOP COUNT (COMPUTED IN INIT)
+;
+	.ECHO	"PPK: ENABLED\n"
 ;
 ;__________________________________________________________________________________________________
 ; KEYBOARD INITIALIZATION
--- a/Source/HBIOS/ppp.asm
+++ b/Source/HBIOS/ppp.asm
@@ -8,6 +8,10 @@
 PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)
 PPP_PPICTL	.EQU	PPPBASE + 3	; PPI CONTROL PORT
+;
+		.ECHO	"PPP: IO="
+		.ECHO	PPP_IO
+		.ECHO	"\n"
 ;
 ; COMMAND BYTES
 ;
@@ -248,6 +252,8 @@ PPP_FWVER		.DB	$00, $00, $00, $00	; MMNNBBB (M=MAJOR, N=MINOR, B=BUILD)
 ;
 PPPCON_ROWS	.EQU	37		; PROPELLER VGA DISPLAY ROWS (40 - 3 STATUS LINES)
 PPPCON_COLS	.EQU	80		; PROPELLER VGA DISPLAY COLS
+;
+		.ECHO	"PPPCON: ENABLED\n"
 ;
 PPPCON_INIT:
 	CALL	NEWLINE
@@ -413,6 +419,8 @@ PPPSD_CFGTBL:
 #ENDIF
 ;
 	.DB	$FF			; END MARKER
+;
+		.ECHO	"PPPSD: ENABLED\n"
 ;
 ; SD CARD INITIALIZATION
 ;
--- a/Source/HBIOS/prp.asm
+++ b/Source/HBIOS/prp.asm
@@ -6,6 +6,10 @@
 ; TODO:
 ;
 PRP_IOBASE	.EQU	$A8
+;
+		.ECHO	"PRP: IO="
+		.ECHO	PRP_IOBASE
+		.ECHO	"\n"
 ;
 ; GLOBAL PROPIO INITIALIZATION
 ;
@@ -119,6 +123,8 @@ PRPCON_DSPRDY	.EQU	$10		; BIT SET WHEN DISPLAY BUF IS READY FOR A BYTE (BUF EMPT
 ;
 PRPCON_ROWS	.EQU	37		; PROPELLER VGA DISPLAY ROWS (40 - 3 STATUS LINES)
 PRPCON_COLS	.EQU	80		; PROPELLER VGA DISPLAY COLS
+;
+		.ECHO	"PRPCON: ENABLED\n"
 ;
 ;
 ;
@@ -310,6 +316,8 @@ PRPSD_CFGTBL:
 #ENDIF
 ;
 	.DB	$FF			; END MARKER
+;
+	.ECHO	"PRPSD: ENABLED\n"
 ;
 ; SD CARD INITIALIZATION
 ;
--- a/Source/HBIOS/rf.asm
+++ b/Source/HBIOS/rf.asm
@@ -42,6 +42,11 @@ RF_CFGTBL:
 	.DW	0,0			; CURRENT LBA
 	.DB	0			; UNUSED
 	.DB	RF_U0IO			; DEVICE BASE ADDR
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U0IO
+	.ECHO	"\n"
+;
 #IF (RF_DEVCNT > 1)
 	; DEVICE 1
 	.DB	1			; DEVICE NUMBER
@@ -50,6 +55,11 @@ RF_CFGTBL:
 	.DB	0			; UNUSED
 	.DB	RF_U1IO			; DEVICE BASE ADDR
 #ENDIF
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U1IO
+	.ECHO	"\n"
+;
 #IF (RF_DEVCNT > 2)
 	; DEVICE 2
 	.DB	2			; DRIVER DEVICE NUMBER
@@ -58,13 +68,23 @@ RF_CFGTBL:
 	.DB	0			; UNUSED
 	.DB	RF_U2IO			; DEVICE BASE ADDR
 #ENDIF
-;	; DEVICE 3
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U2IO
+	.ECHO	"\n"
+;
 #IF (RF_DEVCNT > 3)
+	; DEVICE 3
 	.DB	3			; DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
 	.DW	0,0			; CURRENT LBA
 	.DB	0			; UNUSED
 	.DB	RF_U3IO			; DEVICE BASE ADDR
+;
+	.ECHO	"RF: IO="
+	.ECHO	RF_U3IO
+	.ECHO	"\n"
+;
 #ENDIF
 ;
 #IF ($ - RF_CFGTBL) != (RF_DEVCNT * RF_CFGSIZ)
--- a/Source/HBIOS/rp5rtc.asm
+++ b/Source/HBIOS/rp5rtc.asm
@@ -55,6 +55,10 @@ MODE_RAM1	.EQU	3
 MD_TIME		.EQU	8
 MD_ALRM		.EQU	4

+		.ECHO	"RP5C01: IO="
+		.ECHO	RP5RTC_REG
+		.ECHO	"\n"
+
 RP5RTC_INIT:
 	LD	A, (RTC_DISPACT)	; RTC DISPATCHER ALREADY SET?
 	OR	A			; SET FLAGS
--- a/Source/HBIOS/scon.asm
+++ b/Source/HBIOS/scon.asm
@@ -15,6 +15,10 @@ SCON_DSPRDY	.EQU	%00000100
 ;
 SCON_COLS	.EQU	80
 SCON_ROWS	.EQU	40
+;
+		.ECHO	"SCON: IO="
+		.ECHO	SCON_IOBASE
+		.ECHO	"\n"
 ;
 ;
 ;
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -116,6 +116,8 @@
 SD_NOPULLUP	.EQU	TRUE		; ASSUME NO PULLUP
 ;
 SD_DEVCNT	.EQU	SDCNT		; SET SD_DEVCNT TO SDCNT CONFIG VAR
+;
+		.ECHO	"SD: MODE="
 ;
 #IF (SDMODE == SDMODE_JUHA)		; JUHA MINI-BOARD
 SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
@@ -129,6 +131,7 @@ SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"JUHA"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@@ -145,6 +148,7 @@ SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%01000000	; RTC:6 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"N8"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@@ -159,6 +163,7 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"CSIO"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
@@ -179,6 +184,7 @@ SD_DI		.EQU	%00000001	; PPIC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; PPIB:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_PPIBASE	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		.ECHO	"PPI"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_UART)
@@ -193,6 +199,7 @@ SD_DI		.EQU	%00000001	; UART MCR:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%00100000	; UART MSR:5 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	UARTIOB		; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		.ECHO	"UART"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_DSD)		; DUAL SD
@@ -208,6 +215,7 @@ SD_DI		.EQU	%00000001	; RTC:6 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%00000001	; RTC:0 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"DSD"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_MK4)		; MARK IV (CSIO STYLE INTERFACE)
@@ -219,6 +227,7 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	FALSE		; INVERT CS
+		.ECHO	"MK4"
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_SC)		; SC
@@ -232,9 +241,16 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
+		.ECHO	"SC"
 ;
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
+;
+		.ECHO	", IO="
+		.ECHO	SD_IOBASE
+		.ECHO	", UNITS="
+		.ECHO	SDCNT
+		.ECHO	"\n"
 ;
 #IF (SDMODE == SDMODE_MT)		; MT shift register for RCBUS (ref SDMODE_CSIO)
 ;
@@ -357,6 +373,19 @@ SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
 SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
 SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
+
+; FOR NOW WE JUST HOOK UP ONE UNIT. THERE ARE EIGHT PORTS FOR DIFFERENT
+; THINGS BUT THIS WILL GET US GOING
+#IF (SDMODE == SDMODE_EPITX)		; Z180 ITX - CSIO, 82C55 for CS
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRREG	.EQU	$42		; 82C55 PORT C, LOW 3 ARE \CS MUX
+SD_OPRDEF	.EQU	%11111111	; QUIESCENT STATE (ROM ENABLED)
+SD_CS0		.EQU	%11111000	; SPI CHANNEL 0 (4 INPUTS, ROM EN, CHAN 0)
+SD_CNTR		.EQU	Z180_CNTR
+SD_TRDR		.EQU	Z180_TRDR
+SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
+SD_INVCS	.EQU	FALSE		; INVERT CS
+#ENDIF
 ;
 #IF (SD_DEVCNT > SD_DEVMAX)
 	.ECHO	"*** ERROR: SDCNT EXCEEDS MAXIMUM SUPPORTED BY INTERFACE!!!\n"
@@ -586,6 +615,22 @@ SD_INIT:
 	LD	A,SD_IOBASE
 	CALL	PRTHEXBYTE
 #ENDIF
+;
+#IF (SDMODE == SDMODE_EPITX)
+	PRTS(" MODE=EPITX$")
+  #IF (SDCSIOFAST)
+	PRTS(" FAST$")
+  #ENDIF
+	PRTS(" OPR=0x$")
+	LD	A,SD_OPRREG
+	CALL	PRTHEXBYTE
+	PRTS(" CNTR=0x$")
+	LD	A,SD_CNTR
+	CALL	PRTHEXBYTE
+	PRTS(" TRDR=0x$")
+	LD	A,SD_TRDR
+	CALL	PRTHEXBYTE
+#ENDIF
 ;
 	CALL	SD_PROBE		; CHECK FOR HARDWARE
 	JR	Z,SD_INIT00		; CONTINUE IF PRESENT
@@ -847,7 +892,7 @@ SD_IO:
 	OR	A			; SET FLAGS
 	RET	Z			; ZERO SECTOR I/O, RETURN W/ E=0 & A=0
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	; CONSIDER CAPTURING CURRENT CNTR VALUE HERE AND USE IT
 	; IN SD_CSIO_DEF

@@ -1026,7 +1071,7 @@ SD_INITCARD:
 	CALL	SD_CHKCD		; CHECK CARD DETECT
 	JP	Z,SD_NOMEDIA		; Z=NO MEDIA, HANDLE IF SO
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_CSIO_DEF		; ENSURE CSIO AT DEFAULT SPEED
 #ENDIF
 ;
@@ -1040,7 +1085,7 @@ SD_INITCARD1:
 	DJNZ	SD_INITCARD1		; LOOP AS NEEDED
 ;
 	; MAKE SURE WE FINISH SENDING
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 	CALL	DLY32			; WAIT A BIT MORE FOR FINAL BIT
 #ENDIF
@@ -1776,7 +1821,7 @@ SD_SETUP:
 	OUT	(SD_PPIX),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	; CSIO SETUP FOR Z180 CSIO
 ;	LD	A,2			; DIV 80, 225KHZ @ 18MHZ CLK
 	LD	A,6			; DIV 1280, 14KHZ @ 18MHZ CLK
@@ -1789,7 +1834,7 @@ SD_SETUP:
 	OUT	(SD_OPRREG),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_MT))
+#IF ((SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_EPITX))
 	LD	A,SD_OPRDEF
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
@@ -1894,10 +1939,16 @@ SD_SELECT1:
  #IF (SD_DEVCNT > 1)
 	OR	SD_CS1
  #ENDIF
+#ELSE
+#IF (SDMODE == SDMODE_EPITX)
+	LD	A,(SD_OPRVAL)
+	AND	$F8
+	OR	SD_CS0			; WILL DO 1-7 LATER
 #ELSE
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
 	OR	SD_CS0
 #ENDIF
+#ENDIF
 ;
 SD_SELECT2:
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
@@ -1921,7 +1972,7 @@ SD_SELECT2:
 ; DESELECT CARD
 ;
 SD_DESELECT:
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	; DON'T REMOVE CS UNTIL WE ARE DONE SENDING!
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 ;
@@ -1938,9 +1989,13 @@ SD_DESELECT:
 	LD	A,(SD_OPRVAL)
 #IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1))
 	AND	~(SD_CS0 | SD_CS1)
+#ELSE
+#if (SDMODE == SDMODE_EPITX)
+	OR	7			; CHAN 7 IS USED FOR DESELECTS
 #ELSE
 	AND	~SD_CS0
 #ENDIF
+#ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
 #IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
  #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
@@ -1953,9 +2008,9 @@ SD_DESELECT:
 	OUT	(SD_OPRREG),A
 	RET
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 ;
-; CSIO WAIT FOR TRANSMIT READY (TX REGSITER EMPTY)
+; CSIO WAIT FOR TRANSMIT READY (TX REGISTER EMPTY)
 ;
 SD_WAITTX:
 	IN0	A,(SD_CNTR)		; GET CSIO STATUS
@@ -1981,7 +2036,7 @@ SD_PUT:
 	OUT	(SD_WRTR),A
 #ELSE
 ;
-  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS, RESULT IN C
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	OUT0	(SD_TRDR),C		; PUT BYTE IN BUFFER
@@ -2059,7 +2114,7 @@ SD_GET:
 #IF (SDMODE == SDMODE_MT)
 	IN	A,(SD_RDTR)
 #ELSE
-  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+  #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	IN0	A,(SD_CNTR)		; GET CSIO STATUS
 	SET	5,A			; START RECEIVER
@@ -2153,7 +2208,7 @@ SD_GET1:
 ;
 ; SET CSIO TO DEFAULT SPEED
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
 ;
 SD_CSIO_DEF:
 	; SET CSIO FOR DEFAULT OPERATION
@@ -2406,7 +2461,7 @@ SD_DSKBUF	.DW	0		; ADR OF ACTIVE DISK BUFFER
 ; MSB<-->LSB MIRROR BITS IN A, RESULT IN C
 ;
 MIRROR:
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST)
 					; FASTEST BUT USES MOST CODE SPACE
 	LD	BC,MIRTAB		; 256 BYTE MIRROR TABLE
 	ADD	A,C			; ADD OFFSET
@@ -2439,7 +2494,7 @@ MIRROR2:
 ;
 ; LOOKUP TABLE TO MIRROR BITS IN A BYTE
 ;
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST)

 MIRTAB	.DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H
 	.DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H
--- a/Source/HBIOS/simrtc.asm
+++ b/Source/HBIOS/simrtc.asm
@@ -7,6 +7,10 @@ SIMRTC_IO	.EQU	$FE	; SIMH IO PORT
 SIMRTC_CLKREAD	.EQU	7	; READ CLOCK COMMAND
 SIMRTC_CLKWRITE	.EQU	8	; WRITE CLOCK COMMAND
 SIMRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+	.ECHO	"SIMRTC: IO="
+	.ECHO	SIMRTC_IO
+	.ECHO	"\n"
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -104,12 +104,12 @@ SIO1B_CMD	.EQU	SIO1BASE + $07
 SIO1B_DAT	.EQU	SIO1BASE + $05
  #ENDIF
 ;
-#IF (SIO1MODE == SIOMODE_Z80R)
-SIO1A_CMD	.EQU	SIO0BASE + $03
-SIO1A_DAT	.EQU	SIO0BASE + $01 
-SIO1B_CMD	.EQU	SIO0BASE + $02
-SIO1B_DAT	.EQU	SIO0BASE + $00
-#ENDIF
+  #IF (SIO1MODE == SIOMODE_Z80R)
+SIO1A_CMD	.EQU	SIO1BASE + $03
+SIO1A_DAT	.EQU	SIO1BASE + $01 
+SIO1B_CMD	.EQU	SIO1BASE + $02
+SIO1B_DAT	.EQU	SIO1BASE + $00
+  #ENDIF
 ;
 #ENDIF
 ;
@@ -1170,6 +1170,31 @@ SIO0A_CFG:
 	.DW	SIO0ACLK >> 16		; ... DWORD VALUE
 	.DB	SIO0ACTCC		; CTC CHANNEL
 	.DB	SIO0MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO0MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+
+#IF (SIO0MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO0BASE
+	.ECHO	", CHANNEL A"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@@ -1186,6 +1211,30 @@ SIO0B_CFG:
 	.DW	SIO0BCLK >> 16		; ... DWORD VALUE
 	.DB	SIO0BCTCC		; CTC CHANNEL
 	.DB	SIO0MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO0MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+#IF (SIO0MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO0MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO0BASE
+	.ECHO	", CHANNEL B"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 #IF (SIOCNT >= 2)
 ;
@@ -1202,6 +1251,31 @@ SIO1A_CFG:
 	.DW	SIO1ACLK >> 16		; ... DWORD VALUE
 	.DB	SIO1ACTCC		; CTC CHANNEL
 	.DB	SIO1MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO1MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+
+#IF (SIO1MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO1BASE
+	.ECHO	", CHANNEL A"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 	; SIO1 CHANNEL B
 SIO1B_CFG:
@@ -1216,6 +1290,30 @@ SIO1B_CFG:
 	.DW	SIO1BCLK >> 16		; ... DWORD VALUE
 	.DB	SIO1BCTCC		; CTC CHANNEL
 	.DB	SIO1MODE		; MODE
+;
+	.ECHO	"SIO MODE="
+#IF (SIO1MODE == SIOMODE_STD)
+	.ECHO	"STD"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_RC)
+	.ECHO	"RC"
+#ENDIF	
+#IF (SIO1MODE == SIOMODE_SMB)
+	.ECHO	"SMB"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_ZP)
+	.ECHO	"ZP"
+#ENDIF
+#IF (SIO1MODE == SIOMODE_Z80R)
+	.ECHO	"Z80R"
+#ENDIF
+	.ECHO	", IO="
+	.ECHO	SIO1BASE
+	.ECHO	", CHANNEL B"
+  #IF (INTMODE > 0)
+		.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+		.ECHO	"\n"
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -15,16 +15,29 @@
 ;======================================================================
 ; CONSTANTS
 ;======================================================================
+;
+
+	.ECHO	"SN76489 MODE="
 ;
 #IF (SNMODE == SNMODE_VGM)
 SN76489_PORT_LEFT	.EQU	$C6	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$C7	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
+	.ECHO	"VGM"
 #ENDIF
 ;
 #IF (SNMODE == SNMODE_RC)
 SN76489_PORT_LEFT	.EQU	$FF	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$FB	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
+	.ECHO	"RC"
 #ENDIF
+;
+	.ECHO	", IO_LEFT="
+	.ECHO	SN76489_PORT_LEFT
+	.ECHO	", IO_RIGHT="
+	.ECHO	SN76489_PORT_RIGHT
+	.ECHO	", CLOCK="
+	.ECHO	SN7CLK
+	.ECHO	" HZ\n"
 ;
 SN7_IDAT		.EQU	0
 SN7_TONECNT		.EQU	3	; COUNT NUMBER OF TONE CHANNELS
@@ -34,10 +47,6 @@ CHANNEL_0_SILENT	.EQU	$9F
 CHANNEL_1_SILENT	.EQU	$BF
 CHANNEL_2_SILENT	.EQU	$DF
 CHANNEL_3_SILENT	.EQU	$FF
-;
-	.ECHO	"SN76489 CLOCK: "
-	.ECHO	SN7CLK
-	.ECHO	"\n"
 ;
 #INCLUDE "audio.inc"
 ;
--- a/Source/HBIOS/spk.asm
+++ b/Source/HBIOS/spk.asm
@@ -40,6 +40,10 @@ SP_RTCIOMSK	.EQU	00000100B
 SP_PENDING_PERIOD	.DW	SP_NOTE_C8	; PENDING PERIOD (16 BITS)
 SP_PENDING_VOLUME	.DB	$FF		; PENDING VOL (8 BITS)
 SP_PENDING_DURATION	.DW	0		; PENDING DURATION (16 BITS)
+;
+	.ECHO	"SPK: IO="
+	.ECHO	RTCIO
+	.ECHO	"\n"
 ;
 ;======================================================================
 ;	DRIVER INITIALIZATION
@@ -303,6 +307,14 @@ BE_AGAIN:
 BE_END:
 	HB_EI
 	POP	IX
+;
+;	Above flow flips the speaker bit an odd number of times which
+;	leaves the bit set to the opposite value it started at.  This
+;	ensures that the bit is properly reset to its original value.
+;
+	LD	A,(HB_RTCVAL)		; Get the current RTC latch value
+	OUT	(RTCIO),A		; Set it
+;
 	RET				; ALWAYS EXITS WITH SUCCESS STATUS (A=0)
 ;
 ;======================================================================
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -197,6 +197,7 @@ SDMODE_MT	.EQU	9		; MT (Shift register SPI WIZNET for RCBUS)
 SDMODE_USR	.EQU	10		; USER DEFINED (in sd.asm) (NOT COMPLETE)
 SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
 SDMODE_Z80R	.EQU	12		; Z80 Retro
+SDMODE_EPITX	.EQU	13		; Mini ITX Z180
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;
@@ -506,6 +507,25 @@ CPUKHZ		.SET	CPUKHZ / 2	; Z180 PHI IS ALWAYS 1/2 OSC
 #ENDIF
 ;
 CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN MHZ
+;
+	.ECHO	"ASSUMED CPU SPEED: "
+	.ECHO	CPUKHZ
+	.ECHO	" KHZ\n"
+;
+	.ECHO	"INTERRUPTS: "
+#IF (INTMODE == 0)
+	.ECHO	"NONE"
+#ENDIF
+#IF (INTMODE == 1)
+	.ECHO	"MODE 1"
+#ENDIF
+#IF (INTMODE == 2)
+	.ECHO	"MODE 2"
+#ENDIF
+#IF (INTMODE == 3)
+	.ECHO	"MODE 3"
+#ENDIF
+	.ECHO	"\n"
 ;
 ; SYSTEM PERIODIC TIMER MODE
 ;
@@ -564,6 +584,62 @@ SYSTIM	.SET	TM_Z280
 ;
 #ENDIF
 ;
+#IF (BIOS == BIOS_WBW)
+	.ECHO	"DEFAULT SERIAL CONFIGURATION: "
+  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD9600
+	.ECHO	"9600"
+  #ENDIF
+  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD38400
+	.ECHO	"38400"
+  #ENDIF
+  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD57600
+	.ECHO	"57600"
+  #ENDIF
+  #IF ((DEFSERCFG & %1111100000000) == SER_BAUD115200
+	.ECHO	"115200"
+  #ENDIF
+	.ECHO	" BAUD\n"
+#ENDIF
+;
+;
+;
+#IF (BIOS == BIOS_WBW)
+	.ECHO	"MEMORY MANAGER: "
+  #IF (MEMMGR == MM_SBC)
+	.ECHO	"N8VEM (SBC)"
+  #ENDIF
+  #IF (MEMMGR == MM_Z2)
+	.ECHO	"ZETA 2 (Z2)"
+  #ENDIF
+  #IF (MEMMGR == MM_N8)
+	.ECHO	"N8 ONBOARD (N8)"
+  #ENDIF
+  #IF (MEMMGR == MM_Z180)
+	.ECHO	"Z180 NATIVE (Z180)"
+  #ENDIF
+  #IF (MEMMGR == MM_Z280)
+	.ECHO	"Z280 NATIVE (Z280)"
+  #ENDIF
+  #IF (MEMMGR == MM_ZRC)
+	.ECHO	"ZRC ONBOARD (ZRC)"
+  #ENDIF
+  #IF (MEMMGR == MM_MBC)
+	.ECHO	"NHYODYNE (MBC)"
+  #ENDIF
+  #IF (MEMMGR == MM_RPH)
+	.ECHO	"RHYOPHYRE ONBOARD (RPH)"
+  #ENDIF
+	.ECHO   "\n"
+#ENDIF
+;
+	.ECHO	"ROM SIZE: "
+	.ECHO	ROMSIZE
+	.ECHO	" KB\n"
+;
+	.ECHO	"RAM SIZE: "
+	.ECHO	RAMSIZE
+	.ECHO	" KB\n"
+;
 ; MEMORY BANK CONFIGURATION
 ;
 ROMBANKS	.EQU	(ROMSIZE / 32)			; TOTAL ROM BANKS
@@ -837,7 +913,7 @@ INT_CTC0A	.EQU	0	; ZILOG CTC 0, CHANNEL A
 INT_CTC0B	.EQU	1	; ZILOG CTC 0, CHANNEL B
 INT_CTC0C	.EQU	2	; ZILOG CTC 0, CHANNEL C
 INT_CTC0D	.EQU	3	; ZILOG CTC 0, CHANNEL D
-;INT_SIO0	.EQU	7	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO0	.EQU	6	; ZILOG SIO 0, CHANNEL A & B
 INT_SIO1	.EQU	8	; ZILOG SIO 1, CHANNEL A & B
 INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
 INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
--- a/Source/HBIOS/syq.asm
+++ b/Source/HBIOS/syq.asm
@@ -1446,6 +1446,17 @@ SYQ0_CFG:	; DEVICE 0
 	.DB	SYQ0BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"SYQ: MODE="
+  #IF (SYQMODE == SYQMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (SYQMODE == SYQMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	SYQ0BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF (SYQCNT >= 2)
@@ -1457,6 +1468,17 @@ SYQ1_CFG:	; DEVICE 1
 	.DB	SYQ1BASE		; IO BASE ADDRESS
 	.DW	0,0			; DEVICE CAPACITY
 	.DW	0,0			; CURRENT LBA
+;
+	.ECHO	"SYQ: MODE="
+  #IF (SYQMODE == SYQMODE_SPP)
+	.ECHO	"SPP"
+  #ENDIF
+  #IF (SYQMODE == SYQMODE_MG014)
+	.ECHO	"MG014"
+  #ENDIF
+	.ECHO	", IO="
+	.ECHO	SYQ1BASE
+	.ECHO	"\n"
 #ENDIF
 ;
 #IF ($ - SYQ_CFG) != (SYQCNT * SYQ_CFGSIZ)
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -1,9 +1,10 @@
 ;======================================================================
 ;	TM9918 AND V9958 VDU DRIVER
 ;
-;	WRITTEN BY: DOUGLAS GOODALL
-;	UPDATED BY: WAYNE WARTHEN -- 4/7/2013
-;       UPDATED BY: DEAN NETHERTON -- 5/26/2021 - V9958 SUPPORT
+; WRITTEN BY: DOUGLAS GOODALL
+; UPDATED BY: WAYNE WARTHEN -- 4/7/2013
+; UPDATED BY: DEAN NETHERTON -- 5/26/2021 - V9958 SUPPORT
+; UPDATED BY: JOSE L. COLLADO -- 11/15/2023 - MEMORY MAP CHANGES
 ;======================================================================
 ;
 ; TODO:
@@ -15,14 +16,34 @@
 ; TMS DRIVER - CONSTANTS
 ;======================================================================
 ;
-
+;
+;
+; 40 Column Video Memory Map
+; -----------------------------------
+;			Start	Length
+; Pattern Table:	$0000	$0800	Font data (8 x 256)
+; Unused:		$0800	$1000
+; Sprite Patterns:	$1800	$0800
+; Color Table:		$2000	$1800
+; Name Table:		$3800	$0400	Display characters (40 x 25)
+; Sprite Attributes:	$3B00	$0100
+; Unused:		$3C00	$0400
+;
+; 80 Column Video Memory Map (MSX like)
+; -------------------------------------
+;			Start	Length
+; Pattern Table:	$1000	$0800	Font data (8 x 256)
+; Sprite Patterns:	$????	$????
+; Color Table:		$????	$????
+; Name Table:		$0000	$0800	Display characters (80 x 25)
+; Sprite Attributes:	$????	$????
+; Unused:		$????	$????
+;
 TMSCTRL1:       .EQU   1               ; CONTROL BITS
 TMSINTEN:       .EQU   5               ; INTERRUPT ENABLE BIT
-
-#IF TMSTIMENABLE
-	.ECHO	"TMS INTERRUPTS ENABLED\n"
-#ENDIF
-
+;
+		.ECHO	"TMS: MODE="
+;
 #IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958))
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
@@ -30,24 +51,33 @@ TMS_PPIA	.EQU	0		; PPI PORT A
 TMS_PPIB	.EQU	0		; PPI PORT B
 TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+;
+  #IF (TMSMODE == TMSMODE_MSX)
+		.ECHO	"MSX"
+  #ENDIF
+  #IF (TMSMODE == TMSMODE_MSX9958)
+		.ECHO	"MSX9958"
+  #ENDIF
 #ENDIF
-
-#IF (TMSMODE == TMSMODE_COLECO))
+;
+#IF (TMSMODE == TMSMODE_COLECO)
 TMS_DATREG	.EQU	$BE		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$BF		; READ STATUS / WRITE REG SEL
 TMS_PPIA	.EQU	0		; PPI PORT A
 TMS_PPIB	.EQU	0		; PPI PORT B
 TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+		.ECHO	"COLECO"
 #ENDIF
-
+;
 #IF (TMSMODE == TMSMODE_MSXKBD)
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
 TMS_KBDDATA	.EQU	$E0		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$E1		; KBD CTLR STATUS/CMD PORT
+		.ECHO	"MSXKBD"
 #ENDIF
-
+;
 #IF (TMSMODE == TMSMODE_N8)
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
@@ -55,8 +85,9 @@ TMS_PPIA	.EQU	$84		; PPI PORT A
 TMS_PPIB	.EQU	$85		; PPI PORT B
 TMS_PPIC	.EQU	$86		; PPI PORT C
 TMS_PPIX	.EQU	$87		; PPI CONTROL PORT
+		.ECHO	"N8"
 #ENDIF
-
+;
 #IF (TMSMODE == TMSMODE_SCG)
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
@@ -65,10 +96,10 @@ TMS_PPIA	.EQU	0		; PPI PORT A
 TMS_PPIB	.EQU	0		; PPI PORT B
 TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
+		.ECHO	"SCG"
 #ENDIF
 ;
 #IF (TMSMODE == TMSMODE_MBC)
-
 TMS_DATREG	.EQU	$98		; READ/WRITE DATA
 TMS_CMDREG	.EQU	$99		; READ STATUS / WRITE REG SEL
 TMS_ACR		.EQU	$9C		; AUX CONTROL REGISTER
@@ -78,15 +109,29 @@ TMS_PPIC	.EQU	0		; PPI PORT C
 TMS_PPIX	.EQU	0		; PPI CONTROL PORT
 TMS_KBDDATA	.EQU	$E2		; KBD CTLR DATA PORT
 TMS_KBDST	.EQU	$E3		; KBD CTLR STATUS/CMD PORT
+		.ECHO	"MBC"
 #ENDIF
-
+;
+		.ECHO	", IO="
+		.ECHO	TMS_DATREG
+#IF TMSTIMENABLE
+		.ECHO	", INTERRUPTS ENABLED"
+#ENDIF
+		.ECHO	"\n"
+;
 TMS_ROWS	.EQU	24
-
+;
 #IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC))
 TMS_FNTVADDR	.EQU	$1000		; VRAM ADDRESS OF FONT DATA
+TMS_FNTSIZE	.EQU	8*256		; ### JLC Mod for JBL compatibility ### = 8x8 Font 256 Chars
+TMS_CHRVADDR	.EQU	$0000		; VRAM ADDRESS OF CHAR SCREEN DATA (NEW CONSTANT) = REG2 * $400
 TMS_COLS	.EQU	80
-#ELSE
-TMS_FNTVADDR	.EQU	$0800		; VRAM ADDRESS OF FONT DATA
+#ELSE					; ALL OTHER MODES...
+;TMS_FNTVADDR	.EQU	$0800		; VRAM ADDRESS OF FONT DATA
+TMS_FNTVADDR	.EQU	$0000		; VRAM ADDRESS OF FONT DATA ### JLC Mod for JBL compatibility ### = REG4 * $800
+TMS_FNTSIZE	.EQU	8*256		; ### JLC Mod for JBL compatibility ### = 8x8 Font 256 Chars
+; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
+TMS_CHRVADDR	.EQU	$3800		; VRAM ADDRESS OF CHAR SCREEN DATA (NEW CONSTANT) = REG2 * $400
 TMS_COLS	.EQU	40
 #ENDIF
 ;
@@ -99,15 +144,16 @@ TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 ; IF YOU SEE SCREEN CORRUPTION, ADJUST THIS!!!
 ;
 #IF (CPUFAM == CPU_Z180)
-; BELOW WAS TUNED FOR Z180 AT 18MHZ
-#DEFINE		TMS_IODELAY	EX (SP),HL \ EX (SP),HL	; 38 W/S
+  ; BELOW WAS TUNED FOR Z180 AT 18MHZ
+  #DEFINE	TMS_IODELAY	EX (SP),HL \ EX (SP),HL	; 38 W/S
+  ;#DEFINE	TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP ; 20 W/S ### JLC Mod for Clock/2 (9 MHz) ###
 #ELSE
-; BELOW WAS TUNED FOR SBC AT 8MHZ
-#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC))
-#DEFINE		TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP ; V9958 NEEDS AT WORST CASE, APPROX 4us (28T) DELAY BETWEEN I/O (WHEN IN TEXT MODE)
-#ELSE
-#DEFINE		TMS_IODELAY	NOP \ NOP ; 8 W/S
-#ENDIF
+  ; BELOW WAS TUNED FOR SBC AT 8MHZ
+  #IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC))
+    #DEFINE	TMS_IODELAY	NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP ; V9958 NEEDS AT WORST CASE, APPROX 4us (28T) DELAY BETWEEN I/O (WHEN IN TEXT MODE)
+  #ELSE
+    #DEFINE	TMS_IODELAY	NOP \ NOP ; 8 W/S
+  #ENDIF
 #ENDIF
 ;
 ;======================================================================
@@ -155,6 +201,9 @@ TMS_INIT:
 #IF (TMSMODE == TMSMODE_MSX)
 	PRTS("MSX$")
 #ENDIF
+#IF (TMSMODE == TMSMODE_COLECO)		; ### JLC Mod for completeness ###
+	PRTS("COLECO$")
+#ENDIF
 #IF (TMSMODE == TMSMODE_MSXKBD)
 	PRTS("RCKBD$")
 #ENDIF
@@ -166,9 +215,10 @@ TMS_INIT:
 	LD	A,TMS_DATREG
 	CALL	PRTHEXBYTE
 	CALL	TMS_PROBE		; CHECK FOR HW EXISTENCE
+	;JP	TMS_INIT1		; ### JLC DEBUG: ALLWAYS CONTINUE ###
 	JR	Z,TMS_INIT1		; CONTINUE IF PRESENT
 ;
-	; HARDWARE NOT PRESENT
+	; *** HARDWARE NOT PRESENT ***
 	PRTS(" NOT PRESENT$")
 	OR	$FF			; SIGNAL FAILURE
 	RET
@@ -193,9 +243,9 @@ TMS_INIT1:
 	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST

 	LD	A, (TMS_INITVDU_REG_1)
-        SET	TMSINTEN, A             ; SET INTERRUPT ENABLE BIT
-	LD	(TMS_INITVDU_REG_1), A
-        LD	C, TMSCTRL1
+	SET	TMSINTEN,A		; SET INTERRUPT ENABLE BIT
+	LD	(TMS_INITVDU_REG_1),A
+	LD	C, TMSCTRL1
 	CALL	TMS_SET
 #ENDIF
 ;
@@ -266,11 +316,11 @@ TMS_VDAINI:
 	RET

 TMS_VDAQRY:
-	LD	C,$00		; MODE ZERO IS ALL WE KNOW
-	LD	D,TMS_ROWS	; ROWS
-	LD	E,TMS_COLS	; COLS
-	LD	HL,0		; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED YET
-	XOR	A		; SIGNAL SUCCESS
+	LD	C,$00			; MODE ZERO IS ALL WE KNOW
+	LD	D,TMS_ROWS		; ROWS
+	LD	E,TMS_COLS		; COLS
+	LD	HL,0			; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED YET
+	XOR	A			; SIGNAL SUCCESS
 	RET

 TMS_VDARES:
@@ -294,11 +344,11 @@ TMS_VDARES1:	; ENTRY POINT TO AVOID TMS_Z180IO RECURSION
 	RET

 TMS_VDADEV:
-	LD	D,VDADEV_TMS	; D := DEVICE TYPE
-	LD	E,0		; E := PHYSICAL UNIT IS ALWAYS ZERO
-	LD	H,TMSMODE	; H := MODE
-	LD	L,TMS_DATREG	; L := BASE I/O ADDRESS
-	XOR	A		; SIGNAL SUCCESS
+	LD	D,VDADEV_TMS		; D := DEVICE TYPE
+	LD	E,0			; E := PHYSICAL UNIT IS ALWAYS ZERO
+	LD	H,TMSMODE		; H := MODE
+	LD	L,TMS_DATREG		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
 	RET

 TMS_VDASCS:
@@ -310,28 +360,28 @@ TMS_VDASCP:
 	CALL	TMS_Z180IO
 #ENDIF
 	CALL	TMS_CLRCUR
-	CALL	TMS_XY		; SET CURSOR POSITION
+	CALL	TMS_XY			; SET CURSOR POSITION
 	CALL	TMS_SETCUR
-	XOR	A		; SIGNAL SUCCESS
+	XOR	A			; SIGNAL SUCCESS
 	RET

 TMS_VDASAT:
-	XOR	A		; NOT POSSIBLE, JUST SIGNAL SUCCESS
+	XOR	A			; NOT POSSIBLE, JUST SIGNAL SUCCESS
 	RET

 TMS_VDASCO:
-	XOR	A		; NOT POSSIBLE, JUST SIGNAL SUCCESS
+	XOR	A			; NOT POSSIBLE, JUST SIGNAL SUCCESS
 	RET

 TMS_VDAWRC:
 #IF (CPUFAM == CPU_Z180)
 	CALL	TMS_Z180IO
 #ENDIF
-	CALL	TMS_CLRCUR	; CURSOR OFF
-	LD	A,E		; CHARACTER TO WRITE GOES IN A
-	CALL	TMS_PUTCHAR	; PUT IT ON THE SCREEN
+	CALL	TMS_CLRCUR		; CURSOR OFF
+	LD	A,E			; CHARACTER TO WRITE GOES IN A
+	CALL	TMS_PUTCHAR		; PUT IT ON THE SCREEN
 	CALL	TMS_SETCUR
-	XOR	A		; SIGNAL SUCCESS
+	XOR	A			; SIGNAL SUCCESS
 	RET

 TMS_VDAFIL:
@@ -339,11 +389,11 @@ TMS_VDAFIL:
 	CALL	TMS_Z180IO
 #ENDIF
 	CALL	TMS_CLRCUR
-	LD	A,E		; FILL CHARACTER GOES IN A
-	EX	DE,HL		; FILL LENGTH GOES IN DE
-	CALL	TMS_FILL	; DO THE FILL
+	LD	A,E			; FILL CHARACTER GOES IN A
+	EX	DE,HL			; FILL LENGTH GOES IN DE
+	CALL	TMS_FILL		; DO THE FILL
 	CALL	TMS_SETCUR
-	XOR	A		; SIGNAL SUCCESS
+	XOR	A			; SIGNAL SUCCESS
 	RET

 TMS_VDACPY:
@@ -353,11 +403,11 @@ TMS_VDACPY:
 	CALL	TMS_CLRCUR
 	; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS TMS_POS
 	; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT
-	PUSH	HL		; SAVE LENGTH
-	CALL	TMS_XY2IDX	; ROW/COL IN DE -> SOURCE ADR IN HL
-	POP	BC		; RECOVER LENGTH IN BC
-	LD	DE,(TMS_POS)	; PUT DEST IN DE
-	CALL	TMS_BLKCPY	; DO A BLOCK COPY
+	PUSH	HL			; SAVE LENGTH
+	CALL	TMS_XY2IDX		; ROW/COL IN DE -> SOURCE ADR IN HL
+	POP	BC			; RECOVER LENGTH IN BC
+	LD	DE,(TMS_POS)		; PUT DEST IN DE
+	CALL	TMS_BLKCPY		; DO A BLOCK COPY
 	CALL	TMS_SETCUR
 	XOR	A
 	RET
@@ -368,20 +418,20 @@ TMS_VDASCR:
 #ENDIF
 	CALL	TMS_CLRCUR
 TMS_VDASCR0:
-	LD	A,E		; LOAD E INTO A
-	OR	A		; SET FLAGS
-	JR	Z,TMS_VDASCR2	; IF ZERO, WE ARE DONE
-	PUSH	DE		; SAVE E
-	JP	M,TMS_VDASCR1	; E IS NEGATIVE, REVERSE SCROLL
-	CALL	TMS_SCROLL	; SCROLL FORWARD ONE LINE
-	POP	DE		; RECOVER E
-	DEC	E		; DECREMENT IT
-	JR	TMS_VDASCR0	; LOOP
+	LD	A,E			; LOAD E INTO A
+	OR	A			; SET FLAGS
+	JR	Z,TMS_VDASCR2		; IF ZERO, WE ARE DONE
+	PUSH	DE			; SAVE E
+	JP	M,TMS_VDASCR1		; E IS NEGATIVE, REVERSE SCROLL
+	CALL	TMS_SCROLL		; SCROLL FORWARD ONE LINE
+	POP	DE			; RECOVER E
+	DEC	E			; DECREMENT IT
+	JR	TMS_VDASCR0		; LOOP
 TMS_VDASCR1:
-	CALL	TMS_RSCROLL	; SCROLL REVERSE ONE LINE
-	POP	DE		; RECOVER E
-	INC	E		; INCREMENT IT
-	JR	TMS_VDASCR0	; LOOP
+	CALL	TMS_RSCROLL		; SCROLL REVERSE ONE LINE
+	POP	DE			; RECOVER E
+	INC	E			; INCREMENT IT
+	JR	TMS_VDASCR0		; LOOP
 TMS_VDASCR2:
 	CALL	TMS_SETCUR
 	XOR	A
@@ -393,23 +443,23 @@ TMS_VDASCR2:
 ;----------------------------------------------------------------------

 TMS_VDARDC:
-	OR	$FF		; UNSUPPORTED FUNCTION
+	OR	$FF			; UNSUPPORTED FUNCTION
 	RET

 ; DUMMY FUNCTIONS BELOW BECAUSE SCG BOARD HAS NO
 ; KEYBOARD INTERFACE

 TMS_STAT:
-	XOR	A		; SIGNAL NOTHING READY
-	JP	CIO_IDLE	; DO IDLE PROCESSING
+	XOR	A			; SIGNAL NOTHING READY
+	JP	CIO_IDLE		; DO IDLE PROCESSING

 TMS_FLUSH:
-	XOR	A		; SIGNAL SUCCESS
+	XOR	A			; SIGNAL SUCCESS
 	RET

 TMS_READ:
-	LD	E,26		; RETURN <SUB> (CTRL-Z)
-	XOR	A		; SIGNAL SUCCESS
+	LD	E,26			; RETURN <SUB> (CTRL-Z)
+	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
 ;======================================================================
@@ -469,7 +519,7 @@ TMS_RD:
 ; ON RETURN, ZF SET INDICATES HARDWARE FOUND
 ;
 TMS_PROBE:
-	; SET WRITE ADDRESS TO $0
+	; SET WRITE ADDRESS TO $0000
 	LD	HL,0
 	CALL	TMS_WR
 	; WRITE TEST PATTERN TO FIRST TWO BYTES
@@ -481,19 +531,18 @@ TMS_PROBE:
 	OUT	(TMS_DATREG),A		; SECOND BYTE
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
-	; SET READ ADDRESS TO $0
+;
+	; SET READ ADDRESS TO $0000
 	LD	HL,0
 	CALL	TMS_RD
 	; READ TEST PATTERN
 	LD	C,$A5			; VALUE TO EXPECT
 	IN	A,(TMS_DATREG)		; READ FIRST BYTE
-	;CALL	PRTHEXBYTE
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
 	CP	C			; COMPARE
 	RET	NZ			; RETURN ON MISCOMPARE
 	IN	A,(TMS_DATREG)		; READ SECOND BYTE
-	;CALL	PRTHEXBYTE
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
 	CPL				; COMPLEMENT IT
@@ -505,12 +554,12 @@ TMS_PROBE:
 ;----------------------------------------------------------------------
 ;
 TMS_CRTINIT:
-	; SET WRITE ADDRESS TO $0
+	; SET WRITE ADDRESS TO $0000 Beginning of VRAM
 	LD	HL,0
 	CALL	TMS_WR
 ;
-	; FILL ENTIRE RAM CONTENTS
-	LD	DE,$4000
+	; FILL ENTIRE 16KB VRAM CONTENTS with $00 ### JLC Comment fix ###
+	LD	DE,$4000		; 16KB
 TMS_CRTINIT1:
 	XOR	A
 	OUT	(TMS_DATREG),A
@@ -521,9 +570,9 @@ TMS_CRTINIT1:
 	JR	NZ,TMS_CRTINIT1
 ;
 	; INITIALIZE VDU REGISTERS
-    	LD 	C,0			; START WITH REGISTER 0
+	LD 	C,0			; START WITH REGISTER 0
 	LD	B,TMS_INITVDULEN	; NUMBER OF REGISTERS TO INIT
-    	LD 	HL,TMS_INITVDU		; HL = POINTER TO THE DEFAULT VALUES
+	LD 	HL,TMS_INITVDU		; HL = POINTER TO THE DEFAULT VALUES
 TMS_CRTINIT2:
 	LD	A,(HL)			; GET VALUE
 	CALL	TMS_SET			; WRITE IT
@@ -565,7 +614,7 @@ TMS_LOADFONT:
 #ENDIF
 ;
 	; FILL TMS_FNTVADDR BYTES FROM FONTDATA
-	LD	DE,TMS_FNTVADDR
+	LD	DE,TMS_FNTSIZE		; ### JLC Mod for JBL compatibility ###
 TMS_LOADFONT1:
 	LD	A,(HL)
 	OUT	(TMS_DATREG),A
@@ -622,20 +671,20 @@ TMS_SETCUR:
 	LD	HL,0			; ZERO HL
 	LD	L,A			; HL IS NOW RAW CHAR INDEX
 	LD	B,3			; LEFT SHIFT BY 3 BITS
-TMS_SETCUR0:	; MULT BY 8 FOR FONT INDEX
+TMS_SETCUR0:				; MULT BY 8 FOR FONT INDEX
 	SLA	L			; SHIFT LSB INTO CARRY
 	RL	H			; SHFT MSB FROM CARRY
 	DJNZ	TMS_SETCUR0		; LOOP 3 TIMES
-	LD	DE,TMS_FNTVADDR			; OFFSET TO START OF FONT TABLE
+	LD	DE,TMS_FNTVADDR		; OFFSET TO START OF FONT TABLE
 	ADD	HL,DE			; ADD TO FONT INDEX
 	CALL	TMS_RD			; SETUP TO READ GLYPH
 	LD	B,8			; 8 BYTES
 	LD	HL,TMS_BUF		; INTO BUFFER
-TMS_SETCUR1:	; READ GLYPH LOOP
+TMS_SETCUR1:				; READ GLYPH LOOP
 	IN	A,(TMS_DATREG)		; GET NEXT BYTE
 	TMS_IODELAY			; IO DELAY
 	LD	(HL),A			; SAVE VALUE IN BUF
-	INC	HL			; BUMP BUF POINTER
+	INC	HL					; BUMP BUF POINTER
 	DJNZ	TMS_SETCUR1		; LOOP FOR 8 BYTES
 ;
 	; NOW WRITE INVERTED GLYPH INTO FONT INDEX 255
@@ -643,7 +692,7 @@ TMS_SETCUR1:	; READ GLYPH LOOP
 	CALL	TMS_WR			; SETUP TO WRITE THE INVERTED GLYPH
 	LD	B,8			; 8 BYTES PER GLYPH
 	LD	HL,TMS_BUF		; POINT TO BUFFER
-TMS_SETCUR2:	; WRITE INVERTED GLYPH LOOP
+TMS_SETCUR2:				; WRITE INVERTED GLYPH LOOP
 	LD	A,(HL)			; GET THE BYTE
 	INC	HL			; BUMP THE BUF POINTER
 	XOR	$FF			; INVERT THE VALUE
@@ -689,6 +738,9 @@ TMS_XY2IDX:
 	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET
 	LD	E,A			; GET COLUMN BACK
 	ADD	HL,DE			; ADD IT IN
+	; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
+	LD	DE,TMS_CHRVADDR		; Add offset Address to start of Name Table (Char)
+	ADD	HL,DE
 	RET				; RETURN
 ;
 ;----------------------------------------------------------------------
@@ -735,10 +787,11 @@ TMS_FILL1:
 ;----------------------------------------------------------------------
 ;
 TMS_SCROLL:
-	LD	HL,0			; SOURCE ADDRESS OF CHARACER BUFFER
+	; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
+	LD	HL,TMS_CHRVADDR		; SOURCE ADDRESS OF CHARACTER BUFFER
 	LD	C,TMS_ROWS - 1		; SET UP LOOP COUNTER FOR ROWS - 1
 ;
-TMS_SCROLL0:	; READ LINE THAT IS ONE PAST CURRENT DESTINATION
+TMS_SCROLL0:				; READ LINE THAT IS ONE PAST CURRENT DESTINATION
 	PUSH	HL			; SAVE CURRENT DESTINATION
 	LD	DE,TMS_COLS
 	ADD	HL,DE			; POINT TO NEXT ROW SOURCE
@@ -786,7 +839,10 @@ TMS_SCROLL3:
 ;----------------------------------------------------------------------
 ;
 TMS_RSCROLL:
+	; ### JLC Fix to allow Name Table Addresses other than $0000 and JBL Compatibility ###
 	LD	HL,TMS_COLS * (TMS_ROWS - 1)
+	LD	DE,TMS_CHRVADDR		; Add offset Address to start of Name Table (Char)
+	ADD	HL,DE
 	LD	C,TMS_ROWS - 1
 ;
 TMS_RSCROLL0:	; READ THE LINE THAT IS ONE PRIOR TO CURRENT DESTINATION
@@ -838,33 +894,33 @@ TMS_RSCROLL3:
 ;
 TMS_BLKCPY:
 	; SAVE DESTINATION AND LENGTH
-	PUSH	BC		; LENGTH
-	PUSH	DE		; DEST
+	PUSH	BC			; LENGTH
+	PUSH	DE			; DEST
 ;
 	; READ FROM THE SOURCE LOCATION
 TMS_BLKCPY1:
-	CALL	TMS_RD		; SET UP TO READ FROM ADDRESS IN HL
-	LD	DE,TMS_BUF	; POINT TO BUFFER
+	CALL	TMS_RD			; SET UP TO READ FROM ADDRESS IN HL
+	LD	DE,TMS_BUF		; POINT TO BUFFER
 	LD	B,C
 TMS_BLKCPY2:
-	IN	A,(TMS_DATREG)	; GET THE NEXT BYTE
-	TMS_IODELAY		; DELAY
-	LD	(DE),A		; SAVE IN BUFFER
-	INC	DE		; BUMP BUF PTR
-	DJNZ	TMS_BLKCPY2	; LOOP AS NEEDED
+	IN	A,(TMS_DATREG)		; GET THE NEXT BYTE
+	TMS_IODELAY			; DELAY
+	LD	(DE),A			; SAVE IN BUFFER
+	INC	DE			; BUMP BUF PTR
+	DJNZ	TMS_BLKCPY2		; LOOP AS NEEDED
 ;
 	; WRITE TO THE DESTINATION LOCATION
-	POP	HL		; RECOVER DESTINATION INTO HL
-	CALL	TMS_WR		; SET UP TO WRITE
-	LD	DE,TMS_BUF	; POINT TO BUFFER
-	POP	BC		; GET LOOP COUNTER BACK
+	POP	HL			; RECOVER DESTINATION INTO HL
+	CALL	TMS_WR			; SET UP TO WRITE
+	LD	DE,TMS_BUF		; POINT TO BUFFER
+	POP	BC			; GET LOOP COUNTER BACK
 	LD	B,C
 TMS_BLKCPY3:
-	LD	A,(DE)		; GET THE CHAR FROM BUFFER
-	OUT	(TMS_DATREG),A	; WRITE TO VDU
-	TMS_IODELAY		; DELAY
-	INC	DE		; BUMP BUF PTR
-	DJNZ	TMS_BLKCPY3	; LOOP AS NEEDED
+	LD	A,(DE)			; GET THE CHAR FROM BUFFER
+	OUT	(TMS_DATREG),A		; WRITE TO VDU
+	TMS_IODELAY			; DELAY
+	INC	DE			; BUMP BUF PTR
+	DJNZ	TMS_BLKCPY3		; LOOP AS NEEDED
 ;
 	RET
 ;
@@ -915,7 +971,7 @@ TMS_INTHNDL:
 ;	CALL	MKY_INT
 ;#ENDIF

-	CALL	HB_TIMINT	; RETURN NZ - HANDLED
+	CALL	HB_TIMINT		; RETURN NZ - HANDLED
 	OR	$FF
 	RET
 #ENDIF
@@ -924,28 +980,27 @@ TMS_INTHNDL:
 ;   TMS DRIVER - DATA
 ;==================================================================================================
 ;
-TMS_POS		.DW 	0	; CURRENT DISPLAY POSITION
-TMS_CURSAV	.DB	0	; SAVES ORIGINAL CHARACTER UNDER CURSOR
-TMS_BUF		.FILL	256,0	; COPY BUFFER
+TMS_POS		.DW 	0		; CURRENT DISPLAY POSITION
+TMS_CURSAV	.DB	0		; SAVES ORIGINAL CHARACTER UNDER CURSOR
+TMS_BUF		.FILL	256,0		; COPY BUFFER

 ;
 ;==================================================================================================
 ;   TMS DRIVER - INSTANCE DATA
 ;==================================================================================================
 ;
-
 TMS_IDAT:
 #IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_N8) | (TMSMODE == TMSMODE_SCG))
-	.DB	TMS_PPIA	; PPI PORT A
-	.DB	TMS_PPIB        ; PPI PORT B
-	.DB	TMS_PPIC        ; PPI PORT C
-	.DB	TMS_PPIX        ; PPI CONTROL PORT
+	.DB	TMS_PPIA		; PPI PORT A
+	.DB	TMS_PPIB		; PPI PORT B
+	.DB	TMS_PPIC		; PPI PORT C
+	.DB	TMS_PPIX		; PPI CONTROL PORT
 #ENDIF
 #IF ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC))
-	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
-	.DB	TMS_KBDST	; 8242 CMD/STATUS PORT
-	.DB	TMS_KBDDATA	; 8242 DATA PORT
-	.DB	0		; FILLER
+	.DB	KBDMODE_PS2		; PS/2 8242 KEYBOARD CONTROLLER
+	.DB	TMS_KBDST		; 8242 CMD/STATUS PORT
+	.DB	TMS_KBDDATA		; 8242 DATA PORT
+	.DB	0			; FILLER
 #ENDIF
 ;
 	.DB	TMS_DATREG
@@ -958,8 +1013,8 @@ TMS_IDAT:
 ; Control Registers (write CMDREG):
 ;
 ; Reg	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	Description
-; 0	-	-	-	-	-	-	M2	EXTVID
-; 1	4/16K	BL	GINT	M1	M3	-	SI	MAG
+; 0	-	-	-	-	-	-	M3	EXTVID
+; 1	4/16K	BL	GINT	M1	M2	-	SI	MAG
 ; 2	-	-	-	-	PN13	PN12	PN11	PN10
 ; 3	CT13	CT12	CT11	CT10	CT9	CT8	CT7	CT6
 ; 4	-	-	-	-	-	PG13	PG12	PG11
@@ -994,32 +1049,50 @@ TMS_IDAT:
 ; INT		Set at each screen update, used for interrupts.
 ;
 #IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC))
-TMS_INITVDU:
-	.DB	$04		; REG 0 - NO EXTERNAL VID, SET M4 = 1
+;
+; NOTE: YAMAHA 9938/58 DOCUMENTATION SAYS R3 IS SAME AS 9918 (ADR >> 10),
+; BUT THIS SEEMS TO BE WRONG AND CORRECTLY DOCUMENTED AT
+; https://www.msx.org/wiki/Screen_Modes_Description#SCREEN_0_in_80-column_.28Text_mode_2.29
+; BITS 1-0 SHOULD BE 1.  BITS 8-2 SHOULD BE (ADR >> 8).
+;
+TMS_INITVDU:	; V9958 REGISTER SET
+	.DB	$04		; REG 0 - NO EXTERNAL VID, SET M4 = 1 FOR 80 COLS
 TMS_INITVDU_REG_1:
-	.DB	$50		; REG 1 - ENABLE SCREEN, SET MODE 1
-	.DB	$03		; REG 2 - PATTERN NAME TABLE := 0
+	.DB	$50		; REG 1 - ENABLE SCREEN, SET M1
+	.DB	$03		; REG 2 - SET PATTERN NAME TABLE TO (TMS_CHRVADDR >> 8) | $03
 	.DB	$00		; REG 3 - NO COLOR TABLE
 	.DB	$02		; REG 4 - SET PATTERN GENERATOR TABLE TO (TMS_FNTVADDR -> $1000)
 	.DB	$00		; REG 5 - SPRITE ATTRIBUTE IRRELEVANT
 	.DB	$00		; REG 6 - NO SPRITE GENERATOR TABLE
 	.DB	$F0		; REG 7 - WHITE ON BLACK
-
 	.DB	$88		; REG 8 - COLOUR BUS INPUT, DRAM 64K
 	.DB	$00		; REG 9
 	.DB	$00		; REG 10 - COLOUR TABLE A14-A16 (TMS_FNTVADDR - $1000)
-
-#ELSE ; TMS REGISTER SET
-TMS_INITVDU:
-	.DB	$00		; REG 0 - NO EXTERNAL VID
+;
+#ELSE 		; _______TMS9918 REGISTER SET ### JLC Mod for JBL compatibility & MODE II Readiness ###_______
+;
+TMS_INITVDU:	; V9918 REGISTER SET
+	.DB	$00		; REG 0 - SET TEXT MODE, NO EXTERNAL VID
 TMS_INITVDU_REG_1:
-	.DB	$50		; REG 1 - ENABLE SCREEN, SET MODE 1
-	.DB	$00		; REG 2 - PATTERN NAME TABLE := 0
-	.DB	$00		; REG 3 - NO COLOR TABLE
-	.DB	$01		; REG 4 - SET PATTERN GENERATOR TABLE TO (TMS_FNTVADDR -> $0800)
-	.DB	$00		; REG 5 - SPRITE ATTRIBUTE IRRELEVANT
-	.DB	$00		; REG 6 - NO SPRITE GENERATOR TABLE
-	.DB	$F0		; REG 7 - WHITE ON BLACK
+	.DB	$D0		; REG 1 - SET 16K VRAM, ENABLE SCREEN, NO INTERRUPTS, TEXT MODE ($50 TO BLANK SCREEN)
+	.DB	$0E		; REG 2 - SET PATTERN NAME TABLE TO (TMS_CHRVADDR >> 10)
+	.DB	$FF		; REG 3 - NO COLOR TABLE, SET TO MODE II DEFAULT VALUE
+	.DB	$00		; REG 4 - SET PATTERN GENERATOR TABLE TO (TMS_FNTVADDR -> $0000)
+	.DB	$76		; REG 5 - SPRITE ATTRIBUTE IRRELEVANT, SET TO MODE II DEFAULT VALUE
+	.DB	$03		; REG 6 - NO SPRITE GENERATOR TABLE, SET TO MODE II DEFAULT VALUE
+	.DB	$E1		; REG 7 - GREY ON BLACK ### JLC Mod Change default text color for better readability YMMV ###
+;
+;TMS_INITVDU:
+;	.DB	$00		; REG 0 - NO EXTERNAL VID
+;TMS_INITVDU_REG_1:
+;	.DB	$50		; REG 1 - ENABLE SCREEN, SET TEXT MODE & BLANK SCREEN ### JLC comment fix (NOT MODE 1) ###
+;	.DB	$00		; REG 2 - PATTERN NAME TABLE := 0
+;	.DB	$00		; REG 3 - NO COLOR TABLE
+;	.DB	$01		; REG 4 - SET PATTERN GENERATOR TABLE TO (TMS_FNTVADDR -> $0800)
+;	.DB	$00		; REG 5 - SPRITE ATTRIBUTE IRRELEVANT
+;	.DB	$00		; REG 6 - NO SPRITE GENERATOR TABLE
+;	.DB	$F0		; REG 7 - WHITE ON TRANSPARENT
+;
 #ENDIF
 ;
 TMS_INITVDULEN	.EQU	$ - TMS_INITVDU
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@@ -59,11 +59,16 @@ UARTSBASE		.EQU	$58
 #ELSE
 UARTSBASE		.EQU	$68
 #ENDIF
+UARTABASE		.EQU	$A8
 UARTCBASE		.EQU	$80
 UARTMBASE		.EQU	$18
 UART4BASE		.EQU	$C0
 UARTRBASE		.EQU	$A0
+#IF (PLATFORM == PLT_DUO)
+UARTDBASE		.EQU	$70
+#ELSE
 UARTDBASE		.EQU	$80
+#ENDIF
 ;
 #IF (UARTINTS)
 ;
@@ -1036,6 +1041,27 @@ UART_CFG_SBC:
 	.DB	UARTSBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	UARTSBC_RCVBUF			; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"UART: MODE=SBC, IO="
+	.ECHO	UARTSBASE
+  #IF ((UARTINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+	.ECHO	"\n"
+#ENDIF
+#IF (UARTAUX)
+UART_CFG_AUX:
+	; AUX SERIAL PORT
+	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
+	.DB	0				; UART TYPE
+	.DB	UARTABASE			; IO PORT BASE (RBR, THR)
+	.DB	UARTABASE + UART_LSR		; LINE STATUS PORT (LSR)
+	.DW	UARTCFG				; LINE CONFIGURATION
+	.DW	0				; NO INT HANDLER
+;
+	.ECHO	"UART: MODE=AUX, IO="
+	.ECHO	UARTABASE
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTCAS)
 UART_CFG_CAS:
@@ -1046,6 +1072,13 @@ UART_CFG_CAS:
 	.DB	UARTCBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCASSPD			; LINE CONFIGURATION
 	.DW	UARTCAS_RCVBUF			; POINTER TO RCV BUFFER STRUCT
+;
+	.ECHO	"UART: MODE=CAS, IO="
+	.ECHO	UARTCBASE
+  #IF ((UARTINTS) & (INTMODE > 0))
+	.ECHO	", INTERRUPTS ENABLED"
+  #ENDIF
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTMFP)
 UART_CFG_MFP:
@@ -1056,6 +1089,10 @@ UART_CFG_MFP:
 	.DB	UARTMBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=MFP, IO="
+	.ECHO	UARTSBASE
+	.ECHO	"\n"
 #ENDIF
 #IF (UART4)
 	; 4UART SERIAL PORT A
@@ -1065,6 +1102,11 @@ UART_CFG_MFP:
 	.DB	UART4BASE+0 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+0
+	.ECHO	"\n"
+;
 	; 4UART SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1072,6 +1114,11 @@ UART_CFG_MFP:
 	.DB	UART4BASE+8 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+8
+	.ECHO	"\n"
+;
 	; 4UART SERIAL PORT C
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1079,6 +1126,11 @@ UART_CFG_MFP:
 	.DB	UART4BASE+16 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+16
+	.ECHO	"\n"
+;
 	; 4UART SERIAL PORT D
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1086,6 +1138,10 @@ UART_CFG_MFP:
 	.DB	UART4BASE+24 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=4UART, IO="
+	.ECHO	UART4BASE+24
+	.ECHO	"\n"
 #ENDIF
 #IF (UARTRC)
 	; UARTRC SERIAL PORT A
@@ -1095,6 +1151,11 @@ UART_CFG_MFP:
 	.DB	UARTRBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=RC, IO="
+	.ECHO	UARTRBASE+0
+	.ECHO	"\n"
+;
 	; UARTRC SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1102,6 +1163,11 @@ UART_CFG_MFP:
 	.DB	UARTRBASE+8 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=RC, IO="
+	.ECHO	UARTRBASE+8
+	.ECHO	"\n"
+;
 #ENDIF
 #IF (UARTDUAL)
 	; DUAL UART CHANNEL A
@@ -1111,6 +1177,11 @@ UART_CFG_MFP:
 	.DB	UARTDBASE + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=DUAL, IO="
+	.ECHO	UARTDBASE+0
+	.ECHO	"\n"
+;
 	; DUAL UART CHANNEL B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@@ -1118,6 +1189,11 @@ UART_CFG_MFP:
 	.DB	UARTDBASE+8 + UART_LSR		; LINE STATUS PORT (LSR)
 	.DW	UARTCFG				; LINE CONFIGURATION
 	.DW	0				; SHOULD NEVER NEED INT HANDLER
+;
+	.ECHO	"UART: MODE=DUAL, IO="
+	.ECHO	UARTDBASE+8
+	.ECHO	"\n"
+;
 #ENDIF
 ;
 UART_CNT	.EQU	($ - UART_CFG) / 8
--- a/Source/HBIOS/uf.asm
+++ b/Source/HBIOS/uf.asm
@@ -23,6 +23,10 @@ UF_USB_ACTIVE	.DB	0		; USB CABLE CONNECTED STATUS FLAG
 ; DEVICE DESCRIPTION TABLE
 ;
 UF_CFG:	.DW	SER_9600_8N1		; DUMMY CONFIGURATION
+;
+	.ECHO	"USB-FIFO: IO="
+	.ECHO	UFBASE
+	.ECHO	"\n"
 ;
 ; SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE
 ;
--- a/Source/HBIOS/util.asm
+++ b/Source/HBIOS/util.asm
@@ -407,8 +407,8 @@ XREGDMP:

 	LD	(REGDMP_SP),SP		; SAVE STACK POINTER

-	;LD	(RD_STKSAV),SP		; SAVE ORIGINAL STACK POINTER
-	;LD	SP,RD_STACK		; SWITCH TO PRIVATE STACK
+	LD	(RD_STKSAV),SP		; SAVE ORIGINAL STACK POINTER
+	LD	SP,RD_STACK		; SWITCH TO PRIVATE STACK

 	PUSH	AF
 	PUSH	BC
@@ -462,7 +462,7 @@ XREGDMP:
 	POP	BC
 	POP	AF

-	;LD	SP,(RD_STKSAV)		; BACK TO ORIGINAL STACK FRAME
+	LD	SP,(RD_STKSAV)		; BACK TO ORIGINAL STACK FRAME

 	JP	$FFFF			; RETURN, $FFFF IS DYNAMICALLY UPDATED
 REGDMP_RET	.EQU	$-2		; RETURN ADDRESS GOES HERE
@@ -470,9 +470,9 @@ REGDMP_RET	.EQU	$-2		; RETURN ADDRESS GOES HERE
 REGDMP_PC	.DW	0
 REGDMP_SP	.DW	0
 ;
-;RD_STKSAV	.DW	0
-;		.FILL	$FF,16*2	; 16 LEVEL PRIVATE STACK
-;RD_STACK	.EQU	$
+RD_STKSAV	.DW	0
+		.FILL	$FF,16*2	; 16 LEVEL PRIVATE STACK
+RD_STACK	.EQU	$
 ;
 ;
 ;
--- a/Source/HBIOS/vdu.asm
+++ b/Source/HBIOS/vdu.asm
@@ -81,6 +81,12 @@ VDU_R11		.EQU	DSCANL-1
 VDU_R10		.EQU	(VDU_BLNK + DSCANL-1)
 VDU_R11		.EQU	DSCANL-1
 #ENDIF
+;
+		.ECHO	"VDU: IO="
+		.ECHO	VDU_RAMRD
+		.ECHO	", PPK IO="
+		.ECHO	VDU_PPIA
+		.ECHO	"\n"
 ;
 ;======================================================================
 ; VDU DRIVER - INITIALIZATION
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Wayne Warthen	b841705023	Final Round of User Guide Updates per Martin R	2023-11-30 12:52:11 -08:00
Wayne Warthen	72cdbdd4ad	Documentation Updates Inspired by Martin R - Implemented a crude mechanism to output config settings during a build which can be imported into the User Guide appendix.	2023-11-29 18:54:51 -08:00
Wayne Warthen	b8ef50fad5	Update ZETA_std.asm - Correct assumed CPU speed in ZETA std config.	2023-11-27 19:15:19 -08:00
Wayne Warthen	c7d22892c1	Update std.asm Fix assembly error.	2023-11-27 17:58:24 -08:00
Wayne Warthen	8b3deb057f	User Guide Updates per Martin R - Credit and thanks to Martin R for providing a substantial list of suggested fixes and improvements to the User Guide. I have done my best to address them -- others will require more time and will hopefully be addressed in the future.	2023-11-27 17:44:53 -08:00
Wayne Warthen	df42cf544e	Support Mini-ITX Z180 Platform by Alan Cox Support for Mini-ITX contributed by Alan Cox.	2023-11-24 18:03:19 -08:00
Wayne Warthen	55a41ec0a3	TMS Driver Enhancement by Jose Collado - The 40 column mode of the TMS driver now conforms to the memory map from the TMS9918 documentation and is also now consistent with the existing TMS9918 video programs from the RC2014 forum.	2023-11-24 17:15:29 -08:00
Wayne Warthen	4417f871e5	Update AddRom.cmd - Minor improvements	2023-11-21 14:55:14 -08:00
Wayne Warthen	1c10f734bd	Create AddRom.cmd Experimental command line script (Windows only) to add a ROM image to user area 0 of hd1k_combo.img. Intended to make it easier to get a ROM image to a system for subsequent FLASHing.	2023-11-21 14:36:56 -08:00
Wayne Warthen	214182b514	Fix RTC Initialization When using the Z2 memory manager, if the HBIOS exceeds 16K, RTCDEFVAL will not be accessible prior to programming the Z2 memory bank registers. In this corner case the RTC latch could be mis-programmed. This commit introduces a workaround.	2023-11-21 11:59:31 -08:00
Wayne Warthen	08942fb944	Support Duodyne SelfHost UART	2023-11-20 17:01:53 -08:00
Wayne Warthen	5dc724785b	Completed CH37x Driver The ch.asm driver now supports SD Card operations (only possible for CH376).	2023-11-19 14:48:41 -08:00
Wayne Warthen	ce17be9ba6	CP/M 3 RAM Check - Check to ensure that we have enough RAM banks for banked CP/M 3 startup. If not, message and return to boot loader.	2023-11-18 16:58:23 -08:00
Wayne Warthen	badca621ba	Merge pull request #372 from dylanhall/dev Allow override of secondary console front panel switch selection	2023-11-18 16:54:50 -08:00
Dylan Hall	291cdd2c03	Use SECCON to override default secondary console selection	2023-11-17 17:47:01 +13:00
Wayne Warthen	888d9879c9	Preliminary Support for CH37x SD Cards - Currently operates as a read only disk device.	2023-11-16 19:39:09 -08:00
Dylan Hall	39446d5e4f	Add SECCON to config files	2023-11-17 16:36:29 +13:00
Wayne Warthen	af8385fba8	Fix IM1 Handling for Z180 - Credit to Dylan Hall - Z180 code failed to initialize interrupt vector registers for IM1 startup - Updated bad interrupt messaging to avoid interrupt stack overflow	2023-11-15 12:48:55 -08:00
Wayne Warthen	10ff97b6c6	ACIA Interrupt Fix & ROMless APPBOOT Fix - ACIA driver was not properly returning ZF to indicate if it handled an interrupt. - APPBOOT was failing on ROMless systems because it was copying the HBIOS code overtop of itself.	2023-11-09 14:37:46 -08:00
Wayne Warthen	7e9191f3ef	Update ps2info.asm - Updated PS2INFO to handle extraneous 0x00 byte after reset command.	2023-11-07 18:30:17 -08:00
Wayne Warthen	a67b1ecd0a	Fix RTC Init on ROMless Restart - On ROMless restart, the RTC was not being included in the boot messages.	2023-10-31 14:54:07 -07:00
Wayne Warthen	4012ee7775	Update User Guide Based on input from Issue #364, I have attempted to clarify a few areas on the User Guide: - Recommendation to only use ROM OSes only for limited purposes - Added a more detailed description of the automatic drive assignment algorithm - Added more detail on batch file auto-submission	2023-10-31 13:03:09 -07:00
Wayne Warthen	150ca6b50c	Fix .gitignore	2023-10-30 15:03:59 -07:00
Wayne Warthen	6af84e9ad8	Update Makefile - Fix Makefile	2023-10-30 14:29:02 -07:00
Wayne Warthen	6bcad122cd	Add Z1RCC Support - Added build support for Bill Chen's Z1RCC. - Thanks and credit to Bill for supplying the bulk of the build changes.	2023-10-30 14:14:11 -07:00
Wayne Warthen	003481410f	Update UNARC to Universal UNARC from Lars Nelson - Credit and thanks to Lars Nelson for providing an enhanced version of UNARC.	2023-10-30 12:07:26 -07:00
Wayne Warthen	9a1c3f7929	Minor Fix in SPK Driver and Tick Counter Space Reservation - Fix ensures that the speaker control bit is set the same as it was initially after playing a tone. - Reserve 2 bytes in the proxy for a platform dependent tick counter value. Currently for HEATH platform.	2023-10-30 11:41:31 -07:00
Wayne Warthen	ef536750ea	Makefile Improvements These changes improve the chances of a make operation actually failing when a nested error occurs.	2023-10-24 13:25:32 -07:00
Wayne Warthen	347a15a3b6	Build Script Updates - Minor update to GitHub build scripts	2023-10-23 18:30:40 -07:00
Wayne Warthen	1e5b38c251	PS2INFO Update & OpenSpin Conversion - Added support for Duodyne to PS2INFO application. - Switched all build paths to consistently use OpenSpin since it appears to be compatible with all build environments supported by RomWBW.	2023-10-23 18:07:42 -07:00
Wayne Warthen	29f93fb153	Enable CH and LPT Drivers for Duodyne	2023-10-19 17:23:08 -07:00
Wayne Warthen	b0975745df	Bump Version	2023-10-19 15:47:45 -07:00
Wayne Warthen	163460856a	Add Real Time Clock Section to User Guide, Issue #368	2023-10-19 15:03:49 -07:00
Wayne Warthen	3ce9246904	Update FLASH to v1.3.7 Thanks and credit to Will Sowerbutts for contributing and maintaining this critical utility!	2023-10-19 14:09:45 -07:00
Wayne Warthen	1a021e02b9	Enable PIO Support for Duodyne	2023-10-16 15:51:14 -07:00
Wayne Warthen	f2d304ef0d	Update cfg_duo.asm	2023-10-15 18:03:01 -07:00
Wayne Warthen	cbfbca8d92	Support New Duodyne Boards - Added support for Duodyne Multi-IO board - Added support for Duodyne Zilog-IO board - Added SUPCTS equate in hbios.asm to allow selectively adding code to suppress use of CTS during HBIOS boot - Added reference in User Guide to Bruce Hall's Assembly Language Programming document	2023-10-15 17:53:35 -07:00
Wayne Warthen	b175808a92	Fix for CP/M 3 Floppy Boot - CP/M 3 ldrbios had not been properly updated for device type id change. - ASSIGN command was not handling DPB's correctly due to device type id change.	2023-10-13 10:29:43 -07:00
Wayne Warthen	3e86e79133	Fix Makefiles	2023-10-12 17:45:00 -07:00
Wayne Warthen	3247e67ed4	ZRC and ZZRCC Image Creation Updates - Modified ZRC and ZZRCC image creation scripts to allow up to 0x1B8 of boot code.	2023-10-12 17:25:40 -07:00
Wayne Warthen	bbc84f0c2d	Fix FAT Application API Call FAT application had not been updated to reflect a change in the HBIOS Disk Device API call return data. This is corrected in this check-in. Related discussion in #368.	2023-10-12 12:49:05 -07:00