;
; ZETA 2 HARDWARE DEFINITIONS
;
#DEFINE 	PLATFORM_NAME	"ZETA V2"
;
SBC_BASE	.EQU	$60		; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
MPGSEL_0	.EQU	SBC_BASE + $18	; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1	.EQU	SBC_BASE + $19	; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2	.EQU	SBC_BASE + $1A	; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3	.EQU	SBC_BASE + $1B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
;
RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
;
CTCBASE		.EQU	$20	; CTC BASE I/O ADDRESS
CTCA		.EQU	CTCBASE + 0	; CTC CHANNEL A
CTCB		.EQU	CTCBASE + 1	; CTC CHANNEL B
CTCC		.EQU	CTCBASE + 2	; CTC CHANNEL C
CTCD		.EQU	CTCBASE + 3	; CTC CHANNEL D