; std-n8.inc 1/19/2013 dwg - 

;;CIODEV_BAT	.EQU	$E0
;;CIODEV_NUL	.EQU	$F0

;
; CHARACTER DEVICES
;
CIODEV_UART		.SET	$00
;CIODEV_ASCI	.EQU	$10
;CIODEV_VDU	.EQU	$20
;CIODEV_CVDU	.EQU	$30
;CIODEV_UPD7220	.EQU	$40
CIODEV_N8V	.EQU	$50
;CIODEV_PRPCON	.EQU	$60
;CIODEV_PPPCON	.EQU	$70
CIODEV_CRT	.EQU	$D0
;CIODEV_BAT	.EQU	$E0
CIODEV_NUL	.EQU	$F0

;
; DISK DEVICES (ONLY FIRST NIBBLE RELEVANT, SECOND NIBBLE RESERVED FOR UNIT)
;
;DIODEV_MD	.EQU	$00
DIODEV_FD	.EQU	$10
DIODEV_IDE	.EQU	$20
DIODEV_ATAPI	.EQU	$30
DIODEV_PPIDE	.EQU	$40
DIODEV_SD	.EQU	$50
DIODEV_PRPSD	.EQU	$60
DIODEV_PPPSD	.EQU	$70
DIODEV_HDSK	.EQU	$80
;
; RAM DISK INITIALIZATION OPTIONS
;
;CLR_NEVER	.EQU	0		; NEVER CLEAR RAM DISK
;CLR_AUTO	.EQU	1		; CLEAR RAM DISK IF INVALID DIR ENTRIES
;;CLR_ALWAYS	.EQU	2		; ALWAYS CLEAR RAM DISK
;
; DISK MAP SELECTION OPTIONS
;
;DM_ROM		.EQU	1		; ROM DRIVE PRIORITY
;DM_RAM		.EQU	2		; RAM DRIVE PRIORITY
;DM_FD		.EQU	3		; FLOPPY DRIVE PRIORITY
;DM_IDE		.EQU	4		; IDE DRIVE PRIORITY
;DM_PPIDE	.EQU	5		; PPIDE DRIVE PRIORITY
:DM_SD		.EQU	6		; SD DRIVE PRIORITY
;DM_PRPSD	.EQU	7		; PROPIO SD DRIVE PRIORITY
;DM_PPPSD	.EQU	8		; PROPIO SD DRIVE PRIORITY
;DM_HDSK		.EQU	9		; SIMH HARD DISK DRIVE PRIORITY
;
; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL)
;
;FDM720		.EQU	0		; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
;FDM144		.EQU	1		; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
;FDM360		.EQU	2		; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
;FDM120		.EQU	3		; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
;FDM111		.EQU	4		; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
;
; MEDIA ID VALUES
;
;MID_NONE	.EQU	0
;MID_MDROM	.EQU	1
;MID_MDRAM	.EQU	2
;MID_HD		.EQU	3
;MID_FD720	.EQU	4
;MID_FD144	.EQU	5
;MID_FD360	.EQU	6
;MID_FD120	.EQU	7
;MID_FD111	.EQU	8
;
; FD MODE SELECTIONS
;
;FDMODE_DIO	.EQU	1		; DISKIO V1
;FDMODE_ZETA	.EQU	2		; ZETA
;FDMODE_DIDE	.EQU	3		; DUAL IDE
;FDMODE_N8	.EQU	4		; N8
;FDMODE_DIO3	.EQU	5		; DISKIO V3
;
; IDE MODE SELECTIONS
;
;IDEMODE_DIO	.EQU	1		; DISKIO V1
;IDEMODE_DIDE	.EQU	2		; DUAL IDE
;
; PPIDE MODE SELECTIONS
;
;PPIDEMODE_STD	.EQU	1		; STANDARD N8VEM PARALLEL PORT
;PPIDEMODE_DIO3	.EQU	2		; DISKIO V3 PARALLEL PORT
;
; CONSOLE TERMINAL TYPE CHOICES
;
;TERM_TTY	.EQU	0
;TERM_ANSI	.EQU	1
;TERM_WYSE	.EQU	2
;TERM_VT52	.EQU	3
;
; EMULATION TYPES
;
;EMUTYP_NONE	.EQU	0
;EMUTYP_TTY	.EQU	1
;EMUTYP_ANSI	.EQU	2
;
; SYSTEM GENERATION SETTINGS
;
;SYS_CPM		.EQU	1		; CPM (IMPLIES BDOS + CCP)
;SYS_ZSYS	.EQU	2		; ZSYSTEM OS (IMPLIES ZSDOS + ZCPR)
;
;DOS_BDOS	.EQU	1		; BDOS
;DOS_ZDDOS	.EQU	2		; ZDDOS VARIANT OF ZSDOS
;DOS_ZSDOS	.EQU	3		; ZSDOS
;
;CP_CCP		.EQU	1		; CCP COMMAND PROCESSOR
;CP_ZCPR		.EQU	2		; ZCPR COMMAND PROCESSOR
;
; CONFIGURE DOS (DOS) AND COMMAND PROCESSOR (CP) BASED ON SYSTEM SETTING (SYS)
;
;#IFNDEF BLD_SYS
;SYS		.EQU	SYS_CPM
;#ELSE
;SYS		.EQU	BLD_SYS
;#ENDIF
;
#IF (SYS == SYS_CPM)
;DOS		.EQU	DOS_BDOS
;CP		.EQU	CP_CCP
#DEFINE		OSLBL	"CP/M-80 2.2"
#ENDIF
;
#IF (SYS == SYS_ZSYS)
DOS		.EQU	DOS_ZSDOS
CP		.EQU	CP_ZCPR
#DEFINE		OSLBL	"ZSDOS 1.1"
#ENDIF
;
; INCLUDE VERSION AND BUILD SETTINGS
;
;#INCLUDE "ver.inc"			; ADD BIOSVER
;
;#INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Support for S100COMPUTERS.COM Hardware ;
; Phase One Support - Minimum Board Set  ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

#IF (PLATFORM == PLT_S100)
;
#IFDEF S100_CPU
#INCLUDE "S100CPU.INC"
#ENDIF
;
#IFDEF S100_IOB
#INCLUDE "S100IOB.INC"
#ENDIF
;
#IFDEF S100_RRF
#INCLUDE "S100RRF.INC"
#ENDIF

#IFDEF S100_DIDE
#INCLUDE "S100DIDE.INC"
#ENDIF
;
#ENDIF


#IF (PLATFORM != PLT_N8)
;
; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
;
MPCL_RAM	.EQU 	78H		; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
MPCL_ROM	.EQU 	7CH		; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
RTC		.EQU	70H		; ADDRESS OF RTC LATCH AND INPUT PORT

;__HARDWARE_INTERFACES________________________________________________________________________________________________________________ 
;
; PPI 82C55 I/O IS DECODED TO PORT 60-67
;
#IF (PLATFORM == PLT_S2I)
PPIBASE		.EQU	80H
#ELSE
PPIBASE		.EQU	60H
#ENDIF
PPIA		.EQU 	PPIBASE + 0	; PORT A
PPIB		.EQU 	PPIBASE + 1	; PORT B
PPIC		.EQU 	PPIBASE + 2	; PORT C
PPIX	 	.EQU 	PPIBASE + 3	; PPI CONTROL PORT
;
; 16C550 SERIAL LINE UART
;
#IF (PLATFORM == PLT_S2I)
SIO_BASE	.EQU	90H
#ELSE
SIO_BASE	.EQU	68H
#ENDIF
SIO_RBR		.EQU	SIO_BASE + 0	; DLAB=0: RCVR BUFFER REG (READ ONLY)
SIO_THR		.EQU	SIO_BASE + 0	; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
SIO_IER		.EQU	SIO_BASE + 1	; DLAB=0: INT ENABLE REG
SIO_IIR		.EQU	SIO_BASE + 2	; INT IDENT REGISTER (READ ONLY)
SIO_FCR		.EQU	SIO_BASE + 2	; FIFO CONTROL REG (WRITE ONLY)
SIO_LCR		.EQU	SIO_BASE + 3	; LINE CONTROL REG
SIO_MCR		.EQU	SIO_BASE + 4	; MODEM CONTROL REG
SIO_LSR		.EQU	SIO_BASE + 5	; LINE STATUS REG
SIO_MSR		.EQU	SIO_BASE + 6	; MODEM STATUS REG
SIO_SCR		.EQU	SIO_BASE + 7	; SCRATCH REGISTER
SIO_DLL		.EQU	SIO_BASE + 0	; DLAB=1: DIVISOR LATCH (LS)
SIO_DLM		.EQU	SIO_BASE + 1	; DLAB=1: DIVISOR LATCH (MS)
;
#ENDIF		; (PLATFORM != PLT_N8)
;
#IF (PLATFORM == PLT_N8)
;
; Z180 REGISTERS
;
CPU_IOBASE	.EQU	40H		; ONLY RELEVANT FOR Z180
;
CPU_CNTLA0:	.EQU	CPU_IOBASE+$00	;ASCI0 control A
CPU_CNTLA1:	.EQU	CPU_IOBASE+$01	;ASCI1 control A
CPU_CNTLB0:	.EQU	CPU_IOBASE+$02	;ASCI0 control B
CPU_CNTLB1:	.EQU	CPU_IOBASE+$03	;ASCI1 control B
CPU_STAT0:	.EQU	CPU_IOBASE+$04	;ASCI0 status
CPU_STAT1:	.EQU	CPU_IOBASE+$05	;ASCI1 status
CPU_TDR0:	.EQU	CPU_IOBASE+$06	;ASCI0 transmit
CPU_TDR1:	.EQU	CPU_IOBASE+$07	;ASCI1 transmit
CPU_RDR0:	.EQU	CPU_IOBASE+$08	;ASCI0 receive
CPU_RDR1:	.EQU	CPU_IOBASE+$09	;ASCI1 receive
CPU_CNTR:	.EQU	CPU_IOBASE+$0A	;CSI/O control
CPU_TRDR:	.EQU	CPU_IOBASE+$0B	;CSI/O transmit/receive
CPU_TMDR0L:	.EQU	CPU_IOBASE+$0C	;Timer 0 data lo
CPU_TMDR0H:	.EQU	CPU_IOBASE+$0D	;Timer 0 data hi
CPU_RLDR0L:	.EQU	CPU_IOBASE+$0E	;Timer 0 reload lo
CPU_RLDR0H:	.EQU	CPU_IOBASE+$0F	;Timer 0 reload hi
CPU_TCR:	.EQU	CPU_IOBASE+$10	;Timer control
;	
CPU_ASEXT0:	.EQU	CPU_IOBASE+$12	;ASCI0 extension control (Z8S180)
CPU_ASEXT1:	.EQU	CPU_IOBASE+$13	;ASCI1 extension control (Z8S180)
;
CPU_TMDR1L:	.EQU	CPU_IOBASE+$14	;Timer 1 data lo
CPU_TMDR1H:	.EQU	CPU_IOBASE+$15	;Timer 1 data hi
CPU_RLDR1L:	.EQU	CPU_IOBASE+$16	;Timer 1 reload lo
CPU_RLDR1H:	.EQU	CPU_IOBASE+$17	;Timer 1 reload hi
CPU_FRC:	.EQU	CPU_IOBASE+$18	;Free running counter

CPU_ASTC0L:	.EQU	CPU_IOBASE+$1A	;ASCI0 Time constant lo (Z8S180)
CPU_ASTC0H:	.EQU	CPU_IOBASE+$1B	;ASCI0 Time constant hi (Z8S180)
CPU_ASTC1L:	.EQU	CPU_IOBASE+$1C	;ASCI1 Time constant lo (Z8S180)
CPU_ASTC1H:	.EQU	CPU_IOBASE+$1D	;ASCI1 Time constant hi (Z8S180)
CPU_CMR:	.EQU	CPU_IOBASE+$1E	;Clock multiplier (latest Z8S180)
CPU_CCR:	.EQU	CPU_IOBASE+$1F	;CPU control (Z8S180)
;
CPU_SAR0L:	.EQU	CPU_IOBASE+$20	;DMA0 source addr lo
CPU_SAR0H:	.EQU	CPU_IOBASE+$21	;DMA0 source addr hi
CPU_SAR0B:	.EQU	CPU_IOBASE+$22	;DMA0 source addr bank
CPU_DAR0L:	.EQU	CPU_IOBASE+$23	;DMA0 dest addr lo
CPU_DAR0H:	.EQU	CPU_IOBASE+$24	;DMA0 dest addr hi
CPU_DAR0B:	.EQU	CPU_IOBASE+$25	;DMA0 dest addr bank
CPU_BCR0L:	.EQU	CPU_IOBASE+$26	;DMA0 byte count lo
CPU_BCR0H:	.EQU	CPU_IOBASE+$27	;DMA0 byte count hi
CPU_MAR1L:	.EQU	CPU_IOBASE+$28	;DMA1 memory addr lo
CPU_MAR1H:	.EQU	CPU_IOBASE+$29	;DMA1 memory addr hi
CPU_MAR1B:	.EQU	CPU_IOBASE+$2A	;DMA1 memory addr bank
CPU_IAR1L:	.EQU	CPU_IOBASE+$2B	;DMA1 I/O addr lo
CPU_IAR1H:	.EQU	CPU_IOBASE+$2C	;DMA1 I/O addr hi
CPU_IAR1B:	.EQU	CPU_IOBASE+$2D	;DMA1 I/O addr bank (Z8S180)
CPU_BCR1L:	.EQU	CPU_IOBASE+$2E	;DMA1 byte count lo
CPU_BCR1H:	.EQU	CPU_IOBASE+$2F	;DMA1 byte count hi
CPU_DSTAT:	.EQU	CPU_IOBASE+$30	;DMA status
CPU_DMODE:	.EQU	CPU_IOBASE+$31	;DMA mode
CPU_DCNTL:	.EQU	CPU_IOBASE+$32	;DMA/WAIT control
CPU_IL:		.EQU	CPU_IOBASE+$33	;Interrupt vector load
CPU_ITC:	.EQU	CPU_IOBASE+$34	;INT/TRAP control
;
CPU_RCR:	.EQU	CPU_IOBASE+$36	;Refresh control
;
CPU_CBR:	.EQU	CPU_IOBASE+$38	;MMU common base register
CPU_BBR:	.EQU	CPU_IOBASE+$39	;MMU bank base register
CPU_CBAR	.EQU	CPU_IOBASE+$3A	;MMU common/bank area register
;
CPU_OMCR:	.EQU	CPU_IOBASE+$3E	;Operation mode control
CPU_ICR:	.EQU	$3F		;I/O control register (not relocated!!!)
;
; N8 ONBOARD  I/O REGISTERS
;
N8_IOBASE	.EQU	$80
;
PPI		.EQU	N8_IOBASE+$00
PPIA		.EQU 	PPI+$00		; PORT A
PPIB		.EQU 	PPI+$01		; PORT B
PPIC		.EQU 	PPI+$02		; PORT C
PPIX	 	.EQU 	PPI+$03		; PPI CONTROL PORT
;
PPI2		.EQU	N8_IOBASE+$04
PPI2A		.EQU 	PPI2+$00	; PORT A
PPI2B		.EQU 	PPI2+$01	; PORT B
PPI2C		.EQU 	PPI2+$02	; PORT C
PPI2X	 	.EQU 	PPI2+$03	; PPI CONTROL PORT
;
RTC:		.EQU	N8_IOBASE+$08	;RTC latch and buffer
;FDC:		.EQU	N8_IOBASE+$0C	;Floppy disk controller
;UTIL:		.EQU	N8_IOBASE+$10	;Floppy disk utility 
ACR:		.EQU	N8_IOBASE+$14	;auxillary control register
RMAP:		.EQU	N8_IOBASE+$16	;ROM page register
VDP:		.EQU	N8_IOBASE+$18	;Video Display Processor (TMS9918A)
PSG:		.EQU	N8_IOBASE+$1C	;Programmable Sound Generator (AY-3-8910)
;
DEFACR		.EQU	$1B
;
#ENDIF