;
;==================================================================================================
;   LOADER
;==================================================================================================
;
P2LOC		.EQU	$F000	; PHASE 2 RUN LOCATION
;
#IFDEF ROMLOAD
CURBNK		.EQU	BID_BOOT
#ELSE
CURBNK		.EQU	BID_USR
#ENDIF
;
;==================================================================================================
;   HBIOS CONFIGURATION BLOCK (HCB)
;==================================================================================================
;
		.ORG	$ + P2LOC
CB:
		.DB	'W',~'W'	; MARKER
		.DB	RMJ << 4 | RMN	; FIRST BYTE OF VERSION INFO
		.DB	RUP << 4 | RTP	; SECOND BYTE OF VERSION INFO
;
CB_PLT		.DB	PLATFORM
CB_CPUMHZ	.DB	CPUMHZ
CB_CPUKHZ	.DW	CPUKHZ
CB_RAMBANKS	.DB	RAMSIZE / 32
CB_ROMBANKS	.DB	ROMSIZE / 32
;
CB_BOOTVOL	.DW	0		; BOOT VOLUME IS UNIT/SLICE, SET BY LOADER
CB_BOOTBID	.DB	0		; BOOT BANK ID, SET BY LOADER
CB_SERDEV	.DB	0		; PRIMARY SERIAL UNIT IS UNIT #0 BY FIAT
CB_CRTDEV	.DB	$FF		; PRIMARY CRT UNIT, $FF UNTIL AFTER HBIOS INIT
CB_CONDEV	.DB	$FF		; CONSOLE UNIT, $FF UNTIL AFTER HBIOS INIT
;
;CB_CUREMU	.DB	VDAEMU		; CURRENT VDA TERMINAL EMULATION (DEPRECATED)
;CB_CURVDA	.DB	VDADEV		; CURRENT VDA TARGET FOR EMULATION (DEPRECATED)
;
; MEMORY MANAGEMENT VARIABLES START AT $20
;
		.FILL	(CB + $20 - $),0
;
CB_HEAP		.DW	0
CB_HEAPTOP	.DW	0
;
; STANDARD BANK ID'S START AT $D8
;
		.FILL	(CB + $D8 - $),0
;
CB_BIDCOM	.DB	BID_COM
CB_BIDUSR	.DB	BID_USR
CB_BIDBIOS	.DB	BID_BIOS
CB_BIDAUX	.DB	BID_AUX
CB_BIDRAMD0	.DB	BID_RAMD0
CB_BIDRAMDN	.DB	BID_RAMDN
CB_BIDROMD0	.DB	BID_ROMD0
CB_BIDROMDN	.DB	BID_ROMDN
;
	.FILL	(CB + HCB_SIZ - $),0	; PAD REMAINDER OF HCB
;
	.ORG	$ - P2LOC
;
;==================================================================================================
;   COLD START
;==================================================================================================
;
START:
	DI			; NO INTERRUPTS
	IM	1		; INTERRUPT MODE 1
	LD	SP,HBX_LOC	; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
;
; HARDWARE BOOTSTRAP FOR Z180
; FOR N8, ACR & RMAP ARE ASSUMED TO BE ALREADY SET OR THIS CODE
; WOULD NOT BE EXECUTING
;
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
	; SET BASE FOR CPU IO REGISTERS
   	LD	A,Z180_BASE
	OUT0	(Z180_ICR),A

	; DISABLE REFRESH
	XOR	A
	OUT0	(Z180_RCR),A

	; SET DEFAULT CPU CLOCK MULTIPLIERS (XTAL / 2)
	XOR	A
	OUT0	(Z180_CCR),A
	OUT0	(Z180_CMR),A

	; SET DEFAULT WAIT STATES
	LD	A,$F0
	OUT0	(Z180_DCNTL),A

	; MMU SETUP
	LD	A,$80
	OUT0	(Z180_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
#IFDEF ROMLOAD
	XOR	A
	OUT0	(Z180_BBR),A		; BANK BASE = 0
#ENDIF
	LD	A,(RAMSIZE + RAMBIAS - 64) >> 2
	OUT0	(Z180_CBR),A		; COMMON BASE = LAST (TOP) BANK

#IF (Z180_CLKDIV >= 1)
	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
	LD	A,$80
	OUT0	(Z180_CCR),A
#ENDIF

#IF (Z180_CLKDIV >= 2)
	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
	LD	A,$80
	OUT0	(Z180_CMR),A
#ENDIF

	; SET DESIRED WAIT STATES
	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
	OUT0	(Z180_DCNTL),A
#ENDIF
;
; HARDWARE BOOTSTRAP FOR ZETA 2
;
#IF (PLATFORM == PLT_ZETA2)
	; SET PAGING REGISTERS
#IFDEF ROMLOAD
	XOR	A
	OUT	(MPGSEL_0),A
	INC	A
	OUT	(MPGSEL_1),A
#ENDIF
	LD	A,62
	OUT	(MPGSEL_2),A
	INC	A
	OUT	(MPGSEL_3),A
	; ENABLE PAGING
	LD	A,1
	OUT	(MPGENA),A
#ENDIF
;
; EMIT FIRST SIGN OF LIFE TO SERIAL PORT
;
	CALL	XIO_INIT	; INIT SERIAL PORT
#IFNDEF
	CALL	XIO_CRLF	; FORMATTING
	CALL	XIO_CRLF	; FORMATTING
#ENDIF
	LD	HL,STR_BOOT	; POINT TO MESSAGE
	CALL	XIO_OUTS	; SAY HELLO
;
; COPY OURSELVES AND LOADER TO HI RAM FOR PHASE 2
;
	LD	HL,0		; COPY FROM START OF ROM IMAGE
	LD	DE,P2LOC	; TO HIMEM RUN LOCATION
	LD	BC,LDR_END	; COPY FULL IMAGE
	LDIR
;
	CALL	XIO_DOT		; MARK PROGRESS
;
	JP	PHASE2		; JUMP TO PHASE 2 BOOT IN UPPER MEMORY
;
STR_BOOT	.DB	"RomWBW$"
;
; IMBED DIRECT SERIAL I/O ROUTINES
;
#INCLUDE "xio.asm"
#INCLUDE "decode.asm"
;
;______________________________________________________________________________________________________________________
;
; THIS IS THE PHASE 2 CODE THAT MUST EXECUTE IN UPPER MEMORY
;
	.ORG	$ + P2LOC	; WE ARE NOW EXECUTING IN UPPER MEMORY
;
PHASE2:
	CALL	XIO_DOT		; MARK PROGRESS
;
; INSTALL HBIOS PROXY IN UPPER MEMORY
;
#IFDEF ROMLOAD
	LD	A,BID_BIOSIMG	; HBIOS IMAGE ROM BANK
	CALL	BNKSEL		; SELECT IT
#ENDIF
	LD	HL,HBX_IMG	; HL := SOURCE OF HBIOS PROXY IMAGE
#IFNDEF ROMLOAD
	LD	BC,LDR_END	; SIZE OF LOADER
	ADD	HL,BC		; OFFSET SOURCE ADDRESS
#ENDIF
	LD	DE,HBX_LOC	; DE := DESTINATION TO INSTALL IT
	LD	BC,HBX_SIZ	; SIZE
	LDIR			; DO THE COPY
	LD	A,CURBNK	; BOOT/SETUP BANK
	LD	(HB_CURBNK),A	; INIT CURRENT BANK
#IFDEF ROMLOAD
	CALL	BNKSEL		; SELECT IT
#ENDIF
	CALL	XIO_DOT		; MARK PROGRESS
;
; INSTALL HBIOS CODE BANK
;
#IFDEF ROMLOAD
	LD	A,BID_BIOSIMG	; SOURCE BANK
#ELSE
	LD	A,(HB_CURBNK)	; SOURCE BANK
#ENDIF
	LD	(HB_SRCBNK),A	; SET IT
	LD	A,BID_BIOS	; DESTINATION BANK
	LD	(HB_DSTBNK),A	; SET IT
	LD	HL,0		; SOURCE ADDRESS IS ZERO
#IFNDEF ROMLOAD
	LD	BC,LDR_END	; SIZE OF LOADER
	ADD	HL,BC		; OFFSET SOURCE ADDRESS
#ENDIF
	LD	DE,0		; TARGET ADDRESS IS ZERO
	LD	BC,HB_END	; COPY ALL OF HBIOS IMAGE
	CALL	XIO_DOT		; MARK PROGRESS
	CALL	HB_BNKCPY	; DO IT
	CALL	XIO_DOT		; MARK PROGRESS
	
	;; HACK TO FLUSH THE OUTPUT FIFO
	;XOR	A
	;CALL	XIO_OUTC
	;CALL	XIO_OUTC
	;CALL	XIO_OUTC
	;CALL	XIO_OUTC
;
; INSTALL HCB INTO HBIOS CODE BANK
;
	LD	A,BID_BIOS	; GET BIOS BANK
	LD	(HB_SRCBNK),A	; SET AS SOURCE (IRRELEVANT)
	LD	(HB_DSTBNK),A	; SET AS DEST
	LD	HL,CB		; LOCAL LOADER HCB ADDRESS
	LD	DE,HCB_LOC	; DEST HBIOS HCB ADDRESS
	LD	BC,HCB_SIZ	; ONE PAGE IN LENGTH
	CALL	HB_BNKCPY	; DO IT
	CALL	XIO_DOT		; MARK PROGRESS
;
; INITIALIZE HBIOS
;
	LD	A,BID_BIOS	; HBIOS BANK
	LD	HL,0		; ADDRESS 0 IS HBIOS INIT ENTRY ADDRESS
	CALL	HB_BNKCALL	; DO IT
;
; CHAIN TO OS LOADER
;
#IFDEF ROMLOAD
	; PERFORM BANK CALL TO OS IMAGES BANK
	LD	A,BID_OSIMG	; CHAIN TO OS IMAGES BANK
	LD	HL,0		; ENTER AT ADDRESS 0
	CALL	HB_BNKCALL	; GO THERE
	HALT			; WE SHOULD NEVER COME BACK!
#ELSE
	; SLIDE OS IMAGES BLOB DOWN TO $0000
	LD	HL,LDR_END	; SOURCE IS LOADER END
	LD	BC,HB_END	; PLUS HBIOS IMAGE SIZE
	ADD	HL,BC		; FINAL SOURCE ADDRESS
	LD	DE,0		; TARGET ADDRESS IS ZERO
	LD	BC,BNKTOP	; MAX SIZE OF OS IMAGES
	LDIR			; DO IT
	; JUMP TO START
	JP	0		; AND CHAIN
#ENDIF
;
;==================================================================================================
;   MEMORY MANAGER
;==================================================================================================
;
#IFDEF ROMLOAD
#INCLUDE "memmgr.asm"
#ENDIF
;
;==================================================================================================
;   CLEAN UP
;==================================================================================================
;
	.ORG	$ - P2LOC	; BACK TO IMAGE-BASED ADDRESSING
LDR_END	.EQU	$		; MARK END OF LOADER