;:::::::::::::::::::::::::::::::::::::::::::::::********************** ; B/P BIOS Configuration and Equate File. ** System Dependant ** ; - Retro-Brew boards /w RomWBW HBIOS - ********************** ; Setup for a Non-banked, internal HBIOS proxy System ; Custom tailor your system here. ; ; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN ; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN ; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN ; 17 Jan 14 - Initial N8VEM release WW+LN ; 30 Aug 01 - Cleaned up for GPL release. HFB ; 11 May 97 - Added GIDE and adjusted HD equates. HFB ; 5 Jan 97 - Reformatted to Standard. HFB ; 10 Jun 96 - Initial Test Release. HFB ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ; BIOS Configuration Equates and Macros DATE MACRO DEFB '02 Aug 21' ; Date of this version ENDM AUTOCL MACRO DEFB 8,'ZEX ZSTN',0 ; Autostart command line ENDM ;--- Basic System and Z-System Section --- MOVCPM EQU NO ; Integrate into MOVCPM "type" loader? IF MOVCPM VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor) ELSE VERS EQU 21H ; Version number w/Device Swapping permitted ENDIF BANKED EQU NO ; Is this a banked BIOS? ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible INROM EQU NO ; Alternate bank in ROM? MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24) FASTWB EQU YES ; Yes if restoring CPR from banked RAM ; ..No if restoring from Drive A Z3 EQU YES ; Include ZCPR init code? HAVIOP EQU NO ; Include IOP code into Jump table? INTPXY EQU YES ; YES to use internal HBIOS proxy ; and load Proxy as part of BPBIOS. ; NO to use HBIOS Proxy in high RAM ; (already loaded) IF INTPXY ; YES load Proxy as part of BPBIOS. MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS ; interface (32 bytes) ELSE ; NO use HBIOS Proxy in high RAM ; (already loaded) HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used) MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS ENDIF ;--- Memory configuration Section --- (Expansion Memory configured here) IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180) ; No = Include Common RAM transfer buffer ;--- Character Device Section --- MORDEV EQU NO ; YES = Include any extra Char Device Drivers ; NO = Only use the 4 defined Char Devices QSIZE EQU 32 ; size of interrupt typeahead buffers (if used) ; ..must be 2^n with n<8 RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs? XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines? ;--- Clock and Time Section --- CLOCK EQU YES ; Include ZSDOS Clock Driver Code? CLKSET EQU YES ; Allow Clock Sets? (Error if No) ;--- Floppy Diskette Section --- FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made BIOERM EQU yes ; Print BIOS error messages? CALCSK EQU YES ; Calculate skew table? AUTOSL EQU YES ; Auto select floppy formats? ; If AUTOSL=True, the next two are active... FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers? FLOPYH EQU no ; Include "Hi-Density" Floppy Formats? FLOPY8 EQU no ; Include 8" Floppy Formats? MORDPB EQU NO ; Include additional Floppy DPB Formats? ;;--- RAM Disk Section --- ; ;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made ;--- Hard Disk Section --- HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only ; (Pick 1 of 3 options below) HBDSK EQU YES ; YES = Use HBIOS Disk Driver HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers? ; (DMA not implemented for GIDE) UNIT_0 EQU YES ; Hard Disk Physical Unit 1 UNIT_1 EQU YES ; Hard Disk Physical Unit 2 UNIT_2 EQU YES ; Hard Disk Physical Unit 3 ;--- Logical Drive Section --- ; ; Set each of these equates for the drive and partition complement of ; your system. Set equates to no if drive exists or is wanted. DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0. DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1. DRV_C EQU yes DRV_D EQU yes DRV_E EQU yes ; Default is C-J are Hard Disk Slices DRV_F EQU yes ; on the first hard drive (room for DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card. DRV_H EQU yes DRV_I EQU yes DRV_J EQU yes DRV_K EQU yes ; Default is K-N are Hard Disk Slices DRV_L EQU yes ; on a second hard drive (room for up to DRV_M EQU yes ; 4 Slices provided) e.g. SD card DRV_N EQU yes if FLPYDSK DRV_O EQU yes ; O & P are floppies DRV_P EQU yes else DRV_O EQU no ; O & P are floppies DRV_P EQU no endif ;========== Configuration Unique Equates =========== ;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<< ;>>> Do NOT Alter these unless you KNOW what you're doing <<< ;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< REFRSH EQU NO ; Set to NO for only Static RAM, needed for ; systems with dynamic RAMs. NOWAIT EQU NO ; Set to NO to use configured Wait States in ; Hard Disk Driver. Yes to eliminate Waits. ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; For Z-180/HD64180 systems, The Bank numbers should reflect Physical ; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the ; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k ; of 512k. HBIOS occupies bank 1. The upper ; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration. BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H BNKU EQU 00H ; User Area Bank 58000H ; (set to 0 to disable) BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H BNKM EQU BID_RAMM ; Maximum Bank # F8000H ; With both on-board RAMs only (MEM1 or MEM2), ; the maximum Bank number is 11 (0BH). IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a ; nice resource for Z180 programing in general ;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ========== CNTLA0 EQU 00H ; Control Port ASCI 0 CNTLA1 EQU 01H ; Control Port ASCI 1 STAT0 EQU 04H ; Serial port 0 Status STAT1 EQU 05H ; Serial port 1 Status TDR0 EQU 06H ; Serial port 0 Output Data TDR1 EQU 07H ; Serial port 1 Output Data RDR0 EQU 08H ; Serial port 0 Input Data RDR1 EQU 09H ; Serial Port 1 Input Data CNTR EQU 0AH ; HD64180 Counter port TMDR0L EQU 0CH ; HD64180 DMA channel reg (low) TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi) RLDR0L EQU 0EH ; CTC0 Reload Count, Low RLDR0H EQU 0FH ; CTC0 Reload Count, High TCR EQU 10H ; Interrupt Control Register TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low) TMDR1H EQU 15H ; Timer Data Reg Ch1 (High) RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low) RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High) FRC EQU 18H ; Free-Running Counter CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182) SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports) MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports) DSTAT EQU 30H ; DMA Status/Control port DMODE EQU 31H ; DMA Mode Control port DCNTL EQU 32H ; DMA/WAIT Control Register IL EQU 33H ; Interrupt Segment Register ITC EQU 34H ; Interrupt/Trap Control Register RCR EQU 36H ; HD64180 Refresh Control register CBR EQU 38H ; MMU Common Base Register BBR EQU 39H ; MMU Bank Base Register CBAR EQU 3AH ; MMU Common/Bank Area Register OMCR EQU 3EH ; Operation Mode Control Reg ICR EQU 3FH ; I/O Control Register ; Some bit definitions used with the Z-180 on-chip peripherals: TDRE EQU 02H ; ACSI Transmitter Buffer Empty RDRF EQU 80H ; ACSI Received Character available ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; Extended Features of Z80182 for P112 WSGCS EQU 0D8H ; Wait-State Generator CS ENH182 EQU 0D9H ; Z80182 Enhancements Register PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register RAMUBR EQU 0E6H ; RAM End Boundary RAMLBR EQU 0E7H ; RAM Start Boundary ROMBR EQU 0E8H ; ROM Boundary FIFOCTL EQU 0E9H ; FIFO Control Register RTOTC EQU 0EAH ; RX Time-Out Time Constant TTOTC EQU 0EBH ; TX Time-Out Time Constant FCR EQU 0ECH ; FIFO Register SCR EQU 0EFH ; System Pin Control RBR EQU 0F0H ; MIMIC RX Buffer Register (R) THR EQU 0F0H ; MIMIN TX Holding Register (W) IER EQU 0F1H ; Interrupt Enable Register LCR EQU 0F3H ; Line Control Register MCR EQU 0F4H ; Modem Control Register LSR EQU 0F5H ; Line Status Register MDMSR EQU 0F6H ; Modem Status Register MSCR EQU 0F7H ; MIMIC Scratch Register DLATL EQU 0F8H ; Divisor Latch (Low) DLATM EQU 0F9H ; Divisor Latch (High) TTCR EQU 0FAH ; TX Time Constant RTCR EQU 0FBH ; RX Time Constant IVEC EQU 0FCH ; MIMIC Interrupt Vector MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register MMCR EQU 0FFH ; MIMIC Master Control Register ; Z80182 PIO Registers DDRA EQU 0EDH ; Data Direction Register A DRA EQU 0EEH ; Port A Data DDRB EQU 0E4H ; Data Direction Register B DRB EQU 0E5H ; Data B Data DDRC EQU 0DDH ; Data Direction Register C DRC EQU 0DEH ; Data C Data ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; ESCC Registers on Z80182 SCCACNT EQU 0E0H ; ESCC Control Channel A SCCAD EQU 0E1H ; ESCC Data Channel A SCCBCNT EQU 0E2H ; ESCC Control Channel B SCCBD EQU 0E3H ; ESCC Data Channel B ; [E]SCC Internal Register Definitions RR0 EQU 00H RR1 EQU 01H RR2 EQU 02H RR3 EQU 03H RR6 EQU 06H RR7 EQU 07H RR10 EQU 0AH RR12 EQU 0CH RR13 EQU 0DH RR15 EQU 0FH WR0 EQU 00H WR1 EQU 01H WR2 EQU 02H WR3 EQU 03H WR4 EQU 04H WR5 EQU 05H WR6 EQU 06H WR7 EQU 07H WR9 EQU 09H WR10 EQU 0AH WR11 EQU 0BH WR12 EQU 0CH WR13 EQU 0DH WR14 EQU 0EH WR15 EQU 0FH ; FDC37C665/6 Parallel Port in Standard AT Mode DPORT EQU 8CH ; Data Port SPORT EQU 8DH ; Status Port CPORT EQU 8EH ; Control Port ; FDC37C665/6 Configuration Control (access internal registers) CFCNTL EQU 90H ; Configuration control port CFDATA EQU 91H ; Configuration data port ; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible) DCR EQU 92H ; Drive Control Register (Digital Output) MSR EQU 94H ; Main Status Register DR EQU 95H ; Data/Command Register DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7 _DMA EQU 0A0H ; Diskette DMA Address ; FDC37C665/6 Serial Port (National 16550 compatible) _RBR EQU 68H ;R Receiver Buffer _THR EQU 68H ;W Transmit Holding Reg _IER EQU 69H ;RW Interrupt-Enable Reg _IIR EQU 6AH ;R Interrupt Ident. Reg _FCR EQU 6AH ;W FIFO Control Reg _LCR EQU 6BH ;RW Line Control Reg _MCR EQU 6CH ;RW Modem Control Reg _LSR EQU 6DH ;RW Line Status Reg _MMSR EQU 6EH ;RW Modem Status Reg _SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT) _DDL EQU 68H ;RW Divisor LSB | wih DLAB _DLM EQU 69H ;RW Divisor MSB | set High ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; Equates for the National DP8490/NCR 5380 Prototype SCSI controller IF HARDDSK NCR EQU 40H ; Base of NCR 5380 ; 5380 Chip Registers NCRDAT EQU NCR ; Current SCSI Data (Read) ; Output Data Register (Write) NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write) NCRMOD EQU NCR+2 ; Mode Register (Read/Write) NCRTGT EQU NCR+3 ; Target Command Register (Read/Write) NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read) NCRST EQU NCR+5 ; Bus & Status Register (Read) ; Start DMA Send (Write) NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read) ; Start DMA Initiator Receive (Write) DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write) ; Bit Assignments for NCR 5380 Ports as indicated B_ARST EQU 10000000B ; Assert *RST (NCRCMD) B_AACK EQU 00010000B ; Assert *ACK (NCRCMD) B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD) B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD) B_BSY EQU 01000000B ; *Busy (NCRBUS) B_REQ EQU 00100000B ; *Request (NCRBUS) B_MSG EQU 00010000B ; *Message (NCRBUS) B_CD EQU 00001000B ; *Command/Data (NCRBUS) B_IO EQU 00000100B ; *I/O (NCRBUS) B_SEL EQU 00000010B ; *Select (NCRBUS) B_PHAS EQU 00001000B ; Phase Match (NCRST) B_BBSY EQU 00000100B ; Bus Busy (NCRST) B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD) B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD) ENDIF ;harddsk ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added) ; Set the base GIDE equate to the jumper setting on the GIDE board. IF IDE GIDE EQU 50H ; Set base of 16 byte address range IDEDOR EQU GIDE+6 ; Digital Output Register IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide) IDEErr EQU GIDE+9 ; IDE Error Register IDESCnt EQU GIDE+0AH ; IDE Sector Count Register IDESNum EQU GIDE+0BH ; IDE Sector Number Register IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low) IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High) IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register IDECmd EQU GIDE+0FH ; IDE Command/Status Register CMDHOM EQU 10H ; Home Drive Heads CMDRD EQU 20H ; Read Sector Command (w/retry) CMDWR EQU 30H ; Write Sector Command (w/retry) CMDVER EQU 40H ; Verify Sector(s) Command (w/retry) CMDFMT EQU 50H ; Format Track Command CMDDIAG EQU 90H ; Execute Diagnostics Command CMDINIT EQU 91H ; Initialize Drive Params Command CMDPW0 EQU 0E0H ; Low Range of Power Control Commands CMDPW3 EQU 0E3H ; High Range of Power Control Commands CMDPWQ EQU 0E5H ; Power Status Query Command CMDID EQU 0ECH ; Read Drive Ident Data Command ENDIF ;ide ;=================== End Unique Equates ======================= ENDIF ; REMOVE CODE