;
; SBC HARDWARE DEFINITIONS
;
SBC_BASE	.EQU	$60		; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
;
#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))
; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)
MPCL_RAM	.EQU 	SBC_BASE + $18	; MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY)
MPCL_ROM	.EQU 	SBC_BASE + $1C	; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
#ENDIF
;
#IF (PLATFORM == PLT_ZETA2)
MPGSEL_0	.EQU	SBC_BASE + $18	; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_1	.EQU	SBC_BASE + $19	; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_2	.EQU	SBC_BASE + $1A	; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
MPGSEL_3	.EQU	SBC_BASE + $1B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
#ENDIF
;
RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT				;PS