;
; MARK IV HARDWARE DEFINITIONS
;
CPU_BASE	.EQU	$40		; ONLY RELEVANT FOR Z180
;
RAMBIAS		.EQU	512		; RAM STARTS AT 512K
;
MK4_BASE	.EQU	$80
;
MK4_IDE		.EQU	MK4_BASE + $00	; IDE REGISTERS ($00-$07, $0E-$0F)
MK4_XAR		.EQU	MK4_BASE + $08	; EXTERNAL ADDRESS REGISTER (XAR)
MK4_SD		.EQU	MK4_BASE + $09	; SD CARD CONTROL REGISTER
MK4_RTC		.EQU	MK4_BASE + $0A	; RTC INTERFACE REGISTER
;
RTC		.EQU	MK4_RTC		; GENERIC ALIAS FOR RTC PORT
;
; DUMMY VALUES BELOW TO ALLOW DBGMON TO BUILD...
; NEED TO REMOVE AND CLEAN THIS UP LATER.
;
PPIBASE		.EQU	$00
PPIA		.EQU 	PPIBASE + 0	; PORT A
PPIB		.EQU 	PPIBASE + 1	; PORT B
PPIC		.EQU 	PPIBASE + 2	; PORT C
PPIX	 	.EQU 	PPIBASE + 3	; PPI CONTROL PORT
;
; MEMORY BANK CONFIGURATION
;
BID_ROM0	.EQU	$00
BID_ROMN	.EQU	(BID_ROM0 + ((ROMSIZE / 32) - 1))
BID_RAM0	.EQU	$10
BID_RAMN	.EQU	(BID_RAM0 + ((RAMSIZE / 32) - 1))

BID_BOOT	.EQU	BID_ROM0	; BOOT BANK
BID_BIOSIMG	.EQU	BID_ROM0 + 1	; BIOS IMAGE BANK
BID_OSIMG	.EQU	BID_ROM0 + 2	; ROM LOADER AND IMAGES BANK
BID_FSFAT	.EQU	BID_ROM0 + 3	; FAT FILESYSTEM DRIVER BANK
BID_ROMD0	.EQU	BID_ROM0 + 4	; FIRST ROM DRIVE BANK
BID_ROMDN	.EQU	BID_ROMN	; LAST ROM DRIVE BANK

BID_RAMD0	.EQU	BID_RAM0	; FIRST RAM DRIVE BANK
BID_RAMDN	.EQU	BID_RAMN - 4	; LAST RAM DRIVE BANK
BID_AUX		.EQU	BID_RAMN - 3	; AUX BANK (BPBIOS, ETC.)
BID_BIOS	.EQU	BID_RAMN - 2	; BIOS BANK
BID_USR		.EQU	BID_RAMN - 1	; USER BANK (CP/M TPA, ETC.)
BID_COM		.EQU	BID_RAMN	; COMMON BANK, UPPER 32K

;
; Z180 REGISTERS
;
CPU_CNTLA0	.EQU	CPU_BASE + $00	; ASCI0 CONTROL A
CPU_CNTLA1	.EQU	CPU_BASE + $01	; ASCI1 CONTROL A
CPU_CNTLB0	.EQU	CPU_BASE + $02	; ASCI0 CONTROL B
CPU_CNTLB1	.EQU	CPU_BASE + $03	; ASCI1 CONTROL B
CPU_STAT0	.EQU	CPU_BASE + $04	; ASCI0 STATUS
CPU_STAT1	.EQU	CPU_BASE + $05	; ASCI1 STATUS
CPU_TDR0	.EQU	CPU_BASE + $06	; ASCI0 TRANSMIT
CPU_TDR1	.EQU	CPU_BASE + $07	; ASCI1 TRANSMIT
CPU_RDR0	.EQU	CPU_BASE + $08	; ASCI0 RECEIVE
CPU_RDR1	.EQU	CPU_BASE + $09	; ASCI1 RECEIVE
CPU_CNTR	.EQU	CPU_BASE + $0A	; CSI/O CONTROL
CPU_TRDR	.EQU	CPU_BASE + $0B	; CSI/O TRANSMIT/RECEIVE
CPU_TMDR0L	.EQU	CPU_BASE + $0C	; TIMER 0 DATA LO
CPU_TMDR0H	.EQU	CPU_BASE + $0D	; TIMER 0 DATA HI
CPU_RLDR0L	.EQU	CPU_BASE + $0E	; TIMER 0 RELOAD LO
CPU_RLDR0H	.EQU	CPU_BASE + $0F	; TIMER 0 RELOAD HI
CPU_TCR		.EQU	CPU_BASE + $10	; TIMER CONTROL
;	
CPU_ASEXT0	.EQU	CPU_BASE + $12	; ASCI0 EXTENSION CONTROL (Z8S180)
CPU_ASEXT1	.EQU	CPU_BASE + $13	; ASCI1 EXTENSION CONTROL (Z8S180)
;
CPU_TMDR1L	.EQU	CPU_BASE + $14	; TIMER 1 DATA LO
CPU_TMDR1H	.EQU	CPU_BASE + $15	; TIMER 1 DATA HI
CPU_RLDR1L	.EQU	CPU_BASE + $16	; TIMER 1 RELOAD LO
CPU_RLDR1H	.EQU	CPU_BASE + $17	; TIMER 1 RELOAD HI
CPU_FRC		.EQU	CPU_BASE + $18	; FREE RUNNING COUNTER

CPU_ASTC0L	.EQU	CPU_BASE + $1A	; ASCI0 TIME CONSTANT LO (Z8S180)
CPU_ASTC0H	.EQU	CPU_BASE + $1B	; ASCI0 TIME CONSTANT HI (Z8S180)
CPU_ASTC1L	.EQU	CPU_BASE + $1C	; ASCI1 TIME CONSTANT LO (Z8S180)
CPU_ASTC1H	.EQU	CPU_BASE + $1D	; ASCI1 TIME CONSTANT HI (Z8S180)
CPU_CMR		.EQU	CPU_BASE + $1E	; CLOCK MULTIPLIER (LATEST Z8S180)
CPU_CCR		.EQU	CPU_BASE + $1F	; CPU CONTROL (Z8S180)
;
CPU_SAR0L	.EQU	CPU_BASE + $20	; DMA0 SOURCE ADDR LO
CPU_SAR0H	.EQU	CPU_BASE + $21	; DMA0 SOURCE ADDR HI
CPU_SAR0B	.EQU	CPU_BASE + $22	; DMA0 SOURCE ADDR BANK
CPU_DAR0L	.EQU	CPU_BASE + $23	; DMA0 DEST ADDR LO
CPU_DAR0H	.EQU	CPU_BASE + $24	; DMA0 DEST ADDR HI
CPU_DAR0B	.EQU	CPU_BASE + $25	; DMA0 DEST ADDR BANK
CPU_BCR0L	.EQU	CPU_BASE + $26	; DMA0 BYTE COUNT LO
CPU_BCR0H	.EQU	CPU_BASE + $27	; DMA0 BYTE COUNT HI
CPU_MAR1L	.EQU	CPU_BASE + $28	; DMA1 MEMORY ADDR LO
CPU_MAR1H	.EQU	CPU_BASE + $29	; DMA1 MEMORY ADDR HI
CPU_MAR1B	.EQU	CPU_BASE + $2A	; DMA1 MEMORY ADDR BANK
CPU_IAR1L	.EQU	CPU_BASE + $2B	; DMA1 I/O ADDR LO
CPU_IAR1H	.EQU	CPU_BASE + $2C	; DMA1 I/O ADDR HI
CPU_IAR1B	.EQU	CPU_BASE + $2D	; DMA1 I/O ADDR BANK (Z8S180)
CPU_BCR1L	.EQU	CPU_BASE + $2E	; DMA1 BYTE COUNT LO
CPU_BCR1H	.EQU	CPU_BASE + $2F	; DMA1 BYTE COUNT HI
CPU_DSTAT	.EQU	CPU_BASE + $30	; DMA STATUS
CPU_DMODE	.EQU	CPU_BASE + $31	; DMA MODE
CPU_DCNTL	.EQU	CPU_BASE + $32	; DMA/WAIT CONTROL
CPU_IL		.EQU	CPU_BASE + $33	; INTERRUPT VECTOR LOAD
CPU_ITC		.EQU	CPU_BASE + $34	; INT/TRAP CONTROL
;
CPU_RCR		.EQU	CPU_BASE + $36	; REFRESH CONTROL
;
CPU_CBR		.EQU	CPU_BASE + $38	; MMU COMMON BASE REGISTER
CPU_BBR		.EQU	CPU_BASE + $39	; MMU BANK BASE REGISTER
CPU_CBAR	.EQU	CPU_BASE + $3A	; MMU COMMON/BANK AREA REGISTER
;
CPU_OMCR	.EQU	CPU_BASE + $3E	; OPERATION MODE CONTROL
CPU_ICR		.EQU	$3F		; I/O CONTROL REGISTER (NOT RELOCATED!!!)