;
; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
;
MPCL_RAM	.EQU 	$78		; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
MPCL_ROM	.EQU 	$7C		; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
RTC		.EQU	$70		; ADDRESS OF RTC LATCH AND INPUT PORT
;
; PPI 82C55 I/O IS DECODED TO PORT 60-67
;
PPIBASE		.EQU	$60
PPIA		.EQU 	PPIBASE + 0	; PORT A
PPIB		.EQU 	PPIBASE + 1	; PORT B
PPIC		.EQU 	PPIBASE + 2	; PORT C
PPIX	 	.EQU 	PPIBASE + 3	; PPI CONTROL PORT
;
; 16C550 SERIAL LINE UART
;
SIO_BASE	.EQU	$68
SIO_RBR		.EQU	SIO_BASE + 0	; DLAB=0: RCVR BUFFER REG (READ ONLY)
SIO_THR		.EQU	SIO_BASE + 0	; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
SIO_IER		.EQU	SIO_BASE + 1	; DLAB=0: INT ENABLE REG
SIO_IIR		.EQU	SIO_BASE + 2	; INT IDENT REGISTER (READ ONLY)
SIO_FCR		.EQU	SIO_BASE + 2	; FIFO CONTROL REG (WRITE ONLY)
SIO_LCR		.EQU	SIO_BASE + 3	; LINE CONTROL REG
SIO_MCR		.EQU	SIO_BASE + 4	; MODEM CONTROL REG
SIO_LSR		.EQU	SIO_BASE + 5	; LINE STATUS REG
SIO_MSR		.EQU	SIO_BASE + 6	; MODEM STATUS REG
SIO_SCR		.EQU	SIO_BASE + 7	; SCRATCH REGISTER
SIO_DLL		.EQU	SIO_BASE + 0	; DLAB=1: DIVISOR LATCH (LS)
SIO_DLM		.EQU	SIO_BASE + 1	; DLAB=1: DIVISOR LATCH (MS)
;
; MEMORY BANK CONFIGURATION
;
#IFDEF UNALOAD
BID_BOOT	.EQU	$00		; HARDWARE COLD BOOT (SETUP)
BID_COMIMG	.EQU	$02             ; LOADER + CP/M IMAGE TO COPY TO BID_COM
BID_HBIMG	.EQU	$04             ; HBIOS IMAGE TO COPY TO BID_HB
BID_ROMD	.EQU	$05             ; FIRST ROM DRIVE BANK
BID_ROMDN	.EQU	($00 + ((ROMSIZE / 32) - 1))	; LAST ROM DRIVE BANK
BID_USR		.EQU	$80             ; LOW 32K OF TPA
BID_HB		.EQU	$81             ; WORKING COPY OF HBIOS IN RAM
BID_BPB		.EQU	$82             ; BPBIOS BANK
BID_RAMD	.EQU	$83             ; START OF RAM DRIVE
BID_RAMDN	.EQU	($80 + ((RAMSIZE / 32) - 2))	; LAST RAM DRIVE BANK
BID_COM		.EQU	$8F             ; COMMON BANK, UPPER 32K
#ELSE
BID_BOOT	.EQU	$00		; HARDWARE COLD BOOT (SETUP)
BID_COMIMG	.EQU	$00             ; LOADER + CP/M IMAGE TO COPY TO BID_COM
BID_HBIMG	.EQU	$01             ; HBIOS IMAGE TO COPY TO BID_HB
BID_ROMD	.EQU	$02             ; FIRST ROM DRIVE BANK
BID_ROMDN	.EQU	($00 + ((ROMSIZE / 32) - 1))	; LAST ROM DRIVE BANK
BID_USR		.EQU	$80             ; LOW 32K OF TPA
BID_HB		.EQU	$81             ; WORKING COPY OF HBIOS IN RAM
BID_BPB		.EQU	$82             ; BPBIOS BANK
BID_RAMD	.EQU	$83             ; START OF RAM DRIVE
BID_RAMDN	.EQU	($80 + ((RAMSIZE / 32) - 2))	; LAST RAM DRIVE BANK
BID_COM		.EQU	$8F             ; COMMON BANK, UPPER 32K
#ENDIF