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28 lines
1.1 KiB
28 lines
1.1 KiB
;
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; SBC HARDWARE DEFINITIONS
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;
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#DEFINE PLATFORM_NAME "SBC"
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;
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SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
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;
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))
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; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)
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MPCL_RAM .EQU SBC_BASE + $18 ; MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY)
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MPCL_ROM .EQU SBC_BASE + $1C ; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
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#ENDIF
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;
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#IF (PLATFORM == PLT_ZETA2)
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MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
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MPGSEL_1 .EQU SBC_BASE + $19 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
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MPGSEL_2 .EQU SBC_BASE + $1A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
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MPGSEL_3 .EQU SBC_BASE + $1B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
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MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
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#ENDIF
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;
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RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
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PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
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PIOZBASE .EQU $88 ; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
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PIO4BASE .EQU $90 ; ECB-4PIO DEFAULT PIO DEFAULT
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;
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;
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FIFO_BASE .EQU $0C ; ECB USB-FIFO DEFAULT PORT
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