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130 lines
6.8 KiB
130 lines
6.8 KiB
{\rtf1\ansi\ansicpg1252\deff0\nouicompat\deflang1033\deflangfe1033{\fonttbl{\f0\fswiss\fprq2\fcharset0 Arial;}{\f1\fmodern\fprq1\fcharset0 Courier New;}{\f2\fnil\fcharset0 Courier New;}}
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{\colortbl ;\red255\green255\blue0;}
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{\*\generator Riched20 10.0.14393}{\*\mmathPr\mnaryLim0\mdispDef1\mwrapIndent1440 }\viewkind4\uc1
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\pard\nowidctlpar\qc\f0\fs36 BPBIOS Errata\par
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\pard\nowidctlpar\fs22\par
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\ul\fs28 File: deblock.z80 @ SLP0:\par
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\ulnone\fs22\par
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When attempting to increment the sector number for sequential unallocated write matching, HL was pointing one byte past the sector number byte when it was intended to point at the sector number byte. Added a DEC HL to make it point to the right place. Without this fix, there will be far more disk writes than desired, but no data corruption as far as I can tell.\par
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\f1\par
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\fs20 ; More unallocated records remain. Check for any change.\par
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\par
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\tab DEC\tab A\tab\tab ; Decrement unallocated count\par
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\tab LD\tab (UNACNT),A\tab ; And save it\par
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\tab LD\tab B,4\tab\tab ; Compare four bytes\par
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\tab LD\tab HL,UNADSK\tab ; Compare Old Disk, Track & Sector\par
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\tab LD\tab DE,SEKDSK\tab ; .to New Disk, Track & Sector\par
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SLP0:\tab LD\tab A,(DE)\par
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\tab CP\tab (HL)\tab\tab ; Same?\par
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\tab JR\tab NZ,ALLOC\tab ; ..jump if not\par
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\tab INC\tab HL\tab\tab ; Else advance to next\par
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\tab INC\tab DE\par
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\tab DJNZ\tab SLP0\tab\tab ; ..and loop til done\par
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\par
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; Everything matches, anticipate the next sector\par
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\par
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\highlight1\tab DEC\tab HL\tab\tab ; WBW: point back to sector num\par
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\highlight0\tab INC\tab (HL)\tab\tab ; Unasec+1\par
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\tab LD\tab A,(CPMSPT)\tab ; Max sectors per track\par
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\tab CP\tab (HL)\tab\tab ; Compare them\par
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\tab JR\tab NZ,NOOVF\tab ; ..jump if not ready for new track yet\par
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\fs22\par
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\ul\f0\fs28 File: hardide.z80 \strike & hard-dx.z80\strike0 @ HDWRIT:\par
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\ulnone\fs22\par
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HSTACT was being reset instead of HSTWRT at every disk write call. Makes no sense and was causing many extra writes. Switched to HSTWRT which is what the floppy driver does.\par
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\f1\par
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\fs20 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::\par
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; Write to Hard Disk Drive\tab\tab\tab < Internal BIOS Routine >\par
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; Writes from HSTBUF using HSTTRK and HSTSEC to build Block Number.\par
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; NOTE: This routine uses physical drive characteristics from ICFG-xx.\par
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\par
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HDWRIT:\tab XOR\tab A\par
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\highlight1 ;WBW\tab LD\tab (HSTACT),A\tab ; Show no active writes pending\par
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\tab LD\tab (HSTWRT),A\tab ; WBW: Show no active writes pending\par
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\highlight0\par
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\tab LD\tab HL,7CH*256+CMDWR ; Set the IDE Write Command\par
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\tab JR\tab HDRW\tab\tab ; ..continue\par
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\fs22\par
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\ul\f0\fs28\page\strike selrwd.z80 @ SELDK0:\par
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\ulnone\fs22\par
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It appears that if a disk is selected (SELDSK) and is not a new disk login, then, the driver select processing is being bypassed. Does not make sense to me, but not causing any harm that I can see at this point.\par
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\par
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No code fix created yet.\par
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\strike0\par
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\ul\fs28 fdc-dx.z80 @ FDCDN:\par
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\ulnone\fs22\par
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At high clock speeds (>~24MHz) the seek/recal command wait for completion needs to make sure the prior command is not still active.\par
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\par
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\f1\fs20 ;.....\par
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; Check for Proper Termination of Seek/Recalibrate Actions by\par
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; executing a Check Interrupt Command returning ST0 in A.\par
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\par
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FDCDN: PUSH HL\tab\tab ; Don't alter regs\par
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EI\tab\tab\tab\tab ; (Ints Ok Now)\par
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FDCDN0: CALL WRDY\tab\tab ; Ready? (leave Ints alone)\par
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\highlight1 BIT 4,A\tab\tab ; WBW: Prior command still active?\par
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JR NZ,FDCDN0\tab ; WBW: If so, keep checking\par
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\highlight0 LD A,08H\tab\tab ; Else Issue Sense Interrupt Status Comnd\par
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OUT0 (DR),A\par
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CALL WRDY\par
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IN0 A,(DR)\tab\tab ; Get first Result Byte (ST0)\par
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LD L,A\par
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CP 80H\tab\tab ; Invalid Command?\par
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JR Z,FDCDN0\tab ; ..jump to exit if So\par
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CALL WRDY\par
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IN0 A,(DR)\tab\tab ; Read Second Result Byte (Trk #)\par
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LD A,L\par
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BIT 5,A\tab\tab ; Command Complete?\par
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JR Z,FDCDN0\tab ; ..loop if Not\par
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POP HL\par
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RET\par
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ENDIF ;~fddma\f0\fs22\par
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\par
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\ul\fs28\page fdc-dx.z80 @ WRDY:\par
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\ulnone\fs22\par
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At high clock speeds (>~24MHz), a small delay is needed between MSR register reads.\par
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\par
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\f1\fs20 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::\par
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; Wait for FDC RQM to become Ready, and return DIO status in Zero Flag\par
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; Pause before reading status port based on CPU Speed and Data Rate.\par
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\par
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WRDY: LD A,(DLYCNT\tab ; Get computed delay count\par
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WRDY0: DEC A\tab\tab\tab ; Done?\par
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JR NZ,WRDY0\tab ; ..loop if Not\par
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WRDYL: IN A,(MSR\tab\tab ; Read Main Status Register\par
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BIT 7,A\tab\tab ; Interrupt Present?\par
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\highlight1 NOP\tab\tab\tab\tab ; WBW: Reg recovery for hi speed op\par
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\highlight0 RET NZ\tab\tab ; Return if So\par
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JR WRDYL\tab\tab ; Else Loop\par
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\f0\fs22\par
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\ul\fs28 fdc-dx.z80 @ FDRst:\par
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\ulnone\fs22\par
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At high clock speeds (>~24MHz), an additional delay is needed to make sure that the reset minimum timing is met. The code fix below seems to work, but it wold be better to implement a loop based on clock speed.\par
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\par
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\f1\fs20 ========================================================================\par
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; Reset the Floppy Disk Controller. Called from CBOOT in case of Hard\par
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; Disk Boot which leaves the controller in a "hung" state, and locally\par
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; if the Controller times out (often due to changing diskettes).\par
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\par
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FDRst: PUSH AF\tab\tab ; Save any status\par
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XOR A\par
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OUT (DCR),A\tab\tab ; Place Controller in Reset state\par
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\highlight1 EX (SP),HL\tab\tab ; WBW: Delay required at high speed\par
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EX (SP),HL\tab\tab ; WBW: ... to ensure reset works\par
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\highlight0 LD A,(ACTIVE\tab ; get current settings\par
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AND 0FCH\tab\tab ; keep only motors, DMA and Ready\par
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OUT (DCR),A\tab\tab ; and Restore\par
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POP AF\tab\tab ; Restore Status\par
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RET\par
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\f0\fs28\par
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\ul fdc-dx.z80 @ FDCINT:\par
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\ulnone\fs22\par
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At high clock speeds, the FDC interrupt polling loop is insufficient. Assuming the original value of 30 is optimal for 16MHz and assuming we want to handle up to 50MHz now, a reasonable new value is 90.\par
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\par
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\f2\fs20\tab LD\tab BC,0000\tab\tab ; Inner loop timeout\par
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\highlight1 ;\tab LD\tab D,30\tab\tab\tab ; Outer loop timeout\par
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\tab LD\tab D,90\tab\tab\tab ; Outer loop timeout\par
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\highlight0\tab LD\tab HL,ST0\tab\tab ; Point to Status Area\f1\fs22\par
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}
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