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21 lines
764 B
21 lines
764 B
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; Z280 CPU CONTROL REGISTERS (VIA LDCTL)
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Z280_MSR .EQU $00 ; MASTER STATUS REG
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Z280_ISR .EQU $16 ; INTERRUPT STATUS REG
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Z280_VPR .EQU $06 ; INT/TRAP VECT PTR REG
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Z280_IOPR .EQU $08 ; I/O PAGE REG
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Z280_BTIR .EQU $FF ; BUS TIMING & INIT REG
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Z280_BTCR .EQU $02 ; BUS TIMING & CONTROL REG
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Z280_SLR .EQU $04 ; STACK LIMIT REG
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Z280_TCR .EQU $10 ; TRAP CONTROL REG
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Z280_CCR .EQU $12 ; CACHE CONTROL REG
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Z280_LAR .EQU $14 ; LOCAL ADDRESS REG
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; Z280 MMU REGISTERS (I/O PAGE $FF, I/O ADDRESS $FF**NN)
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Z280_MMUMCR .EQU $F0 ; Z280 MMU MASTER CONTROL REG
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Z280_MMUPDRPTR .EQU $F1 ; Z280 MMU PDR POINTER REG
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Z280_MMUINV .EQU $F2 ; Z280 MMU INVALIDATION PORT
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Z280_MMUBLKMOV .EQU $F4 ; Z280 MMU BLOCK MOVE PORT
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Z280_MMUPDR .EQU $F5 ; Z280 MMU PDR PORT
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