mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
872d51e9b6
- Detect CTS at startup to ensure it is asserted. If not, disable hardware flow control to avoid stalling the console at boot. Only for UART driver because this is the only place it is currently relevant.
293 lines
15 KiB
NASM
293 lines
15 KiB
NASM
;
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;==================================================================================================
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; ROMWBW 3.X CONFIGURATION FOR N8
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;==================================================================================================
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;
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; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
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; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
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; UNDER THIS DIRECTORY.
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;
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; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
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; FOR THE PLATFORM.
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;
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#DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]"
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;
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#INCLUDE "hbios.inc"
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;
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PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
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;
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
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BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
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;
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CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
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CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
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CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
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INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
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DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
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;
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
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MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
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RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
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;
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Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
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Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
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Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
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Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
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;
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N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
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N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
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N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR
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N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
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N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
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N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
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;
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RTCIO .EQU N8_RTC ; RTC LATCH REGISTER ADR
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;
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
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;
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
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CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
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CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
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;
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PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
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PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
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;
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EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
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;
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SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
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;
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WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
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;
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FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
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FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
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FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
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FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
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FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
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;
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DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
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;
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LEDENABLE .EQU FALSE ; ENABLES STATUS LED
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LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC]
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LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
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LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
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;
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DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
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DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
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ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
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ICMPPIBASE .EQU N8_PPI0 ; BASE I/O ADDRESS OF ICM PPI
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PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
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PKDPPIBASE .EQU N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI
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PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
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H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
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;
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BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
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CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
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VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
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ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
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KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
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MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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;
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DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
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DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
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;
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DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
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DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
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;
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BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
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BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
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;
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INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
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;
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RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
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;
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HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
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SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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;
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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;
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UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
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UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
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UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
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UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
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UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART
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UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
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UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
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UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
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UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
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UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
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;
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ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
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;
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ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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;
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SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
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SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
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SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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;
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
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;
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VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
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VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
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CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
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CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
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CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
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GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
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TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
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TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
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TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
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VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
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VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
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VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
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SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
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;
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MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
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MDROM .EQU TRUE ; MD: ENABLE ROM DISK
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MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
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MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
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;
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FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
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FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
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FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
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FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
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FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
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FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
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FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
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;
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RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
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RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
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;
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IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
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IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
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IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
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IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
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IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
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IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
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IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
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IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
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IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
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IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
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IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
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IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
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IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
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IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
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IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
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IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
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IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
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IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
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IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
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IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
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;
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PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
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PPIDE0BASE .EQU N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
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PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
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PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
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PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
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PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
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PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
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PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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;
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SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
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SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
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SDPPIBASE .EQU N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
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SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
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SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
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;
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CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
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;
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PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
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PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
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PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
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;
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PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
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;
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ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
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;
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HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
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;
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PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
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PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
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PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
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;
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LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
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;
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PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
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;
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IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
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;
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SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
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;
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PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
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PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
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PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
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PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
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PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
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PIOSBASE .EQU N8_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
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;
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UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
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FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
|
|
;
|
|
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
|
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
|
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
|
SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
|
;
|
|
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
|
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
|
AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
|
|
;
|
|
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
|
;
|
|
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
|
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
|
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
|
;
|
|
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
|
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|