mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
14b005d64e
- The UART driver has been enhanced to allow use of interrupt driven receive buffer and RTS flow control. It will only be used if enabled and the chip detected has no auto-flow control capability.
251 lines
13 KiB
NASM
251 lines
13 KiB
NASM
;
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;==================================================================================================
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; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 Z80
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;==================================================================================================
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;
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; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
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; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
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; UNDER THIS DIRECTORY.
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;
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; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
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; FOR THE PLATFORM.
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;
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#DEFINE PLATFORM_NAME "RC2014"
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;
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PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
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CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
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;
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
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;
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CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ
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INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
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DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
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;
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0)
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ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0)
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MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
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MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
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MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
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;
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RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
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;
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
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;
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
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CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
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CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
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CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
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CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
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CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
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CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
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CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY
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;
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EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
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;
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SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
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SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
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;
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WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
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WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR
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;
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DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
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DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
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DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
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;
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LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
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LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC]
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LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
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LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
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;
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DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
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;
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BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
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CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
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ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
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MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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;
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DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
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DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
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;
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BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
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BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
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;
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INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
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;
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RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
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;
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HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
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SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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;
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
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DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
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DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
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DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
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DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
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DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
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DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
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;
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UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
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UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
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UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
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UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
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UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
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UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
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UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
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;
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ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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;
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Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
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;
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ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
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ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
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ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
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ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
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ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
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ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
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ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
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ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
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ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
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ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
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;
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SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
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SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
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SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
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SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
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SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
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SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
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SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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;
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
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;
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VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
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CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
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NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
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TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
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TMSMODE .EQU TMSMODE_RC ; TMS: DRIVER MODE: TMSMODE_[SCG/N8/RC/RCV9958]
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TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
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VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
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;
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MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
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MDROM .EQU TRUE ; MD: ENABLE ROM DISK
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MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
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MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
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;
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FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
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FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
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FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
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FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
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FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
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FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
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FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
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;
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RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
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;
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IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
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IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
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IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
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IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
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IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
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IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
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IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
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IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
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IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
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IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
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IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
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IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
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IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
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IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
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IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
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IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
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IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
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IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
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IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
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IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
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;
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PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
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PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
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PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
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PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
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PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
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PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
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PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
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PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
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;
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SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
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SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
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SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
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SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
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SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
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SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
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;
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PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
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PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
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PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
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;
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PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
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;
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HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
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;
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PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
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PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
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PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
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;
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UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
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;
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SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
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AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
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SN7CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4
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;
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AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
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AY_CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4
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AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
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;
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SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
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;
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DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
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DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
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DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
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