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524 lines
15 KiB
524 lines
15 KiB
/* std.h 6/1/2012 dwg - c version of std.asm */
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#define TERM_TTY 0
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#define TERM_ANSI 1
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#define TERM_WYSE 2
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#define TERM_VT52 3
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#define DEV_MD 0x00
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#define DEV_FD 0x10
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#define DEV_IDE 0x20
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#define DEV_ATAPI 0x30
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#define DEV_PPIDE 0x40
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#define DEV_SD 0x50
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#define DEV_PRPSD 0x60
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#define DEV_PPPSD 0x70
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#define PLT_N8VEM 1
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#define PLT_ZETA 2
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#define PLT_N8 3
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#define DPNONE 0
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#define DPDIO 1
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#define DPZETA 2
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#define DPDIDE 3
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#define DPN8 4
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#define DPDIO3 5
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#define VPNONE 0 /* NO VDU */
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#define VPVDU 1 /* ORIGINAL ECB VDU (6545 CHIP) */
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#define VPVDUC 2 /* ECB VDU COLOR (PENDING HARDWARE DEVELOPMENT) */
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#define VPPROPIO 3 /* ECB PROPIO (NOT IMPLEMENTED) */
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#define VPN8 4 /* N8 ONBOARD VIDEO SUBSYSTEM (NOT IMPLEMENTED) */
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#define CLRNEV 0 /* never clear ram disk */
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#define CLRAUTO 1 /* clear if invalid dir entries */
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#define CLRALLW 2 /* always clear ram disk */
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#define FDM720 0 /* 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS */
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#define FDM144 1 /* 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS */
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#define FDM360 2 /* 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS */
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#define FDM120 3 /* 3.5" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS */
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#define BTMENU 1
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#define BTAUTO 2
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/*
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; BT$MENU equ 1 ; WAIT FOR MENU SELECTION AT LOADER PROMPT
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; BT$AUTO equ 2 ; AUTO SELECT BOOT$DEFAULT AFTER BOOT$TIMEOUT
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*/
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/*
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; DIOPLT$NONE equ 0 ; NO DISK IO HARDWARE
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; DIOPLT$DISKIO equ 1 ; N8VEM ECB DISK IO BOARD
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; DIOPLT$ZETA equ 2 ; ZETA BUILT-IN DISK IO SECTION
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; DIOPLT$DIDE equ 3 ; N8VEM ECB DUAL IDE W/ FLOPPY BOARD
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; DIOPLT$N8 equ 4 ; N8 BUILT-IN DISK IO SECTION
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; DIOPLT$DISKIO3 equ 5 ; N8VEM ECB DISK IO V3 BOARD
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; std.lib 2/21/2012 dwg - added TERM$VT52
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; TRUE equ 1
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; FALSE equ 00
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;
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; PRIMARY HARDWARE PLATFORMS
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; PLT$N8VEM equ 1 ; N8VEM ECB Z80 SBC
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; PLT$ZETA equ 2 ; ZETA Z80 SBC
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; PLT$N8 equ 3 ; N8 (HOME COMPUTER) Z180 SBC
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;
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; BOOT STYLE
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; BT$MENU equ 1 ; WAIT FOR MENU SELECTION AT LOADER PROMPT
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; BT$AUTO equ 2 ; AUTO SELECT BOOT$DEFAULT AFTER BOOT$TIMEOUT
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;
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; VDU PLATFORM SELECTIONS
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;
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;
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; VDUPLT$NONE equ 0 ; NO VDU
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; VDUPLT$VDU equ 1 ; ORIGINAL ECB VDU (6545 CHIP)
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; VDUPLT$VDUC equ 2 ; ECB VDU COLOR (PENDING HARDWARE DEVELOPMENT)
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; VDUPLT$PROPIO equ 3 ; ECB PROPIO (NOT IMPLEMENTED)
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; VDUPLT$N8 equ 4 ; N8 ONBOARD VIDEO SUBSYSTEM (NOT IMPLEMENTED)
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;
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; RAM DISK INITIALIZATION OPTIONS
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; CLR$NEVER equ 0 ; NEVER CLEAR RAM DISK
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; CLR$AUTO equ 1 ; CLEAR RAM DISK IF INVALID DIR ENTRIES
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; CLR$ALWAYS equ 2 ; ALWAYS CLEAR RAM DISK
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;
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;
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; ; DISK MAP SELECTION OPTIONS
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;
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; DM$ROM equ 1 ; ROM DRIVE PRIORITY
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; DM$RAM equ 2 ; RAM DRIVE PRIORITY
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; DM$FD equ 3 ; FLOPPY DRIVE PRIORITY
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; DM$IDE equ 4 ; IDE DRIVE PRIORITY
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; DM$PPIDE equ 5 ; PPIDE DRIVE PRIORITY
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; DM$SD equ 6 ; SD DRIVE PRIORITY
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; DM$PRPSD equ 7 ; PROPIO SD DRIVE PRIORITY
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;
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;
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; ; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD$TBL)
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;
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;
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; FDM720 equ 0 ; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
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; FDM144 equ 1 ; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
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; FDM360 equ 2 ; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
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; FDM120 equ 3 ; 3.5" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
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;
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;
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; ; DISK PLATFORM SELECTIONS
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;
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; DIOPLT$NONE equ 0 ; NO DISK IO HARDWARE
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; DIOPLT$DISKIO equ 1 ; N8VEM ECB DISK IO BOARD
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; DIOPLT$ZETA equ 2 ; ZETA BUILT-IN DISK IO SECTION
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; DIOPLT$DIDE equ 3 ; N8VEM ECB DUAL IDE W/ FLOPPY BOARD
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; DIOPLT$N8 equ 4 ; N8 BUILT-IN DISK IO SECTION
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; DIOPLT$DISKIO3 equ 5 ; N8VEM ECB DISK IO V3 BOARD
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;
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; CONSOLE DEVICE CHOICES FOR LDRCON AND DBGCON IN CONFIG SETTINGS
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;
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; CON$UART equ 1
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; CON$VDU equ 2
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; CON$PRP equ 3
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;
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; CONSOLE TERMINAL TYPE CHOICES
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;
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TERM$TTY equ 0
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TERM$ANSI equ 1
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TERM$WYSE equ 2
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TERM$VT52 equ 3
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;
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;
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; ; SYSTEM GENERATION SETTINGS
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;
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; SYS$CPM equ 1 ; CPM (IMPLIES BDOS + CCP)
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; SYS$ZSYS equ 2 ; ZSYSTEM OS (IMPLIES ZSDOS + ZCPR)
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;
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; DOS$BDOS equ 1 ; BDOS
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; DOS$ZDDOS equ 2 ; ZDDOS VARIANT OF ZSDOS
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; DOS$ZSDOS equ 3 ; ZSDOS
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;
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; CP$CCP equ 1 ; CCP COMMAND PROCESSOR
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; CP$ZCPR equ 2 ; ZCPR COMMAND PROCESSOR
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;
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; CONFIGURE DOS (DOS) AND COMMAND PROCESSOR (CP) BASED ON SYSTEM SETTING (SYS)
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;
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;
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; #IFNDEF BLD$SYS
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; SYS equ SYS$CPM
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; #ELSE
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; SYS equ BLD$SYS
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; #ENDIF
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;
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; #IF (SYS == SYS$CPM)
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; DOS equ DOS$BDOS
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; CP equ CP$CCP
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; #DEFINE OSLBL "CP/M-80 2.2C"
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; #ENDIF
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;
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; #IF (SYS == SYS$ZSYS)
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; DOS equ DOS$ZSDOS
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; CP equ CP$ZCPR
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; #DEFINE OSLBL "ZSYSTEM (ZSDOS 1.2, ZCPR 1.0)"
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; #ENDIF
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;
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;
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; ; INCLUDE VERSION AND BUILD SETTINGS
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;
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; #INCLUDE "ver.inc" ; ADD BIOSVER
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;
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;
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; #INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
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;
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;
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; #IF (PLATFORM NE PLT$N8)
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;
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;
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; ; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
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; MPCL$RAM equ 78H ; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
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; MPCL$ROM equ 7CH ; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
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;
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;
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; ; HARDWARE INTERFACES
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;
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; PIO 82C55 I/O IS DECODED TO PORT 60-67
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; PIOA equ 60H ; PORT A
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; PIOB equ 61H ; PORT B
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; PIOC equ 62H ; PORT C
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; PIOX equ 63H ; PIO CONTROL PORT
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;
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; 16C550 SERIAL LINE UART
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;
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; SIO$BASE equ 68H
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; SIO$RBR equ SIO$BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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; SIO$THR equ SIO$BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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; SIO$IER equ SIO$BASE + 1 ; DLAB=0: INT ENABLE REG
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; SIO$IIR equ SIO$BASE + 2 ; INT IDENT REGISTER (READ ONLY)
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; SIO$FCR equ SIO$BASE + 2 ; FIFO CONTROL REG (WRITE ONLY)
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; SIO$LCR equ SIO$BASE + 3 ; LINE CONTROL REG
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; SIO$MCR equ SIO$BASE + 4 ; MODEM CONTROL REG
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; SIO$LSR equ SIO$BASE + 5 ; LINE STATUS REG
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; SIO$MSR equ SIO$BASE + 6 ; MODEM STATUS REG
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; SIO$SCR equ SIO$BASE + 7 ; SCRATCH REGISTER
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; SIO$DLL equ SIO$BASE + 0 ; DLAB=1: DIVISOR LATCH (LS)
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; SIO$DLM equ SIO$BASE + 1 ; DLAB=1: DIVISOR LATCH (MS)
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; #ENDIF ; (PLATFORM NE PLT$N8)
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;
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;
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; #IF (PLATFORM NE PLT$N8)
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;
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;
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; ; Z180 REGISTERS
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;
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;
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; CPU$IOBASE equ 40H ; ONLY RELEVANT FOR Z180
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; CPU$CNTLA0 equ CPU$IOBASE+$00 ;ASCI0 control A
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; CPU$CNTLA1 equ CPU$IOBASE+$01 ;ASCI1 control A
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; CPU$CNTLB0 equ CPU$IOBASE+$02 ;ASCI0 control B
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; CPU$CNTLB1 equ CPU$IOBASE+$03 ;ASCI1 control B
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; CPU$STAT0 equ CPU$IOBASE+$04 ;ASCI0 status
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; CPU$STAT1 equ CPU$IOBASE+$05 ;ASCI1 status
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; CPU$TDR0 equ CPU$IOBASE+$06 ;ASCI0 transmit
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; CPU$TDR1 equ CPU$IOBASE+$07 ;ASCI1 transmit
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; CPU$RDR0 equ CPU$IOBASE+$08 ;ASCI0 receive
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; CPU$RDR1 equ CPU$IOBASE+$09 ;ASCI1 receive
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; CPU$CNTR equ CPU$IOBASE+$0A ;CSI/O control
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; CPU$TRDR equ CPU$IOBASE+$0B ;CSI/O transmit/receive
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; CPU$TMDR0L equ CPU$IOBASE+$0C ;Timer 0 data lo
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; CPU$TMDR0H equ CPU$IOBASE+$0D ;Timer 0 data hi
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; CPU$RLDR0L equ CPU$IOBASE+$0E ;Timer 0 reload lo
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; CPU$RLDR0H equ CPU$IOBASE+$0F ;Timer 0 reload hi
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; CPU$TCR equ CPU$IOBASE+$10 ;Timer control
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; CPU$ASEXT0 equ CPU$IOBASE+$12 ;ASCI0 extension control (Z8S180)
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; CPU$ASEXT1 equ CPU$IOBASE+$13 ;ASCI1 extension control (Z8S180)
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; CPU$TMDR1L equ CPU$IOBASE+$14 ;Timer 1 data lo
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; CPU$TMDR1H equ CPU$IOBASE+$15 ;Timer 1 data hi
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; CPU$RLDR1L equ CPU$IOBASE+$16 ;Timer 1 reload lo
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; CPU$RLDR1H equ CPU$IOBASE+$17 ;Timer 1 reload hi
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; CPU$FRC equ CPU$IOBASE+$18 ;Free running counter
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; CPU$ASTC0L equ CPU$IOBASE+$1A ;ASCI0 Time constant lo (Z8S180)
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; CPU$ASTC0H equ CPU$IOBASE+$1B ;ASCI0 Time constant hi (Z8S180)
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; CPU$ASTC1L equ CPU$IOBASE+$1C ;ASCI1 Time constant lo (Z8S180)
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; CPU$ASTC1H equ CPU$IOBASE+$1D ;ASCI1 Time constant hi (Z8S180)
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; CPU$CMR equ CPU$IOBASE+$1E ;Clock multiplier (latest Z8S180)
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; CPU$CCR equ CPU$IOBASE+$1F ;CPU control (Z8S180)
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; CPU$SAR0L equ CPU$IOBASE+$20 ;DMA0 source addr lo
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; CPU$SAR0H equ CPU$IOBASE+$21 ;DMA0 source addr hi
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; CPU$SAR0B equ CPU$IOBASE+$22 ;DMA0 source addr bank
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; CPU$DAR0L equ CPU$IOBASE+$23 ;DMA0 dest addr lo
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; CPU$DAR0H equ CPU$IOBASE+$24 ;DMA0 dest addr hi
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; CPU$DAR0B equ CPU$IOBASE+$25 ;DMA0 dest addr bank
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; CPU$BCR0L equ CPU$IOBASE+$26 ;DMA0 byte count lo
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; CPU$BCR0H equ CPU$IOBASE+$27 ;DMA0 byte count hi
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; CPU$MAR1L equ CPU$IOBASE+$28 ;DMA1 memory addr lo
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; CPU$MAR1H equ CPU$IOBASE+$29 ;DMA1 memory addr hi
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; CPU$MAR1B equ CPU$IOBASE+$2A ;DMA1 memory addr bank
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; CPU$IAR1L equ CPU$IOBASE+$2B ;DMA1 I/O addr lo
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; CPU$IAR1H equ CPU$IOBASE+$2C ;DMA1 I/O addr hi
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; CPU$IAR1B equ CPU$IOBASE+$2D ;DMA1 I/O addr bank (Z8S180)
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; CPU$BCR1L equ CPU$IOBASE+$2E ;DMA1 byte count lo
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; CPU$BCR1H equ CPU$IOBASE+$2F ;DMA1 byte count hi
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; CPU$DSTAT equ CPU$IOBASE+$30 ;DMA status
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; CPU$DMODE equ CPU$IOBASE+$31 ;DMA mode
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; CPU$DCNTL equ CPU$IOBASE+$32 ;DMA/WAIT control
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; CPU$IL equ CPU$IOBASE+$33 ;Interrupt vector load
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; CPU$ITC equ CPU$IOBASE+$34 ;INT/TRAP control
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; CPU$RCR equ CPU$IOBASE+$36 ;Refresh control
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; CPU$CBR equ CPU$IOBASE+$38 ;MMU common base register
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; CPU$BBR equ CPU$IOBASE+$39 ;MMU bank base register
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; CPU$CBAR equ CPU$IOBASE+$3A ;MMU common/bank area register
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; CPU$OMCR equ CPU$IOBASE+$3E ;Operation mode control
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; CPU$ICR equ $3F ;I/O control register (not relocated)
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;
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; N8 ONBOARD I/O REGISTERS
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; N8$IOBASE equ $80
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; PIO equ N8$IOBASE+$00
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; PIOA equ PIO+$00 ; PORT A
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; PIOB equ PIO+$01 ; PORT B
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; PIOC equ PIO+$02 ; PORT C
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; PIOX equ PIO+$03 ; PIO CONTROL PORT
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; PIO2 equ N8$IOBASE+$04
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; PIO2A equ PIO2+$00 ; PORT A
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; PIO2B equ PIO2+$01 ; PORT B
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; PIO2C equ PIO2+$02 ; PORT C
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; PIO2X equ PIO2+$03 ; PIO CONTROL PORT
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;
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; RTC equ N8$IOBASE+$08 ;RTC latch and buffer
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; FDC equ N8$IOBASE+$0C ;Floppy disk controller
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; UTIL equ N8$IOBASE+$10 ;Floppy disk utility
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; ACR equ N8$IOBASE+$14 ;auxillary control register
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; RMAP equ N8$IOBASE+$16 ;ROM page register
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; VDP equ N8$IOBASE+$18 ;Video Display Processor (TMS9918A)
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; PSG equ N8$IOBASE+$1C ;Programmable Sound Generator (AY-3-8910)
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;
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; DEFACR equ $1B
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;
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; #ENDIF
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;
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;
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; ; CHARACTER DEVICE FUNCTIONS
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;
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;
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; CF$INIT equ 0
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; CF$IN equ 1
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; CF$IST equ 2
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; CF$OUT equ 3
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; CF$OST equ 4
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;
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; DISK OPERATIONS
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; DOP$READ equ 0 ; READ OPERATION
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; DOP$WRITE equ 1 ; WRITE OPERATION
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; DOP$FORMAT equ 2 ; FORMAT OPERATION
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; DOP$READID equ 3 ; READ ID OPERATION
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;
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; DISK DRIVER FUNCTIONS
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; DF$READY equ 1
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; DF$SELECT equ 2
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; DF$READ equ 3
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; DF$WRITE equ 4
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; DF$FORMAT equ 5
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;
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; DISK DEVICES (ONLY FIRST NIBBLE RELEVANT, SECOND NIBBLE MUST BE ZERO)
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; DEV$MD equ 000H
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; DEV$FD equ 010H
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; DEV$IDE equ 020H
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; DEV$ATAPI equ 030H
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; DEV$PPIDE equ 040H
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; DEV$SD equ 050H
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; DEV$PRPSD equ 060H
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;
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; IMG$START equ 00000H ; IMMUTABLE: ROM IMAGE AREA START
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; IMG$END equ 08000H ; IMMUTABLE: ROM IMAGE AREA END
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;
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; PG0$LOC equ 00000H ; IMMUTABLE
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; PG0$SIZ equ 00100H ; IMMUTABLE
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; PG0$END equ PG0$LOC + PG0$SIZ
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; PG0$IMG equ IMG$START ; IMMUTABLE
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; LDR$LOC equ PG0$END
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; LDR$SIZ equ 02000H - PG0$SIZ ; CONFIGURABLE
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; LDR$END equ LDR$LOC + LDR$SIZ
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; LDR$IMG equ PG0$IMG + PG0$SIZ
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; CPM$LOC equ 0D000H ; CONFIGURABLE: LOCATION OF CPM FOR RUNNING SYSTEM
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; CPM$END equ 10000H ; IMMUTABLE: TOP OF MEMORY
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; CPM$SIZ equ CPM$END - CPM$LOC ; SIZE OF CPM IMAGE (CCP + BDOS + CBIOS (INCLUDING DATA))
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; CPM$ENT equ CPM$LOC + 01600H ; IMMUTABLE: CPM ENTRY POINT
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; CPM$IMG equ LDR$IMG + LDR$SIZ ; START OF CONCATENATED CPM IMAGE
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; DAT$SIZ equ DATASIZE ; FROM CONFIG FILE
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; DAT$END equ CPM$END
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; DAT$LOC equ DAT$END - DAT$SIZ
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; BIOS$LOC equ CPM$ENT
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; BIOS$END equ DAT$LOC
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; BIOS$SIZ equ DAT$LOC - CPM$ENT
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; MON$IMG equ CPM$IMG + CPM$SIZ ; LOCATION OF MONITOR BINARY IMAGE IN ROM
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; MON$LOC equ 08000H ; LOCATION OF MONITOR FOR RUNNING SYSTEM
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; MON$SIZ equ 01000H ; SIZE OF MONITOR BINARY IMAGE
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; MON$END equ MON$LOC + MON$SIZ
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; MON$DSKY equ MON$LOC ; MONITOR ENTRY (DSKY)
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; MON$UART equ MON$LOC + 3 ; MONITOR ENTRY (UART)
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; ROMX$LOC equ MON$IMG + MON$SIZ ; LOCATION OF ROM EXTENSION CODE
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;
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;
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; ROMX$SIZ equ 02000H ; FIXED
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; ROMX$END equ ROMX$LOC + ROMX$SIZ
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;
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;
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; VDU$LOC equ ROMX$LOC + 0 ; LOCATION OF ROM VDU DRIVER
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;
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;
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; CBIOS$BOOT equ BIOS$LOC + 0
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; CBIOS$WBOOT equ BIOS$LOC + 3
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; CBIOS$CONST equ BIOS$LOC + 6
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; CBIOS$CONIN equ BIOS$LOC + 9
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; CBIOS$CONOUT equ BIOS$LOC + 12
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; CBIOS$LIST equ BIOS$LOC + 15
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; CBIOS$PUNCH equ BIOS$LOC + 18
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; CBIOS$READER equ BIOS$LOC + 21
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; CBIOS$HOME equ BIOS$LOC + 24
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; CBIOS$SELDSK equ BIOS$LOC + 27
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; CBIOS$SETTRK equ BIOS$LOC + 30
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; CBIOS$SETSEC equ BIOS$LOC + 33
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; CBIOS$SETDMA equ BIOS$LOC + 36
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; CBIOS$READ equ BIOS$LOC + 39
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; CBIOS$WRITE equ BIOS$LOC + 42
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; CBIOS$LISTST equ BIOS$LOC + 45
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; CBIOS$SECTRN equ BIOS$LOC + 48
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;
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; MEMORY CONFIGURATION
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;
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; MSIZE equ 59 ; CP/M VERSION MEMORY SIZE IN KILOBYTES
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;
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; "BIAS" IS ADDRESS OFFSET FROM 3400H FOR MEMORY SYSTEMS
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; ; THAN 16K (REFERRED TO AS "B" THROUGHOUT THE TEXT)
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;
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; BIAS equ (MSIZE-20)*1024
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; CCP equ 3400H+BIAS ; BASE OF CCP
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; BDOS equ CCP+806H ; BASE OF BDOS
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; BIOS equ CCP+1600H ; BASE OF BIOS
|
|
; CCPSIZ equ 00800H
|
|
;
|
|
; #IF (PLATFORM == PLT$N8VEM)
|
|
;
|
|
;
|
|
; ; #DEFINE PLATFORM$NAME "N8VEM Z80 SBC"
|
|
;
|
|
;
|
|
; ; #ENDIF
|
|
;
|
|
;
|
|
; ; #IF (PLATFORM == PLT$ZETA)
|
|
; ; #DEFINE PLATFORM$NAME "ZETA Z80 SBC"
|
|
; ; #ENDIF
|
|
;
|
|
;
|
|
; ; #IF (PLATFORM == PLT$N8)
|
|
; ; #DEFINE PLATFORM$NAME "N8 Z180 SBC"
|
|
; ; #ENDIF
|
|
;
|
|
; #IF (DSKYENABLE)
|
|
; ; #DEFINE DSKYLBL ", DSKY"
|
|
; ; #ELSE
|
|
; ; #DEFINE DSKYLBL ""
|
|
; ; #ENDIF
|
|
;
|
|
; #IF (VDUENABLE)
|
|
; #DEFINE VDULBL ", VDU"
|
|
; #ELSE
|
|
; #DEFINE VDULBL ""
|
|
; #ENDIF
|
|
;
|
|
; #IF (DIOPLT NE DIOPLT$NONE)
|
|
;
|
|
;
|
|
; #IF (DIOPLT EQ DIOPLT$DISKIO)
|
|
; #DEFINE DIOLBL ", DISKIO"
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; #IF (DIOPLT EQ DIOPLT$ZETA)
|
|
; #DEFINE DIOLBL ""
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; #IF (DIOPLT EQ DIOPLT$DIDE)
|
|
; #DEFINE DIOLBL ", DUALIDE"
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; #IF (DIOPLT EQ DIOPLT$N8)
|
|
; #DEFINE DIOLBL ""
|
|
; #ENDIF
|
|
;
|
|
; #IF (DIOPLT EQ DIOPLT$DISKIO3)
|
|
; #DEFINE DIOLBL ", DISKIO-V3"
|
|
; #ENDIF
|
|
;
|
|
; #ELSE
|
|
; #DEFINE DIOLBL ""
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; ; #ENDIF
|
|
;
|
|
;
|
|
; #IF (FDENABLE)
|
|
; #IF (FDMAUTO)
|
|
; #DEFINE FDLBL ", FLOPPY (AUTOSIZE)"
|
|
; #ELSE
|
|
; #IF (FDMEDIA == FDM720)
|
|
; #DEFINE FDLBL ", FLOPPY (720KB)"
|
|
; #ENDIF
|
|
; #IF (FDMEDIA == FDM144)
|
|
; #DEFINE FDLBL ", FLOPPY (1.44MB)"
|
|
; #ENDIF
|
|
; #ENDIF
|
|
; #ELSE
|
|
; #DEFINE FDLBL ""
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; #IF (IDEENABLE)
|
|
; #DEFINE IDELBL ", IDE"
|
|
; #ELSE
|
|
; #DEFINE IDELBL ""
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; #IF (PPIDEENABLE)
|
|
; #DEFINE PPIDELBL ", PPIDE"
|
|
; #ELSE
|
|
; #DEFINE PPIDELBL ""
|
|
; #ENDIF
|
|
;
|
|
; #IF (SDENABLE)
|
|
; #DEFINE SDLBL ", SD CARD"
|
|
; #ELSE
|
|
; #DEFINE SDLBL ""
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; #IF (PRPSDENABLE)
|
|
; #DEFINE PRPSDLBL ", PROPIO SD CARD"
|
|
; #ELSE
|
|
; #DEFINE PRPSDLBL ""
|
|
; #ENDIF
|
|
;
|
|
;
|
|
; ; .ECHO "Configuration: "
|
|
; ; .ECHO PLATFORM$NAME
|
|
; ; .ECHO DSKYLBL
|
|
; ; .ECHO VDULBL
|
|
; ; .ECHO DIOLBL
|
|
; ; .ECHO FDLBL
|
|
; ; .ECHO IDELBL
|
|
; ; .ECHO PPIDELBL
|
|
; ; .ECHO SDLBL
|
|
; ; .ECHO PRPSDLBL
|
|
; ; .ECHO "\n"
|
|
; ;
|
|
;
|
|
; eof - std.lib
|
|
|
|
*/
|
|
|