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1134 lines
33 KiB
1134 lines
33 KiB
; The purpose of this file is to define generic symbols and to include
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; the requested build configuration file to bring in platform specifics.
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; There are several hardware platforms supported by SBC.
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; 1. SBC Z80 SBC (v1 or v2) w/ ECB interface
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; 2. ZETA Standalone Z80 SBC w/ SBC compatibility
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; 3. ZETA2 Second version of ZETA with enhanced memory bank switching
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; 4. N8 MSX-ish Z180 SBC w/ onboard video and sound
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; 5. MK4 Mark IV Z180 based SBC w/ ECB interface
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; 6. UNA Any Z80/Z180 computer with UNA BIOS
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; 7. RCZ80 RCBUS based system with 512K banked RAM/ROM card
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; 8. RCZ180 RCBUS based system with Z180 CPU
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; 9. EZZ80 Easy Z80, Z80 SBC w/ RCBUS and CTC
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; 10. SCZ180 Steve Cousins Z180 based system
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; 11. DYNO Steve Garcia's Dyno Micro-ATX Motherboard
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; 12. RCZ280 Z280 CPU on RCBUS or ZZ80MB
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; 13. MBC Andrew Lynch's Multi Board Computer
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; 14. RPH Andrew Lynch's RHYOPHYRE Graphics Computer
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; 15. Z80RETRO Peter Wilson's Z80-Retro Computer
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; 16. SZ180 S100 Computers Z180-based System
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; 17. DUO Andrew Lynch's Duodyne Computer
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; 18. HEATH Les Bird's Heath Z80 Board
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; 19. EPITX Alan Cox' Mini-ITX System
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; 20. MON Jacques Pelletier's Monsputer (deprecated)
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; 21. GMZ180 Doug Jacksons' Genesis Z180 System
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; 22. NABU NABU w/ Les Bird's RomWBW Option Board
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; 23. SZ80 S100 Computers Z80-based System
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; 24. RCEZ80 RCBus eZ80
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; 25. MSX MSX Computers
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;
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;
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; INCLUDE BUILD VERSION
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;
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#INCLUDE "../ver.inc" ; ADD BIOSVER
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;
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FALSE .EQU 0
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TRUE .EQU ~FALSE
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;
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; CONTROLS PRINTING OF SYSTEM INFORMATION IN ASSEMBLY OUTPUT
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;
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#IFDEF SYSINFO
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#DEFINE SYSECHO .ECHO
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#ELSE
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#DEFINE SYSECHO \;
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#ENDIF
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;
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; DEBUGGING OPTIONS
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;
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USENONE .EQU 0 ; NO DEBUG
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USEXIO .EQU 1 ; BASIC SERIAL DRIVER
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USEMIO .EQU 2 ; MEMORY BUFFER DRIVER
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WBWDEBUG .EQU USENONE
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;
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; DIAGNOSTIC LEVEL OPTIONS
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;
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DL_NONE .EQU 0 ; HBIOS DISPLAY NO MESSAGES
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DL_CRITICAL .EQU 4 ; HBIOS DISPLAY CRITICAL ERROR MESSAGES
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DL_ERROR .EQU 8 ; HBIOS DISPLAYS ALL ERROR MESSAGES
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DL_WARNING .EQU 12 ; HBIOS DISPLAYS WARNING MESSAGES
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DL_INFO .EQU 16 ; HBIOS DISPLAYS INFORMATIONAL MESSAGES
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DL_DETAIL .EQU 20 ; HBIOS DISPLAYS DETAILED DIAGNOSTIC MESSAGES
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DL_VERBOSE .EQU 24 ; HBIOS DISPLAYS ANYTHING IT KNOWS HOW TO
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;
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; CPU TYPES
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;
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CPU_NONE .EQU 0 ; NO CPU TYPE DEFINED
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CPU_Z80 .EQU 1 ; Z80 FAMILY
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CPU_Z180 .EQU 2 ; Z180 FAMILY
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CPU_Z280 .EQU 3 ; Z280 FAMILY
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CPU_EZ80 .EQU 4 ; eZ280 FAMILY
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;
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; BIOS MODE
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;
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BIOS_NONE .EQU 0 ; NO BIOS TYPE DEFINED
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BIOS_WBW .EQU 1 ; ROMWBW HBIOS
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BIOS_UNA .EQU 2 ; UNA UBIOS
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;
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; HBIOS BOOT MODES
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;
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BM_ROMBOOT .EQU 1 ; ROM BOOT
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BM_APPBOOT .EQU 2 ; APPLICATION BOOT
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BM_IMGBOOT .EQU 3 ; IMAGE BOOT (DEPRECATED)
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;
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; HBIOS STARTUP MODES
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;
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START_WARM .EQU 1 ; COLD START
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START_COLD .EQU 2 ; WARM START
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;
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; MEMORY MANAGERS
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;
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MM_NONE .EQU 0
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MM_SBC .EQU 1 ; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
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MM_Z2 .EQU 2 ; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
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MM_N8 .EQU 3 ; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
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MM_Z180 .EQU 4 ; Z180 NATIVE MEMORY MANAGER
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MM_Z280 .EQU 5 ; Z280 NATIVE MEMORY MANAGER
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MM_ZRC .EQU 6 ; ZRC BANK SWITCHING
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MM_MBC .EQU 7 ; MBC MEMORY MANAGER
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MM_RPH .EQU 8 ; Z180 WITH RPH EXTENSIONS
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MM_MON .EQU 9 ; MONSPUTER MMU (DEPRECATED)
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MM_EZ512 .EQU 10 ; EZ512 BANK SWITCHING
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MM_SZ80 .EQU 11 ; S100 Z80 CPU ONBAORD MEMORY MANAGER
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MM_MSX .EQU 12 ; MSX RAM MAPPER MEMORY MANAGER
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;
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; BOOT STYLE
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;
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BT_MENU .EQU 1 ; WAIT FOR MENU SELECTION AT LOADER PROMPT
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BT_AUTO .EQU 2 ; AUTO SELECT BOOT_DEFAULT AFTER BOOT_TIMEOUT
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;
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; BOOT RECOVERY METHODS
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;
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BT_REC_NONE .EQU 0 ; NO RECOVERY MODE
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BT_REC_FORCE .EQU 1 ; FORCE BOOT RECOVERY MODE
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BT_REC_SBCB0 .EQU 2 ; ECB-SBCV2 - BIT 0 RTC HIGH
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BT_REC_SBC1B .EQU 3 ; ECB-SBCV2/MBC - 1-BIT IO PORT
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BT_REC_SBCRI .EQU 4 ; ECB-SBCV2 - 16550 UART RING INDICATOR LINE
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BT_REC_DUORI .EQU 5 ; DUO MULTI I/O - TL16C2552FN UART RING INDICATOR LINE
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;
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; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL)
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;
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FDM720 .EQU 0 ; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
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FDM144 .EQU 1 ; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
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FDM360 .EQU 2 ; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
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FDM120 .EQU 3 ; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
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FDM111 .EQU 4 ; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
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;
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; FLOPPY DISK TYPE
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;
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FDT_NONE .EQU 0 ; NONE
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FDT_3DD .EQU 1 ; 3.5" FLOPPY, DOUBLE DENSITY
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FDT_3HD .EQU 2 ; 3.5" FLOPPY, HIGH DENSITY
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FDT_5DD .EQU 3 ; 5.25" FLOPPY, DOUBLE DENSITY
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FDT_5HD .EQU 4 ; 5.25" FLOPPY, HIGH DNSITY
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FDT_8 .EQU 5 ; 8" FLOPPY, DOUBLE DENSITY
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;
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; ZILOG CTC MODE SELECTIONS
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;
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CTCMODE_NONE .EQU 0 ; NO CTC
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CTCMODE_CTR .EQU 1 ; CTC COUNTER
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CTCMODE_TIM16 .EQU 2 ; CTC TIMER W/ DIV 16
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CTCMODE_TIM256 .EQU 3 ; CTC TIMER W/ DIV 256
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;
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; DS1302 RTC MODE SELECTIONS
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;
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DSRTCMODE_NONE .EQU 0 ; NO DSRTC
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DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
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DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT
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DSRTCMODE_K80W .EQU 3 ; K80W
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;
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; DS1307 RTC MODE SELECTIONS
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;
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DS7RTCMODE_NONE .EQU 0 ; NO DSRTC
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DS7RTCMODE_PCF .EQU 1 ; PCF8584 I2C
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;
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; SIO MODE SELECTIONS
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;
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SIOMODE_NONE .EQU 0
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SIOMODE_STD .EQU 1 ; STD SIO REG CFG (EZZ80, KIO)
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SIOMODE_RC .EQU 2 ; RCBUS SIO MODULE (SPENCER OWEN)
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SIOMODE_SMB .EQU 3 ; RCBUS SIO MODULE (SCOTT BAKER)
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SIOMODE_ZP .EQU 4 ; ECB-ZILOG PERIPHERALS BOARD
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SIOMODE_Z80R .EQU 5 ; SIO A/B SWAPPED
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;
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; TYPE OF CONSOLE BELL TO USE
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;
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CONBELL_NONE .EQU 0
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CONBELL_PSG .EQU 1
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CONBELL_IOBIT .EQU 2
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;
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; LED MODE SELECTIONS
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;
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LEDMODE_NONE .EQU 0
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LEDMODE_STD .EQU 1
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LEDMODE_SC .EQU 2
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LEDMODE_RTC .EQU 3
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LEDMODE_NABU .EQU 4
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;
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; DSKY MODE SELECTIONS
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;
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DSKYMODE_NONE .EQU 0
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DSKYMODE_V1 .EQU 1
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DSKYMODE_NG .EQU 2
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DSKYMODE_GM7303 .EQU 3
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;
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; DSKY MESSAGE IDS
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;
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DSKY_MSG_LDR_SEL .EQU 0
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DSKY_MSG_LDR_BOOT .EQU 1
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DSKY_MSG_LDR_LOAD .EQU 2
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DSKY_MSG_LDR_GO .EQU 3
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DSKY_MSG_MON_RDY .EQU 4
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DSKY_MSG_MON_BOOT .EQU 5
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;
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; DSKY EVENT IDS
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;
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DSKY_EVT_CPUSPD .EQU 0
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DSKY_EVT_DSKACT .EQU 1
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;
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; FD MODE SELECTIONS
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;
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FDMODE_NONE .EQU 0
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FDMODE_DIO .EQU 1 ; DISKIO V1
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FDMODE_ZETA .EQU 2 ; ZETA
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FDMODE_ZETA2 .EQU 3 ; ZETA V2
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FDMODE_DIDE .EQU 4 ; DUAL IDE
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FDMODE_N8 .EQU 5 ; N8
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FDMODE_DIO3 .EQU 6 ; DISKIO V3
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FDMODE_RCSMC .EQU 7 ; RCBUS SMC 9266 @ $40 (SCOTT BAKER)
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FDMODE_RCWDC .EQU 8 ; RCBUS WDC 37C65 @ $40 (SCOTT BAKER)
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FDMODE_DYNO .EQU 9 ; DYNO WDC 37C65 @ $84
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FDMODE_EPFDC .EQU 10 ; RCBUS ETCHED PIXELS FDC
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FDMODE_MBC .EQU 11 ; NHYODYNE (MBC) FDC
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FDMODE_DUO .EQU 12 ; DUODUYNE (DUO) FDC
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;
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; IDE MODE SELECTIONS
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;
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IDEMODE_NONE .EQU 0
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IDEMODE_DIO .EQU 1 ; DISKIO V1
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IDEMODE_DIDE .EQU 2 ; DUAL IDE
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IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT ONLY)
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IDEMODE_RC .EQU 4 ; RCBUS CF MODULE (8 BIT ONLY)
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IDEMODE_GIDE .EQU 5 ; GENESIS MODULES STD BUS IDE CONTROLLER
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;
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; PPIDE MODE SELECTIONS
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;
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PPIDEMODE_NONE .EQU 0
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PPIDEMODE_STD .EQU 1 ; STANDARD
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PPIDEMODE_S100A .EQU 2 ; S100 PRIMARY INTERFACE
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PPIDEMODE_S100B .EQU 3 ; S100 SECONDARY INTERFACE
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PPIDEMODE_MSX .EQU 4 ; MSX BEER IDE INTERFACE
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;
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; SD MODE SELECTIONS
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;
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SDMODE_NONE .EQU 0
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SDMODE_JUHA .EQU 1 ; JUHA MINI BOARD
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SDMODE_N8 .EQU 2 ; N8-2511, UNMODIFIED
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SDMODE_CSIO .EQU 3 ; N8-2312 OR N8-2511 MODIFIED
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SDMODE_PPI .EQU 4 ; PPISD MINI BOARD
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SDMODE_UART .EQU 5 ; SD INTERFACE VIA UART
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SDMODE_DSD .EQU 6 ; DUAL SD
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SDMODE_MK4 .EQU 7 ; MARK IV
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SDMODE_SC .EQU 8 ; SC (Steve Cousins)
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SDMODE_MT .EQU 9 ; MT (Shift register SPI WIZNET for RCBUS)
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SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE)
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SDMODE_PIO .EQU 11 ; Z80 PIO bitbang
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SDMODE_Z80R .EQU 12 ; Z80 Retro
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SDMODE_EPITX .EQU 13 ; Mini ITX Z180
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SDMODE_T35 .EQU 14 ; S100 TRION T35 FPGA Z80
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SDMODE_GM .EQU 15 ; Genesis SD Driver
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SDMODE_EZ512 .EQU 16 ; EZ512 SD
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SDMODE_K80W .EQU 17 ; K80W SD
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;
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; AY SOUND CHIP MODE SELECTIONS
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;
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AYMODE_NONE .EQU 0
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AYMODE_N8 .EQU 1 ; N8 BUILT-IN SOUND
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AYMODE_SCG .EQU 2 ; SCG ECB BOARD
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AYMODE_RCZ80 .EQU 3 ; RCBUS SOUND MODULE BY ED BRINDLEY ON Z80
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AYMODE_RCZ180 .EQU 4 ; RCBUS SOUND MODULE BY ED BRINDLEY ON Z180
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AYMODE_MSX .EQU 5 ; RCBUS SOUND MODULE REV6 BY ED BRINDLEY ON Z80/Z180 AT MSX PORTS
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AYMODE_LINC .EQU 6 ; LINC Z50 AY SOUND CARD
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AYMODE_MBC .EQU 7 ; MBC SOUND BOARD
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AYMODE_DUO .EQU 8 ; MBC SOUND BOARD
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AYMODE_NABU .EQU 9 ; NABU BUILT-IN SOUND
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;
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; SN SOUND CHIP MODE SELECTIONS
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;
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SNMODE_NONE .EQU 0
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SNMODE_RC .EQU 1 ; RCBUS SOUND MODULE
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SNMODE_VGM .EQU 2 ; VGM ECB BOARD
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SNMODE_DUO .EQU 3 ; DUODYNE MEDIA-IO BOARD
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;
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; SN SOUND MODULE CHANNEL SELECTION
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;
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SNCHAN_BOTH .EQU 0 ; BOTH LEFT & RIGHT CHANNELS GET SAME OUTPUT
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SNCHAN_LEFT .EQU 1 ; LEFT CHANNEL ONLY
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SNCHAN_RIGHT .EQU 2 ; RIGHT CHANNEL ONLY
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;
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; TMS VIDEO MODE SELECTIONS
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;
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TMSMODE_NONE .EQU 0
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TMSMODE_SCG .EQU 1 ; SCG ECB BOARD
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TMSMODE_N8 .EQU 2 ; N8 BUILT-IN VIDEO
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TMSMODE_MSX .EQU 3 ; STD MSX PORTS
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TMSMODE_MSXKBD .EQU 4 ; STD MSX PORTS + PS2 KEYBOARD
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TMSMODE_MSXMKY .EQU 5 ; STD MSX PORTS + MSX KEYBAORD
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TMSMODE_MBC .EQU 6 ; MBC V9938/58 VIDEO BOARD
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TMSMODE_COLECO .EQU 7 ; COLECOVISION PORT MAPPING
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TMSMODE_DUO .EQU 8 ; DUODYNE PORT MAPPING
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TMSMODE_NABU .EQU 9 ; NABU
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TMSMODE_MSXUKY .EQU 10 ; STD MSX PORTS + USB KEYBOARD
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;
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; CVDU VIDEO MODE SELECTIONS
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;
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CVDUMODE_NONE .EQU 0
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CVDUMODE_ECB .EQU 1 ; SCG ECB BOARD
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CVDUMODE_MBC .EQU 2 ; MBC VDC BOARD
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;
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; CVDU MONITOR SELECTIONS
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;
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CVDUMON_NONE .EQU 0
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CVDUMON_CGA .EQU 1 ; CGA MONITOR TIMING (16.000 MHZ OSC)
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CVDUMON_EGA .EQU 2 ; EGA MONITOR TIMING (16.257 MHZ OSC)
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;
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; GDC VIDEO MODE SELECTIONS
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;
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GDCMODE_NONE .EQU 0
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GDCMODE_ECB .EQU 1 ; ECB GDC
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GDCMODE_RPH .EQU 2 ; RPH GDC
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;
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; LPT DRIVER MODE SELECTIONS
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;
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LPTMODE_NONE .EQU 0 ; NONE
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LPTMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP)
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LPTMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE
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LPTMODE_T35 .EQU 3 ; S100 Z80 TRION T35 FPGA BUILT-IN PRINTER PORT
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;
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; PPA DRIVER MODE SELECTIONS
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;
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PPAMODE_NONE .EQU 0 ; NONE
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PPAMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP)
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PPAMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE
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;
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; IMM DRIVER MODE SELECTIONS
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;
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IMMMODE_NONE .EQU 0 ; NONE
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IMMMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP)
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IMMMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE
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;
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; SYQ DRIVER MODE SELECTIONS
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;
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SYQMODE_NONE .EQU 0 ; NONE
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SYQMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP)
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SYQMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE
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;
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; PCF CLOCK CHIP FREQUENCIES
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;
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PCFCLK_3 .EQU $00 ; 3 MHz
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PCFCLK_443 .EQU $10 ; 4.43 MHz
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PCFCLK_6 .EQU $14 ; 6 MHz
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PCFCLK_8 .EQU $18 ; 8 MHz
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PCFCLK_12 .EQU $1C ; 12 MHz
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;
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; PCF TRANSMISSION FREQUENCIES
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;
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PCFTRNS_90 .EQU $00 ; 90 KHZ
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PCFTRNS_45 .EQU $01 ; 45 KHZ
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PCFTRNS_11 .EQU $02 ; 11 KHZ
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PCFTRNS_15 .EQU $03 ; 1.5 KHZ
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;
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; GDC MONITOR SELECTIONS
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;
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GDCMON_NONE .EQU 0
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GDCMON_CGA .EQU 1 ; CGA MONITOR TIMING (16.000 MHZ OSC)
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GDCMON_EGA .EQU 2 ; EGA MONITOR TIMING (16.257 MHZ OSC)
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;
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; DMA MODE SELECTIONS
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;
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DMAMODE_NONE .EQU 0
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DMAMODE_ECB .EQU 1 ; ECB-DMA WOLFGANG KABATZKE'S Z80 DMA ECB BOARD
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DMAMODE_Z180 .EQU 2 ; Z180 INTEGRATED DMA
|
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DMAMODE_Z280 .EQU 3 ; Z280 INTEGRATED DMA
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DMAMODE_RC .EQU 4 ; RCBUS Z80 DMA
|
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DMAMODE_MBC .EQU 5 ; MBC
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DMAMODE_DUO .EQU 6 ; DUO
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DMAMODE_VDG .EQU 7 ; VELESOFT DATAGEAR
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;
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; KEYBOARD MODE SELECTIONS
|
|
;
|
|
KBDMODE_NONE .EQU 0
|
|
KBDMODE_PS2 .EQU 1 ; PS/2 KEYBOARD CONTROLLER
|
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KBDMODE_VRC .EQU 2 ; VGARC KEYBOARD CONTROLLER
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KBDMODE_T35 .EQU 3 ; S100 T35 FPGA KEYBOARD CONTROLLER
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;
|
|
; SERIAL DEVICE CONFIGURATION CONSTANTS
|
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;
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|
SER_DATA5 .EQU 0 << 0
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SER_DATA6 .EQU 1 << 0
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SER_DATA7 .EQU 2 << 0
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SER_DATA8 .EQU 3 << 0
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;
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SER_PARNONE .EQU 0 << 3
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SER_PARODD .EQU 1 << 3
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SER_PAREVEN .EQU 3 << 3
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SER_PARMARK .EQU 5 << 3
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SER_PARSPACE .EQU 7 << 3
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;
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SER_STOP1 .EQU 0 << 2
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SER_STOP2 .EQU 1 << 2
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;
|
|
; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y
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|
; AND STORED AS 5 BITS: YXXXX
|
|
;
|
|
SER_BAUD75 .EQU $00 << 8
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SER_BAUD150 .EQU $01 << 8
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SER_BAUD300 .EQU $02 << 8
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SER_BAUD600 .EQU $03 << 8
|
|
SER_BAUD1200 .EQU $04 << 8
|
|
SER_BAUD2400 .EQU $05 << 8
|
|
SER_BAUD4800 .EQU $06 << 8
|
|
SER_BAUD9600 .EQU $07 << 8
|
|
SER_BAUD19200 .EQU $08 << 8
|
|
SER_BAUD38400 .EQU $09 << 8
|
|
SER_BAUD76800 .EQU $0A << 8
|
|
SER_BAUD153600 .EQU $0B << 8
|
|
SER_BAUD307200 .EQU $0C << 8
|
|
SER_BAUD614400 .EQU $0D << 8
|
|
SER_BAUD1228800 .EQU $0E << 8
|
|
SER_BAUD2457600 .EQU $0F << 8
|
|
SER_BAUD225 .EQU $10 << 8
|
|
SER_BAUD450 .EQU $11 << 8
|
|
SER_BAUD900 .EQU $12 << 8
|
|
SER_BAUD1800 .EQU $13 << 8
|
|
SER_BAUD3600 .EQU $14 << 8
|
|
SER_BAUD7200 .EQU $15 << 8
|
|
SER_BAUD14400 .EQU $16 << 8
|
|
SER_BAUD28800 .EQU $17 << 8
|
|
SER_BAUD57600 .EQU $18 << 8
|
|
SER_BAUD115200 .EQU $19 << 8
|
|
SER_BAUD230400 .EQU $1A << 8
|
|
SER_BAUD460800 .EQU $1B << 8
|
|
SER_BAUD921600 .EQU $1C << 8
|
|
SER_BAUD1843200 .EQU $1D << 8
|
|
SER_BAUD3686400 .EQU $1E << 8
|
|
SER_BAUD7372800 .EQU $1F << 8
|
|
;
|
|
; UART DIVIDER VALUES
|
|
; STORED AS 5 BITS: YXXXX
|
|
;
|
|
DIV_1 .EQU $00
|
|
DIV_2 .EQU $01
|
|
DIV_4 .EQU $02
|
|
DIV_8 .EQU $03
|
|
DIV_16 .EQU $04
|
|
DIV_32 .EQU $05
|
|
DIV_64 .EQU $06
|
|
DIV_128 .EQU $07
|
|
DIV_256 .EQU $08
|
|
DIV_512 .EQU $09
|
|
DIV_1024 .EQU $0A
|
|
DIV_2048 .EQU $0B
|
|
DIV_4096 .EQU $0C
|
|
DIV_8192 .EQU $0D
|
|
DIV_16384 .EQU $0E
|
|
DIV_32768 .EQU $0F
|
|
DIV_3 .EQU $10
|
|
DIV_6 .EQU $11
|
|
DIV_12 .EQU $12
|
|
DIV_24 .EQU $13
|
|
DIV_48 .EQU $14
|
|
DIV_96 .EQU $15
|
|
DIV_192 .EQU $16
|
|
DIV_384 .EQU $17
|
|
DIV_768 .EQU $18
|
|
DIV_1536 .EQU $19
|
|
DIV_3072 .EQU $1A
|
|
DIV_6144 .EQU $1B
|
|
DIV_12288 .EQU $1C
|
|
DIV_24576 .EQU $1D
|
|
DIV_49152 .EQU $1E
|
|
DIV_98304 .EQU $1F
|
|
;
|
|
SER_XON .EQU 1 << 6
|
|
SER_DTR .EQU 1 << 7
|
|
SER_RTS .EQU 1 << 13
|
|
;
|
|
SER_75_8N1 .EQU SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_150_8N1 .EQU SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_300_8N1 .EQU SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_600_8N1 .EQU SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_1200_8N1 .EQU SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_2400_8N1 .EQU SER_BAUD2400 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_4800_8N1 .EQU SER_BAUD4800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_9600_8N1 .EQU SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_19200_8N1 .EQU SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_38400_8N1 .EQU SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_76800_8N1 .EQU SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_153600_8N1 .EQU SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_307200_8N1 .EQU SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_614400_8N1 .EQU SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_1228800_8N1 .EQU SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_2457600_8N1 .EQU SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_225_8N1 .EQU SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_450_8N1 .EQU SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_900_8N1 .EQU SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_1800_8N1 .EQU SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_3600_8N1 .EQU SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_7200_8N1 .EQU SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_14400_8N1 .EQU SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_28800_8N1 .EQU SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_57600_8N1 .EQU SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_115200_8N1 .EQU SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_230400_8N1 .EQU SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_460800_8N1 .EQU SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_921600_8N1 .EQU SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_1843200_8N1 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1
|
|
;
|
|
SER_75_8N2 .EQU SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_150_8N2 .EQU SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_300_8N2 .EQU SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_600_8N2 .EQU SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_1200_8N2 .EQU SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_2400_8N2 .EQU SER_BAUD2400 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_4800_8N2 .EQU SER_BAUD4800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_9600_8N2 .EQU SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_19200_8N2 .EQU SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_38400_8N2 .EQU SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_76800_8N2 .EQU SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_153600_8N2 .EQU SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_307200_8N2 .EQU SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_614400_8N2 .EQU SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_1228800_8N2 .EQU SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_2457600_8N2 .EQU SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_225_8N2 .EQU SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_450_8N2 .EQU SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_900_8N2 .EQU SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_1800_8N2 .EQU SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_3600_8N2 .EQU SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_7200_8N2 .EQU SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_14400_8N2 .EQU SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_28800_8N2 .EQU SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_57600_8N2 .EQU SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_115200_8N2 .EQU SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_230400_8N2 .EQU SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_460800_8N2 .EQU SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_921600_8N2 .EQU SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_1843200_8N2 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_3686400_8N2 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
SER_7372800_8N2 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP2
|
|
;
|
|
; TERMENABLE CONTROLS INCLUSION OF TERMINAL PSEUDO-DEVICE DRIVER
|
|
; IT IS SET TO TRUE BY THE INCLUSION OF ANY VDA DRIVER.
|
|
;
|
|
TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL AUTO-ENABLE IF A VDA IS ENABLED
|
|
;
|
|
; THE FOLLOWING CONTROL INCLUSION OF THE KEYBOARD DRIVERS. THEY ARE
|
|
; SET TO TRUE IN THE VDA DRIVERS AS NEEDED.
|
|
;
|
|
KBDENABLE .EQU FALSE ; PS/2 KEYBOARD DRIVER
|
|
PPKENABLE .EQU FALSE ; PPK KEYBOARD DRIVER
|
|
MKYENABLE .EQU FALSE ; MSX KEYBOARD DRIVER
|
|
NABUKBENABLE .EQU FALSE ; NABU KEYBOARD DRIVER
|
|
USBKYBENABLE .EQU FALSE ; USB KEYBOARD DRIVER
|
|
;
|
|
; VIDEO MODES
|
|
;
|
|
V80X24 .EQU 0 ; ECB-VDU
|
|
V80X25 .EQU 1 ; ECB-VDU, ECB-VGA3, EF9345
|
|
V80X30 .EQU 2 ; ECB-VDU, ECB-VGA3
|
|
V80X25B .EQU 3 ; ECB-VDU
|
|
V80X24B .EQU 4 ; ECB-VDU
|
|
V80X43 .EQU 5 ; ECB-VGA3
|
|
V80X60 .EQU 6 ; ECB-VGA3
|
|
V40X24 .EQU 7 ; EF9345
|
|
;
|
|
; FONT IDS
|
|
;
|
|
FONTID_6X8 .EQU 1
|
|
FONTID_8X8 .EQU 2
|
|
FONTID_8X11 .EQU 3
|
|
FONTID_8X16 .EQU 4
|
|
;
|
|
; KEYBOARD LAYOUTS
|
|
;
|
|
KBD_US .EQU 0 ; US ENGLISH
|
|
KBD_DE .EQU 1 ; GERMAN
|
|
;
|
|
; EMULATION TYPES
|
|
;
|
|
EMUTYP_NONE .EQU 0 ; NONE
|
|
EMUTYP_TTY .EQU 1 ; TTY
|
|
EMUTYP_ANSI .EQU 2 ; ANSI
|
|
;
|
|
; WATCHDOG TYPES
|
|
;
|
|
WDOG_NONE .EQU 0 ; NONE
|
|
WDOG_EZZ80 .EQU 1 ; EASY Z80 WATCHDOG
|
|
WDOG_SKZ .EQU 2 ; SK Z80 CPU W/ 512K
|
|
;
|
|
; SYSTEM SPEED CAPABILITIES
|
|
;
|
|
SPD_FIXED .EQU 0 ; PLATFORM SPEED FIXED AND CANNOT CHANGE SPEEDS
|
|
SPD_HILO .EQU 1 ; PLATFORM CAN CHANGE BETWEEN TWO SPEEDS
|
|
;
|
|
; SYSTEM SPEED CHARACTERISTICS
|
|
;
|
|
SPD_UNSUP .EQU 0 ; PLATFORM CAN CHANGE SPEEDS BUT IS UNSUPPORTED
|
|
SPD_HIGH .EQU 1 ; PLATFORM CAN CHANGE SPEED, STARTS HIGH
|
|
SPD_LOW .EQU 2 ; PLATFORM CAN CHANGE SPEED, STARTS LOW
|
|
;
|
|
; SCSI COMMAND CODES (SHOULD BE IT IT'S OWN FILE)
|
|
;
|
|
SCSI_CMD_TSTRDY .EQU $00
|
|
SCSI_CMD_SENSE .EQU $03
|
|
SCSI_CMD_READ .EQU $08
|
|
SCSI_CMD_WRITE .EQU $0A
|
|
SCSI_CMD_INQ .EQU $12
|
|
SCSI_CMD_START .EQU $1B
|
|
SCSI_CMD_RDCAP .EQU $25
|
|
SCSI_CMD_READ10 .EQU $28
|
|
SCSI_CMD_WRITE10 .EQU $2A
|
|
;
|
|
; EZ80 BUS MODES
|
|
;
|
|
EZ80WSMD_CALC .EQU 0
|
|
EZ80WSMD_CYCLES .EQU 1
|
|
EZ80WSMD_WAIT .EQU 2
|
|
;
|
|
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
|
|
;
|
|
; INCLUDE Z180 REGISTER DEFINITIONS
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
#IF (CPUFAM == CPU_Z180)
|
|
#INCLUDE "z180.inc"
|
|
#ENDIF
|
|
#IF (CPUFAM == CPU_Z280)
|
|
#INCLUDE "z280.inc"
|
|
#ENDIF
|
|
#IF (EIPCENABLE)
|
|
#INCLUDE "eipc.inc"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
; SETUP DEFAULT CPU SPEED VALUES
|
|
;
|
|
CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
#IF (CPUFAM == CPU_Z180)
|
|
#IF (Z180_CLKDIV == 0)
|
|
CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
|
|
#ENDIF
|
|
#IF (Z180_CLKDIV == 2)
|
|
CPUKHZ .SET CPUKHZ * 2 ; ADJUST FOR DOUBLE SPEED OPERATION
|
|
#ENDIF
|
|
#ENDIF
|
|
#IF (CPUFAM == CPU_Z280)
|
|
CPUKHZ .SET CPUKHZ / 2 ; Z180 PHI IS ALWAYS 1/2 OSC
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ
|
|
;
|
|
SYSECHO "CPU SPEED: "
|
|
SYSECHO CPUKHZ
|
|
SYSECHO " KHZ\n"
|
|
;
|
|
; DISPLAY INTERRUPT MODE
|
|
;
|
|
SYSECHO "INTERRUPTS: "
|
|
#IF (INTMODE == 0)
|
|
SYSECHO "NONE"
|
|
#ENDIF
|
|
#IF (INTMODE == 1)
|
|
SYSECHO "MODE 1"
|
|
#ENDIF
|
|
#IF (INTMODE == 2)
|
|
SYSECHO "MODE 2"
|
|
#ENDIF
|
|
#IF (INTMODE == 3)
|
|
SYSECHO "MODE 3"
|
|
#ENDIF
|
|
SYSECHO "\n"
|
|
;
|
|
; SYSTEM PERIODIC TIMER MODE
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
;
|
|
TM_NONE .EQU 0
|
|
TM_CTC .EQU 1
|
|
TM_TMS .EQU 2
|
|
TM_SIMH .EQU 3
|
|
TM_Z180 .EQU 4
|
|
TM_Z280 .EQU 5
|
|
TM_EZ80 .EQU 6
|
|
;
|
|
SYSECHO "SYSTEM TIMER:"
|
|
SYSTIM .EQU TM_NONE
|
|
;
|
|
#IF (CTCENABLE & (INTMODE == 2))
|
|
#IF (CTCTIMER)
|
|
SYSTIM .SET TM_CTC
|
|
SYSECHO " CTC"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF (TMSENABLE & (INTMODE > 0))
|
|
#IF (TMSTIMENABLE)
|
|
SYSTIM .SET TM_TMS
|
|
SYSECHO " TMS"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF ((PLATFORM == PLT_SBC) & (INTMODE == 1))
|
|
#IF (HTIMENABLE)
|
|
SYSTIM .SET TM_SIMH
|
|
SYSECHO " SIMH"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF ((CPUFAM == CPU_Z180) & (INTMODE == 2))
|
|
#IF (Z180_TIMER)
|
|
SYSTIM .SET TM_Z180
|
|
SYSECHO " Z180"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF ((CPUFAM == CPU_Z280) & (MEMMGR == MM_Z280))
|
|
#IF (Z280_TIMER)
|
|
SYSTIM .SET TM_Z280
|
|
SYSECHO " Z280"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF (CPUFAM == CPU_EZ80)
|
|
#IF (EZ80TIMER == EZ80TMR_INT)
|
|
SYSTIM .SET TM_EZ80
|
|
SYSECHO " EZ80"
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF SYSTIM == TM_NONE
|
|
SYSECHO " NONE"
|
|
#ENDIF
|
|
;
|
|
SYSECHO "\n"
|
|
;
|
|
#ENDIF
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
DSCVAL .EQU DEFSERCFG
|
|
SYSECHO "DEFAULT SERIAL CONFIGURATION: "
|
|
#IF ((DSCVAL & %1111100000000) == SER_BAUD9600
|
|
SYSECHO "9600"
|
|
#ENDIF
|
|
#IF ((DSCVAL & %1111100000000) == SER_BAUD38400
|
|
SYSECHO "38400"
|
|
#ENDIF
|
|
#IF ((DSCVAL & %1111100000000) == SER_BAUD57600
|
|
SYSECHO "57600"
|
|
#ENDIF
|
|
#IF ((DSCVAL & %1111100000000) == SER_BAUD115200
|
|
SYSECHO "115200"
|
|
#ENDIF
|
|
SYSECHO " BAUD\n"
|
|
#ENDIF
|
|
;
|
|
;
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
SYSECHO "MEMORY MANAGER: "
|
|
#IF (MEMMGR == MM_SBC)
|
|
SYSECHO "N8VEM (SBC)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_Z2)
|
|
SYSECHO "ZETA 2 (Z2)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_N8)
|
|
SYSECHO "N8 ONBOARD (N8)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_Z180)
|
|
SYSECHO "Z180 NATIVE (Z180)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_Z280)
|
|
SYSECHO "Z280 NATIVE (Z280)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_ZRC)
|
|
SYSECHO "ZRC ONBOARD (ZRC)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_MBC)
|
|
SYSECHO "NHYODYNE (MBC)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_RPH)
|
|
SYSECHO "RHYOPHYRE ONBOARD (RPH)"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_MON)
|
|
SYSECHO "MONSPUTER ONBOARD (MON)" ; DEPRECATED
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_EZ512)
|
|
SYSECHO "EAZY80-512 ONBOARD"
|
|
#ENDIF
|
|
#IF (MEMMGR == MM_SZ80)
|
|
SYSECHO "S100 Z80"
|
|
#ENDIF
|
|
SYSECHO "\n"
|
|
#ENDIF
|
|
;
|
|
SYSECHO "ROM SIZE: "
|
|
SYSECHO ROMSIZE
|
|
SYSECHO " KB\n"
|
|
;
|
|
SYSECHO "RAM SIZE: "
|
|
SYSECHO RAMSIZE
|
|
SYSECHO " KB\n"
|
|
;
|
|
; MEMORY BANK CONFIGURATION
|
|
;
|
|
ROMBANKS .EQU (ROMSIZE / 32) ; TOTAL ROM BANKS
|
|
RAMBANKS .EQU (RAMSIZE / 32) ; TOTAL RAM BANKS
|
|
;
|
|
#IF (BIOS == BIOS_UNA)
|
|
BID_ROM0 .EQU $0000
|
|
BID_RAM0 .EQU $8000
|
|
#ENDIF
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
BID_ROM0 .EQU $00
|
|
BID_RAM0 .EQU $80
|
|
#ENDIF
|
|
;
|
|
BID_ROMN .EQU (BID_ROM0 + ROMBANKS - 1)
|
|
BID_RAMN .EQU (BID_RAM0 + RAMBANKS - 1)
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
;
|
|
#IF (ROMSIZE > 0)
|
|
ROM_BNKS_RSVD .EQU 4
|
|
RAM_BNKS_RSVD .EQU 5
|
|
#ELSE
|
|
ROM_BNKS_RSVD .EQU 0
|
|
RAM_BNKS_RSVD .EQU 8
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
#IF (BIOS == BIOS_UNA)
|
|
ROM_BNKS_RSVD .EQU 4
|
|
RAM_BNKS_RSVD .EQU 4 ; NEED TO CONFIRM THIS!!!
|
|
#ENDIF
|
|
;
|
|
; APPLICATION MEMORY BANKS
|
|
;
|
|
#IF (APP_BNKS == $FF)
|
|
APP_BNKS .SET 0 ; 0K
|
|
#IF ((RAMBANKS - RAM_BNKS_RSVD) > $08)
|
|
APP_BNKS .SET 3 ; 96K
|
|
#ENDIF
|
|
#IF ((RAMBANKS - RAM_BNKS_RSVD) > $18)
|
|
APP_BNKS .SET 11 ; 353KB
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
; ROM/RAM MEMORY BANKS
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
;
|
|
ROMD_BNKS .EQU ROMBANKS - ROM_BNKS_RSVD
|
|
RAMD_BNKS .EQU RAMBANKS - APP_BNKS - RAM_BNKS_RSVD
|
|
;
|
|
#ENDIF
|
|
;
|
|
#IF (BIOS == BIOS_UNA)
|
|
;
|
|
ROMD_BNKS .EQU ROMBANKS - 4
|
|
RAMD_BNKS .EQU RAMBANKS - 4
|
|
;
|
|
#ENDIF
|
|
;
|
|
; ADJUSTMENTS FOR ROMLESS SYSTEMS
|
|
;
|
|
#IF (ROMSIZE == 0)
|
|
;
|
|
; WE NEED TO NORMALIZE THE SIZE OF THE RAM DISK TO FIT
|
|
; ONE OF THE STANDARD ROM DISK IMAGES
|
|
;
|
|
#IF (RAMD_BNKS < 4)
|
|
RAMD_BNKS .SET 0 ; 0KB RAM DISK
|
|
#ENDIF
|
|
#IF ((RAMD_BNKS >= 4) & (RAMD_BNKS < 8))
|
|
RAMD_BNKS .SET 4 ; 128KB RAM DISK
|
|
#ENDIF
|
|
#IF ((RAMD_BNKS >= 8) & (RAMD_BNKS < 12))
|
|
RAMD_BNKS .SET 8 ; 256KB RAM DISK
|
|
#ENDIF
|
|
#IF ((RAMD_BNKS >= 12) & (RAMD_BNKS < 28))
|
|
RAMD_BNKS .SET 12 ; 384KB RAM DISK
|
|
#ENDIF
|
|
#IF (RAMD_BNKS >= 28)
|
|
RAMD_BNKS .SET 28 ; 896KB RAM DISK
|
|
#ENDIF
|
|
;
|
|
#ENDIF
|
|
;
|
|
#IF ((!MDRAM) | (RAMD_BNKS <= 0))
|
|
RAMD_BNKS .SET 0
|
|
#ENDIF
|
|
;
|
|
#IF ((!MDROM) | (ROMD_BNKS <= 0))
|
|
ROMD_BNKS .SET 0
|
|
#ENDIF
|
|
;
|
|
#IF (ROMSIZE > 0)
|
|
;
|
|
; NORMAL SYSTEM WITH ROM & RAM
|
|
; -- TYPICAL --
|
|
BID_BOOT .EQU BID_ROM0 + 0 ; BOOT BANK 0x00
|
|
BID_IMG0 .EQU BID_ROM0 + 1 ; ROM LOADER AND FIRST IMAGES BANK 0x01
|
|
BID_IMG1 .EQU BID_ROM0 + 2 ; ROM APPS IMAGES BANK 0x02
|
|
BID_IMG2 .EQU BID_ROM0 + 3 ; ROM UTILITIES IMAGES BANK 0x03
|
|
BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK 0x04
|
|
BID_BIOS .EQU BID_RAM0 + 0 ; HBIOS BANK 0x80
|
|
BID_RAMD0 .EQU BID_RAM0 + 1 ; FIRST RAM DRIVE BANK 0x81
|
|
BID_APP0 .EQU BID_RAMD0 + RAMD_BNKS ; FIRST APP BANK 0x89
|
|
BID_BUF .EQU BID_RAMN - 3 ; OS BUFFERS (CP/M3) 0x8C
|
|
BID_AUX .EQU BID_RAMN - 2 ; AUX BANK (CP/M 3, BPBIOS, ETC.) 0x8D
|
|
BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.) 0x8E
|
|
BID_COM .EQU BID_RAMN - 0 ; COMMON BANK, UPPER 32K 0x8F
|
|
;
|
|
#ELSE
|
|
;
|
|
; SPECIAL CONFIGURATION FOR A ROMLESS SYSTEM
|
|
; RAM IS POPULATED PRIOR TO ROMWBW STARTUP
|
|
; -- TYPICAL --
|
|
BID_BOOT .EQU BID_RAM0 + 0 ; BOOT BANK 0x80
|
|
BID_IMG0 .EQU BID_RAM0 + 1 ; ROM LOADER AND FIRST IMAGES BANK 0x81
|
|
BID_IMG1 .EQU BID_RAM0 + 2 ; ROM APPS IMAGES BANK 0x82
|
|
BID_IMG2 .EQU BID_RAM0 + 3 ; ROM UTILITIES IMAGES BANK 0x83
|
|
BID_RAMD0 .EQU BID_RAM0 + 4 ; FIRST RAM DRIVE BANK 0x84
|
|
BID_APP0 .EQU BID_RAMD0 + RAMD_BNKS ; FIRST APP BANK 0x89
|
|
BID_BUF .EQU BID_RAMN - 3 ; OS BUFFERS (CP/M3) 0x8C
|
|
BID_AUX .EQU BID_RAMN - 2 ; AUX BANK (CP/M 3, BPBIOS, ETC.) 0x8D
|
|
BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.) 0x8E
|
|
BID_COM .EQU BID_RAMN - 0 ; COMMON BANK, UPPER 32K 0x8F
|
|
;
|
|
BID_BIOS .EQU BID_BOOT ; HBIOS BANK 0x80
|
|
BID_ROMD0 .EQU 0 ; NO ROM DRIVE
|
|
;
|
|
#ENDIF
|
|
;
|
|
#IF ((!MDRAM) | (RAMD_BNKS <= 0))
|
|
BID_RAMD0 .SET $FF
|
|
MDRAM .SET FALSE
|
|
#ENDIF
|
|
;
|
|
#IF ((!MDROM) | (ROMD_BNKS <= 0))
|
|
BID_ROMD0 .SET $FF
|
|
MDROM .SET FALSE
|
|
#ENDIF
|
|
;
|
|
APP_BNKS .SET BID_BUF - BID_APP0
|
|
;
|
|
#IF (APP_BNKS <= 0)
|
|
BID_APP0 .SET $FF
|
|
APP_BNKS .SET 0
|
|
#ENDIF
|
|
;
|
|
;;;BID_RAMDN .EQU BID_RAMD0 + RAMD_BNKS - 1 ; LAST RAM DRIVE BANK
|
|
;;;BID_ROMDN .EQU BID_ROMD0 + ROMD_BNKS - 1 ; LAST ROM DRIVE BANK
|
|
;;;BID_APPN .EQU BID_APP0 + APP_BNKS - 1 ; LAST APP BANK
|
|
;
|
|
#IFDEF SYSINFO
|
|
.ECHO "------------- CAPACITY -----------------\n"
|
|
.ECHO "ROMBANKS: " \ .ECHO ROMBANKS \ .ECHO "\n"
|
|
.ECHO "RAMBANKS: " \ .ECHO RAMBANKS \ .ECHO "\n"
|
|
.ECHO "ROMD_BNKS: " \ .ECHO ROMD_BNKS \ .ECHO "\n"
|
|
.ECHO "RAMD_BNKS: " \ .ECHO RAMD_BNKS \ .ECHO "\n"
|
|
.ECHO "APP_BNKS: " \ .ECHO APP_BNKS \ .ECHO "\n"
|
|
.ECHO "----------- MEMORY LAYOUT --------------\n"
|
|
.ECHO "BID_ROM0: " \ .ECHO BID_ROM0 \ .ECHO "\n"
|
|
.ECHO "BID_ROMN: " \ .ECHO BID_ROMN \ .ECHO "\n"
|
|
.ECHO "BID_RAM0: " \ .ECHO BID_RAM0 \ .ECHO "\n"
|
|
.ECHO "BID_RAMN: " \ .ECHO BID_RAMN \ .ECHO "\n"
|
|
.ECHO "------------- BANK LAYOUT --------------\n"
|
|
.ECHO "BID_BOOT: " \ .ECHO BID_BOOT \ .ECHO "\n"
|
|
.ECHO "BID_IMG0: " \ .ECHO BID_IMG0 \ .ECHO "\n"
|
|
.ECHO "BID_IMG1: " \ .ECHO BID_IMG1 \ .ECHO "\n"
|
|
.ECHO "BID_IMG2: " \ .ECHO BID_IMG2 \ .ECHO "\n"
|
|
.ECHO "BID_ROMD0: " \ .ECHO BID_ROMD0 \ .ECHO "\n"
|
|
;;; .ECHO "BID_ROMDN: " \ .ECHO BID_ROMDN \ .ECHO "\n"
|
|
.ECHO "BID_BIOS: " \ .ECHO BID_BIOS \ .ECHO "\n"
|
|
.ECHO "BID_RAMD0: " \ .ECHO BID_RAMD0 \ .ECHO "\n"
|
|
;;; .ECHO "BID_RAMDN: " \ .ECHO BID_RAMDN \ .ECHO "\n"
|
|
.ECHO "BID_APP0: " \ .ECHO BID_APP0 \ .ECHO "\n"
|
|
;;; .ECHO "BID_APPN: " \ .ECHO BID_APPN \ .ECHO "\n"
|
|
.ECHO "BID_BUF: " \ .ECHO BID_BUF \ .ECHO "\n"
|
|
.ECHO "BID_AUX: " \ .ECHO BID_AUX \ .ECHO "\n"
|
|
.ECHO "BID_USR: " \ .ECHO BID_USR \ .ECHO "\n"
|
|
.ECHO "BID_COM: " \ .ECHO BID_COM \ .ECHO "\n"
|
|
.ECHO "----------------------------------------\n"
|
|
#ENDIF
|
|
;
|
|
; ---------------------------
|
|
; Memory and ROM Bank Layouts
|
|
; ---------------------------
|
|
;
|
|
#INCLUDE "layout.inc"
|
|
;
|
|
; ---------------------------
|
|
;
|
|
; INTERRUPT MODE 2 SLOT ASSIGNMENTS
|
|
;
|
|
#IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
|
|
|
|
#IF (PLATFORM == PLT_MBC)
|
|
;
|
|
; MBC Z80 INTERRUPTS
|
|
;
|
|
INT_UART0 .EQU 4 ; UART 0
|
|
INT_UART1 .EQU 5 ; UART 1
|
|
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
|
|
INT_PIO0A .EQU 10 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 11 ; ZILOG PIO 0, CHANNEL B
|
|
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
|
|
INT_CTC0B .EQU 13 ; ZILOG CTC 0, CHANNEL B
|
|
INT_CTC0C .EQU 14 ; ZILOG CTC 0, CHANNEL C
|
|
INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
|
|
#ENDIF
|
|
|
|
#IF (PLATFORM == PLT_DUO)
|
|
;
|
|
; DUO Z80 IM2 INTERRUPTS
|
|
;
|
|
INT_PS2KB .EQU 2 ; KEYBOARD RECEIVE
|
|
INT_UART0 .EQU 4 ; UART 0
|
|
INT_UART1 .EQU 5 ; UART 1
|
|
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
|
|
INT_PIO0A .EQU 10 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 11 ; ZILOG PIO 0, CHANNEL B
|
|
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
|
|
INT_CTC0B .EQU 13 ; ZILOG CTC 0, CHANNEL B
|
|
INT_CTC0C .EQU 14 ; ZILOG CTC 0, CHANNEL C
|
|
INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
|
|
#ENDIF
|
|
|
|
#IF (PLATFORM == PLT_NABU)
|
|
;
|
|
; NABU Z80 IM2 INTERRUPTS
|
|
;
|
|
INT_HCCARCV .EQU 0 ; CABLE ADAPTER RECEIVE
|
|
INT_HCCASND .EQU 1 ; CABLE ADAPTER SEND
|
|
INT_NABUKB .EQU 2 ; KEYBOARD RECEIVE
|
|
INT_VDP .EQU 3 ; VDP VERTICAL RETRACE
|
|
INT_OPTCRD0 .EQU 4 ; OPTION CARD 0
|
|
INT_OPTCRD1 .EQU 5 ; OPTION CARD 1
|
|
INT_OPTCRD2 .EQU 6 ; OPTION CARD 2
|
|
INT_OPTCRD3 .EQU 7 ; OPTION CARD 3
|
|
#ENDIF
|
|
|
|
#IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))
|
|
;
|
|
; GENERIC Z80 M2 INTERRUPTS
|
|
;
|
|
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
|
|
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
|
|
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
|
|
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
|
|
INT_UART0 .EQU 4 ; UART 0
|
|
INT_UART1 .EQU 5 ; UART 1
|
|
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
|
|
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
|
|
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
|
|
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
|
|
#ENDIF
|
|
|
|
#ENDIF
|
|
|
|
#IF ((CPUFAM == CPU_Z180) & (INTMODE > 0))
|
|
;
|
|
; Z180-BASED SYSTEMS
|
|
;
|
|
; NOTE THAT Z180 PROCESSES ALL INTERNAL INTERRUPTS JUST LIKE
|
|
; IM2 EVEN WHEN CHIP IS IN IM1 MODE. SO WE INCLUDE THE IM2
|
|
; INTERRUPT ASSIGNMENTS FOR IM1 BELOW.
|
|
;
|
|
INT_INT1 .EQU 0 ; Z180 INT 1
|
|
INT_INT2 .EQU 1 ; Z180 INT 2
|
|
INT_TIM0 .EQU 2 ; Z180 TIMER 0
|
|
INT_TIM1 .EQU 3 ; Z180 TIMER 1
|
|
INT_DMA0 .EQU 4 ; Z180 DMA 0
|
|
INT_DMA1 .EQU 5 ; Z180 DMA 1
|
|
INT_CSIO .EQU 6 ; Z180 CSIO
|
|
INT_SER0 .EQU 7 ; Z180 SERIAL 0
|
|
INT_SER1 .EQU 8 ; Z180 SERIAL 0
|
|
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
|
|
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
|
|
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
|
|
INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
|
|
#ENDIF
|
|
|
|
#IF ((CPUFAM == CPU_Z280) & (INTMODE >= 2))
|
|
;
|
|
; Z280-BASED SYSTEMS
|
|
;
|
|
; FOR Z280 MODE 3, THESE APPLY TO THE INTA SIGNAL
|
|
; THESE ARE IDENTICAL TO THE GENERIC Z80 ASSIGNMENTS
|
|
;
|
|
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
|
|
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
|
|
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
|
|
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
|
|
INT_UART0 .EQU 4 ; UART 0
|
|
INT_UART1 .EQU 5 ; UART 1
|
|
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
|
|
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
|
|
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
|
|
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
|
|
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
|
|
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
|
|
#ENDIF
|
|
|
|
|
|
#DEFINE IVT(INTX) HB_IVT + (INTX * 4) + 1
|
|
#DEFINE VEC(INTX) INTX * 2
|
|
|
|
;
|
|
; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
|
|
; DIV 1280, 14KHZ @ 18MHZ CLK
|
|
;
|
|
#IF (BIOS == BIOS_WBW)
|
|
#IF (CPUFAM == CPU_Z180)
|
|
Z180_CNTR_DEF .EQU $06 ; DEFAULT VALUE FOR Z180 CSIO CONFIG
|
|
#ENDIF
|
|
#ENDIF
|
|
;
|
|
; HELPER MACROS
|
|
;
|
|
#DEFINE ALIGN(N) .FILL ((($+(N-1)) & ~(N-1)) - $)
|
|
;
|
|
#DEFINE PRTC(C) CALL PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X')
|
|
#DEFINE PRTS(S) CALL PRTSTRD \ .TEXT S ; PRINT STRING S TO CONSOLE - PRTD("HELLO")
|
|
#DEFINE PRTX(X) CALL PRTSTRI \ .DW X ; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
|
|
#DEFINE DEBUG(S) CALL PRTSTRD \ .TEXT S \ .TEXT "$" ; $$$$$$ PRINT STRING S TO CONSOLE - PRTD("HELLO") - NO TRAILING $ REQUIRED
|
|
;
|
|
#DEFINE XIO_PRTC(C) CALL XIO_PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X')
|
|
#DEFINE XIO_PRTS(S) CALL XIO_PRTSTRD \ .DB S ; PRINT STRING S TO CONSOLE - PRTD("HELLO")
|
|
#DEFINE XIO_PRTX(X) CALL XIO_PRTSTRI \ .DW X ; PRINT STRING AT ADDRESS X TO CONSOLE - PRTI(STR_HELLO)
|
|
|