mirror of https://github.com/wwarthen/RomWBW.git
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58 lines
2.5 KiB
58 lines
2.5 KiB
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; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
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;
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MPCL_RAM .EQU $78 ; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
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MPCL_ROM .EQU $7C ; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
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RTC .EQU $70 ; ADDRESS OF RTC LATCH AND INPUT PORT
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;
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; PPI 82C55 I/O IS DECODED TO PORT 60-67
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;
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PPIBASE .EQU $60
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PPIA .EQU PPIBASE + 0 ; PORT A
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PPIB .EQU PPIBASE + 1 ; PORT B
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PPIC .EQU PPIBASE + 2 ; PORT C
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
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;
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; 16C550 SERIAL LINE UART
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;
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SIO_BASE .EQU $68
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SIO_RBR .EQU SIO_BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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SIO_THR .EQU SIO_BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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SIO_IER .EQU SIO_BASE + 1 ; DLAB=0: INT ENABLE REG
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SIO_IIR .EQU SIO_BASE + 2 ; INT IDENT REGISTER (READ ONLY)
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SIO_FCR .EQU SIO_BASE + 2 ; FIFO CONTROL REG (WRITE ONLY)
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SIO_LCR .EQU SIO_BASE + 3 ; LINE CONTROL REG
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SIO_MCR .EQU SIO_BASE + 4 ; MODEM CONTROL REG
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SIO_LSR .EQU SIO_BASE + 5 ; LINE STATUS REG
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SIO_MSR .EQU SIO_BASE + 6 ; MODEM STATUS REG
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SIO_SCR .EQU SIO_BASE + 7 ; SCRATCH REGISTER
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SIO_DLL .EQU SIO_BASE + 0 ; DLAB=1: DIVISOR LATCH (LS)
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SIO_DLM .EQU SIO_BASE + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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; MEMORY BANK CONFIGURATION
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;
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#IFDEF UNALOAD
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BID_BOOT .EQU $00 ; HARDWARE COLD BOOT (SETUP)
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BID_COMIMG .EQU $02 ; LOADER + CP/M IMAGE TO COPY TO BID_COM
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BID_HBIMG .EQU $04 ; HBIOS IMAGE TO COPY TO BID_HB
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BID_ROMD .EQU $05 ; FIRST ROM DRIVE BANK
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BID_ROMDN .EQU ($00 + ((ROMSIZE / 32) - 1)) ; LAST ROM DRIVE BANK
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BID_USR .EQU $80 ; LOW 32K OF TPA
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BID_HB .EQU $81 ; WORKING COPY OF HBIOS IN RAM
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BID_BPB .EQU $82 ; BPBIOS BANK
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BID_RAMD .EQU $83 ; START OF RAM DRIVE
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BID_RAMDN .EQU ($80 + ((RAMSIZE / 32) - 2)) ; LAST RAM DRIVE BANK
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BID_COM .EQU $8F ; COMMON BANK, UPPER 32K
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#ELSE
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BID_BOOT .EQU $00 ; HARDWARE COLD BOOT (SETUP)
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BID_COMIMG .EQU $00 ; LOADER + CP/M IMAGE TO COPY TO BID_COM
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BID_HBIMG .EQU $01 ; HBIOS IMAGE TO COPY TO BID_HB
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BID_ROMD .EQU $02 ; FIRST ROM DRIVE BANK
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BID_ROMDN .EQU ($00 + ((ROMSIZE / 32) - 1)) ; LAST ROM DRIVE BANK
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BID_USR .EQU $80 ; LOW 32K OF TPA
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BID_HB .EQU $81 ; WORKING COPY OF HBIOS IN RAM
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BID_BPB .EQU $82 ; BPBIOS BANK
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BID_RAMD .EQU $83 ; START OF RAM DRIVE
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BID_RAMDN .EQU ($80 + ((RAMSIZE / 32) - 2)) ; LAST RAM DRIVE BANK
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BID_COM .EQU $8F ; COMMON BANK, UPPER 32K
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#ENDIF
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