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373 lines
14 KiB
373 lines
14 KiB
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
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; B/P BIOS Configuration and Equate File. ** System Dependant **
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; - D-X Designs Pty Ltd P112 CPU Board - **********************
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; Tailor your system here.
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;
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; 30 Aug 01 - Cleaned up for GPL release. HFB
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; 11 May 97 - Added GIDE and adjusted HD equates. HFB
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; 5 Jan 97 - Reformatted to Standard. HFB
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; 10 Jun 96 - Initial Test Release. HFB
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;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; BIOS Configuration Equates and Macros
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DATE MACRO
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DEFB '17 Jan 14' ; Date of this version
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ENDM
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AUTOCL MACRO
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DEFB 8,'ZEX Z41 ',0 ; Autostart command line
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ENDM
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;--- Basic System and Z-System Section ---
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MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
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IF MOVCPM
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VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
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ELSE
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VERS EQU 21H ; Version number w/Device Swapping permitted
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ENDIF
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BANKED EQU YES ; Is this a banked BIOS?
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ZSDOS2 EQU YES ; Yes = Banked Dos, No = CP/M 2.2 Compatible
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INROM EQU NO ; Alternate bank in ROM?
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MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
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FASTWB EQU YES ; Yes if restoring CPR from banked RAM
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; ..No if restoring from Drive A
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Z3 EQU YES ; Include ZCPR init code?
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HAVIOP EQU NO ; Include IOP code into Jump table?
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INTPXY EQU YES ; Internal HBIOS Mini Proxy
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CONF_T EQU NO ; Set for Segment Configuration T
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CONF_N EQU YES ; Set for Segment Configuration N
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;--- Memory configuration Section --- (Expansion Memory configured here)
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IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
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; No = Include Common RAM transfer buffer
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;--- Character Device Section ---
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MORDEV EQU NO ; YES = Include any extra Char Device Drivers
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; NO = Only use the 4 defined Char Devices
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ESCC_B EQU no ; Include ESCC Channel B Driver?
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; The following two devices result in non-standard data rates
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; with the standard 16.00 MHz crystal in the P112. If a more
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; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
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; is used, the ports become usable.
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; Driver code for ASCI0 and ASCI1 includes an option for
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; assembling Polled or Interrupt-driven buffered input.
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; Select the desired option for ASCI0 with the BUFFA0 flag,
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; and BUFFA1 for ASCI1.
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ASCI_0 EQU false ; Include ASCI0 Driver?
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BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
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ASCI_1 EQU false ; Include ASCI1 Driver?
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BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
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QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
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; ..must be 2^n with n<8
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RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
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XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
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;--- Clock and Time Section ---
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CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
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DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
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CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
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TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
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;--- Floppy Diskette Section ---
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BIOERM EQU yes ; Print BIOS error messages?
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CALCSK EQU YES ; Calculate skew table?
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AUTOSL EQU YES ; Auto select floppy formats?
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; If AUTOSL=True, the next two are active...
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FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
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FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
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FLOPY8 EQU no ; Include 8" Floppy Formats?
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MORDPB EQU NO ; Include additional Floppy DPB Formats?
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;--- RAM Disk Section ---
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RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
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;--- Hard Disk Section ---
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HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
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; (Pick 1 of 3 options below)
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SCSI EQU NO ; YES = Use SCSI Driver
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IDE EQU NO ; YES = Use IDE Driver
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SIMHDSK EQU NO ; YES = Use SIMH HDSK Driver
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HBDSK EQU YES ; YES = Use HBIOS Disk Driver
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HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
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; (DMA not implemented for GIDE)
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UNIT_0 EQU YES ; Hard Disk Physical Unit 1
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UNIT_1 EQU YES ; Hard Disk Physical Unit 2
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UNIT_2 EQU YES ; Hard Disk Physical Unit 3
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;--- Logical Drive Section ---
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DRV_A EQU no ; Set each of these equates for the drive and
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DRV_B EQU no ; partition complement of your system. Assume
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DRV_C EQU no ; that A-D are Floppies.
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DRV_D EQU no
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DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
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DRV_F EQU yes ; Partitions
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DRV_G EQU yes
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DRV_H EQU yes
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DRV_I EQU yes
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DRV_J EQU yes
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DRV_K EQU yes
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DRV_L EQU yes
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DRV_M EQU RAMDSK ; This is Yes for RAM drive
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DRV_N EQU yes
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DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
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DRV_P EQU no
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;========== Configuration Unique Equates (P112) ===========
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;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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;>>> Do NOT Alter these unless you KNOW what you're doing <<<
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;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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REFRSH EQU NO ; Set to NO for only Static RAM, needed for
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; systems with dynamic RAMs.
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NOWAIT EQU NO ; Set to NO to use configured Wait States in
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; Hard Disk Driver. Yes to eliminate Waits.
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
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; memory in 32k increments. In P112, the ROM occupies the first 32k
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; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
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; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
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BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
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BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
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BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
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BNKU EQU 00H ; User Area Bank 58000H
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; (set to 0 to disable)
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BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
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BNKM EQU BID_RAMM ; Maximum Bank # F8000H
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; With both on-board RAMs only (MEM1 or MEM2),
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; the maximum Bank number is 11 (0BH).
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;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
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CNTLA0 EQU 00H ; Control Port ASCI 0
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CNTLA1 EQU 01H ; Control Port ASCI 1
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STAT0 EQU 04H ; Serial port 0 Status
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STAT1 EQU 05H ; Serial port 1 Status
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TDR0 EQU 06H ; Serial port 0 Output Data
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TDR1 EQU 07H ; Serial port 1 Output Data
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RDR0 EQU 08H ; Serial port 0 Input Data
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RDR1 EQU 09H ; Serial Port 1 Input Data
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CNTR EQU 0AH ; HD64180 Counter port
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TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
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TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
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RLDR0L EQU 0EH ; CTC0 Reload Count, Low
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RLDR0H EQU 0FH ; CTC0 Reload Count, High
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TCR EQU 10H ; Interrupt Control Register
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TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
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TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
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RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
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RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
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FRC EQU 18H ; Free-Running Counter
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CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
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SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
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MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
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DSTAT EQU 30H ; DMA Status/Control port
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DMODE EQU 31H ; DMA Mode Control port
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DCNTL EQU 32H ; DMA/WAIT Control Register
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IL EQU 33H ; Interrupt Segment Register
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ITC EQU 34H ; Interrupt/Trap Control Register
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RCR EQU 36H ; HD64180 Refresh Control register
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CBR EQU 38H ; MMU Common Base Register
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BBR EQU 39H ; MMU Bank Base Register
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CBAR EQU 3AH ; MMU Common/Bank Area Register
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OMCR EQU 3EH ; Operation Mode Control Reg
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ICR EQU 3FH ; I/O Control Register
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; Some bit definitions used with the Z-180 on-chip peripherals:
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TDRE EQU 02H ; ACSI Transmitter Buffer Empty
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RDRF EQU 80H ; ACSI Received Character available
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Extended Features of Z80182 for P112
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WSGCS EQU 0D8H ; Wait-State Generator CS
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ENH182 EQU 0D9H ; Z80182 Enhancements Register
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PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
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RAMUBR EQU 0E6H ; RAM End Boundary
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RAMLBR EQU 0E7H ; RAM Start Boundary
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ROMBR EQU 0E8H ; ROM Boundary
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FIFOCTL EQU 0E9H ; FIFO Control Register
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RTOTC EQU 0EAH ; RX Time-Out Time Constant
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TTOTC EQU 0EBH ; TX Time-Out Time Constant
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FCR EQU 0ECH ; FIFO Register
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SCR EQU 0EFH ; System Pin Control
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RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
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THR EQU 0F0H ; MIMIN TX Holding Register (W)
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IER EQU 0F1H ; Interrupt Enable Register
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LCR EQU 0F3H ; Line Control Register
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MCR EQU 0F4H ; Modem Control Register
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LSR EQU 0F5H ; Line Status Register
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MDMSR EQU 0F6H ; Modem Status Register
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MSCR EQU 0F7H ; MIMIC Scratch Register
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DLATL EQU 0F8H ; Divisor Latch (Low)
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DLATM EQU 0F9H ; Divisor Latch (High)
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TTCR EQU 0FAH ; TX Time Constant
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RTCR EQU 0FBH ; RX Time Constant
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IVEC EQU 0FCH ; MIMIC Interrupt Vector
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MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
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IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
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MMCR EQU 0FFH ; MIMIC Master Control Register
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; Z80182 PIO Registers
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DDRA EQU 0EDH ; Data Direction Register A
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DRA EQU 0EEH ; Port A Data
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DDRB EQU 0E4H ; Data Direction Register B
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DRB EQU 0E5H ; Data B Data
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DDRC EQU 0DDH ; Data Direction Register C
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DRC EQU 0DEH ; Data C Data
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; ESCC Registers on Z80182
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SCCACNT EQU 0E0H ; ESCC Control Channel A
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SCCAD EQU 0E1H ; ESCC Data Channel A
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SCCBCNT EQU 0E2H ; ESCC Control Channel B
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SCCBD EQU 0E3H ; ESCC Data Channel B
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; [E]SCC Internal Register Definitions
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RR0 EQU 00H
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RR1 EQU 01H
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RR2 EQU 02H
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RR3 EQU 03H
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RR6 EQU 06H
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RR7 EQU 07H
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RR10 EQU 0AH
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RR12 EQU 0CH
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RR13 EQU 0DH
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RR15 EQU 0FH
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WR0 EQU 00H
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WR1 EQU 01H
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WR2 EQU 02H
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WR3 EQU 03H
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WR4 EQU 04H
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WR5 EQU 05H
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WR6 EQU 06H
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WR7 EQU 07H
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WR9 EQU 09H
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WR10 EQU 0AH
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WR11 EQU 0BH
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WR12 EQU 0CH
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WR13 EQU 0DH
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WR14 EQU 0EH
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WR15 EQU 0FH
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; FDC37C665/6 Parallel Port in Standard AT Mode
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DPORT EQU 8CH ; Data Port
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SPORT EQU 8DH ; Status Port
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CPORT EQU 8EH ; Control Port
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; FDC37C665/6 Configuration Control (access internal registers)
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CFCNTL EQU 90H ; Configuration control port
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CFDATA EQU 91H ; Configuration data port
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; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
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DCR EQU 92H ; Drive Control Register (Digital Output)
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MSR EQU 94H ; Main Status Register
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DR EQU 95H ; Data/Command Register
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DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
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_DMA EQU 0A0H ; Diskette DMA Address
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; FDC37C665/6 Serial Port (National 16550 compatible)
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_RBR EQU 68H ;R Receiver Buffer
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_THR EQU 68H ;W Transmit Holding Reg
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_IER EQU 69H ;RW Interrupt-Enable Reg
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_IIR EQU 6AH ;R Interrupt Ident. Reg
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_FCR EQU 6AH ;W FIFO Control Reg
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_LCR EQU 6BH ;RW Line Control Reg
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_MCR EQU 6CH ;RW Modem Control Reg
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_LSR EQU 6DH ;RW Line Status Reg
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_MMSR EQU 6EH ;RW Modem Status Reg
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_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
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_DDL EQU 68H ;RW Divisor LSB | wih DLAB
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_DLM EQU 69H ;RW Divisor MSB | set High
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
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IF HARDDSK
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NCR EQU 40H ; Base of NCR 5380
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; 5380 Chip Registers
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NCRDAT EQU NCR ; Current SCSI Data (Read)
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; Output Data Register (Write)
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NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
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NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
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NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
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NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
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NCRST EQU NCR+5 ; Bus & Status Register (Read)
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; Start DMA Send (Write)
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NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
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; Start DMA Initiator Receive (Write)
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DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
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; Bit Assignments for NCR 5380 Ports as indicated
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B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
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B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
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B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
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B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
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B_BSY EQU 01000000B ; *Busy (NCRBUS)
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B_REQ EQU 00100000B ; *Request (NCRBUS)
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B_MSG EQU 00010000B ; *Message (NCRBUS)
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B_CD EQU 00001000B ; *Command/Data (NCRBUS)
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B_IO EQU 00000100B ; *I/O (NCRBUS)
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B_SEL EQU 00000010B ; *Select (NCRBUS)
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B_PHAS EQU 00001000B ; Phase Match (NCRST)
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B_BBSY EQU 00000100B ; Bus Busy (NCRST)
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B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
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B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
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ENDIF ;harddsk
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;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
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; Set the base GIDE equate to the jumper setting on the GIDE board.
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IF IDE
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GIDE EQU 50H ; Set base of 16 byte address range
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IDEDOR EQU GIDE+6 ; Digital Output Register
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IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
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IDEErr EQU GIDE+9 ; IDE Error Register
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IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
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IDESNum EQU GIDE+0BH ; IDE Sector Number Register
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IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
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IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
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IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
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IDECmd EQU GIDE+0FH ; IDE Command/Status Register
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CMDHOM EQU 10H ; Home Drive Heads
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CMDRD EQU 20H ; Read Sector Command (w/retry)
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CMDWR EQU 30H ; Write Sector Command (w/retry)
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CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
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CMDFMT EQU 50H ; Format Track Command
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CMDDIAG EQU 90H ; Execute Diagnostics Command
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CMDINIT EQU 91H ; Initialize Drive Params Command
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CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
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CMDPW3 EQU 0E3H ; High Range of Power Control Commands
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CMDPWQ EQU 0E5H ; Power Status Query Command
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CMDID EQU 0ECH ; Read Drive Ident Data Command
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ENDIF ;ide
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;=================== End Unique Equates =======================
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