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52 lines
1.2 KiB
52 lines
1.2 KiB
/*
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* sbcv2.h - Macros describing the N8VEM SBC V2
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*
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*/
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#define SBCV2
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/* set i/o base to first block of 32 addresses
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possible are 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0
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depending oon setting of dip switches on board
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*/
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#define SBCV2_IO_BASE 0x00
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#define UART_IO_BASE ( SBCV2_IO_BASE + 0x68 )
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__sfr __at (UART_IO_BASE+0) rUART_RBR;
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__sfr __at (UART_IO_BASE+0) wUART_THR;
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__sfr __at (UART_IO_BASE+0) wUART_DIV_LO;
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__sfr __at (UART_IO_BASE+1) wUART_DIV_HI;
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__sfr __at (UART_IO_BASE+1) wUART_IER;
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__sfr __at (UART_IO_BASE+2) rUART_IIR;
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__sfr __at (UART_IO_BASE+3) wUART_LCR;
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__sfr __at (UART_IO_BASE+4) wUART_MCR;
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__sfr __at (UART_IO_BASE+5) rUART_LSR;
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__sfr __at (UART_IO_BASE+6) rUART_MSR;
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__sfr __at (UART_IO_BASE+7) wUART_FCR;
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#define DISKIO_IDE 0x20
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#define DISKIO_FLP 0x30
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#define PPORT 0x60
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#define MPCL 0x70
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__sfr __at (MPCL + 0x08) pMPCL_RAM;
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__sfr __at (MPCL + 0x0c) pMPCL_ROM;
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#define RAMTARG_CPM 0x2000
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#define ROMSTART_CPM 0x0000
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#define CCPSIZ_CPM 0x2000
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#define LOADER_ORG 0x0000
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#define CPM_ORG 0x0A00
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#define MON_ORG 0x3800
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#define ROM_G 0x5000
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#define ROM_F 0x8000
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/*
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#define VDU_DRV 0xF8100
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*/
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