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38 lines
1.3 KiB
38 lines
1.3 KiB
; ~/RomWBW/branches/s100/Source/s100iob.inc 1/17/2013 dwg -
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; S100COMPUTERS.COM Input Output Board Schema
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#DEFINE IC_SCC_8530
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#DEFINE IC_PPI_8255
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;
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;==================================================================
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; WBW: STUFF BELOW IS TEMPORARY TO ALLOW S100 TO BUILD WITHOUT ERROR
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;==================================================================
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;
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; PPI 82C55 I/O IS DECODED TO PORT 60-67
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;
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PPIBASE .EQU 60H
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PPIA .EQU PPIBASE + 0 ; PORT A
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PPIB .EQU PPIBASE + 1 ; PORT B
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PPIC .EQU PPIBASE + 2 ; PORT C
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
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;
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; 16C550 SERIAL LINE UART
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;
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SIO_BASE .EQU 68H
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SIO_RBR .EQU SIO_BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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SIO_THR .EQU SIO_BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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SIO_IER .EQU SIO_BASE + 1 ; DLAB=0: INT ENABLE REG
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SIO_IIR .EQU SIO_BASE + 2 ; INT IDENT REGISTER (READ ONLY)
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SIO_FCR .EQU SIO_BASE + 2 ; FIFO CONTROL REG (WRITE ONLY)
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SIO_LCR .EQU SIO_BASE + 3 ; LINE CONTROL REG
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SIO_MCR .EQU SIO_BASE + 4 ; MODEM CONTROL REG
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SIO_LSR .EQU SIO_BASE + 5 ; LINE STATUS REG
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SIO_MSR .EQU SIO_BASE + 6 ; MODEM STATUS REG
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SIO_SCR .EQU SIO_BASE + 7 ; SCRATCH REGISTER
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SIO_DLL .EQU SIO_BASE + 0 ; DLAB=1: DIVISOR LATCH (LS)
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SIO_DLM .EQU SIO_BASE + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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;==================================================================
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