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186 lines
4.5 KiB
186 lines
4.5 KiB
;
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;==================================================================================================
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; LOADER
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;==================================================================================================
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;
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P2LOC .EQU $F000 ; PHASE 2 RUN LOCATION
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;
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#IFDEF ROMLOAD
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CURBNK .EQU BID_BOOT
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#ELSE
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CURBNK .EQU BID_USR
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#ENDIF
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;
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;==================================================================================================
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; COLD START
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;==================================================================================================
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;
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START:
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DI ; NO INTERRUPTS
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IM 1 ; INTERRUPT MODE 1
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LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
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;
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; HARDWARE BOOTSTRAP FOR Z180
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; FOR N8, ACR & RMAP ARE ASSUMED TO BE ALREADY SET OR THIS CODE
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; WOULD NOT BE EXECUTING
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;
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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; SET BASE FOR CPU IO REGISTERS
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LD A,Z180_BASE
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OUT0 (Z180_ICR),A
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; DISABLE REFRESH
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XOR A
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OUT0 (Z180_RCR),A
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; SET DEFAULT CPU CLOCK MULTIPLIERS (XTAL / 2)
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XOR A
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OUT0 (Z180_CCR),A
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OUT0 (Z180_CMR),A
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; SET DEFAULT WAIT STATES
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LD A,$F0
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OUT0 (Z180_DCNTL),A
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; MMU SETUP
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LD A,$80
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OUT0 (Z180_CBAR),A ; SETUP FOR 32K/32K BANK CONFIG
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#IFDEF ROMLOAD
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XOR A
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OUT0 (Z180_BBR),A ; BANK BASE = 0
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#ENDIF
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LD A,(RAMSIZE + RAMBIAS - 64) >> 2
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OUT0 (Z180_CBR),A ; COMMON BASE = LAST (TOP) BANK
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#IF (Z180_CLKDIV >= 1)
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; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
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LD A,$80
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OUT0 (Z180_CCR),A
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#ENDIF
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#IF (Z180_CLKDIV >= 2)
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; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
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LD A,$80
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OUT0 (Z180_CMR),A
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#ENDIF
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; SET DESIRED WAIT STATES
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LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
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OUT0 (Z180_DCNTL),A
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#ENDIF
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;
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; HARDWARE BOOTSTRAP FOR ZETA 2
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;
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#IF (PLATFORM == PLT_ZETA2)
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; SET PAGING REGISTERS
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#IFDEF ROMLOAD
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XOR A
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OUT (MPGSEL_0),A
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INC A
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OUT (MPGSEL_1),A
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#ENDIF
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LD A,62
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OUT (MPGSEL_2),A
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INC A
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OUT (MPGSEL_3),A
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; ENABLE PAGING
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LD A,1
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OUT (MPGENA),A
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#ENDIF
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;
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; COPY OURSELVES AND LOADER TO HI RAM FOR PHASE 2
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;
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LD HL,0 ; COPY FROM START OF ROM IMAGE
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LD DE,P2LOC ; TO HIMEM RUN LOCATION
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LD BC,LDR_END ; COPY FULL IMAGE
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LDIR
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JP PHASE2 ; JUMP TO PHASE 2 BOOT IN UPPER MEMORY
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;
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; THIS IS THE PHASE 2 CODE THAT MUST EXECUTE IN UPPER MEMORY
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;
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.ORG $ + P2LOC ; WE ARE NOW EXECUTING IN UPPER MEMORY
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;
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PHASE2:
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;
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; INSTALL HBIOS PROXY IN UPPER MEMORY
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;
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;#IFDEF ROMLOAD
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; LD A,BID_BIOSIMG ; HBIOS IMAGE ROM BANK
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; CALL BNKSEL ; SELECT IT
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;#ENDIF
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LD HL,HBX_IMG ; HL := SOURCE OF HBIOS PROXY IMAGE
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#IFNDEF ROMLOAD
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LD BC,LDR_END ; SIZE OF LOADER
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ADD HL,BC ; OFFSET SOURCE ADDRESS
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#ENDIF
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LD DE,HBX_LOC ; DE := DESTINATION TO INSTALL IT
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LD BC,HBX_SIZ ; SIZE
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LDIR ; DO THE COPY
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LD A,CURBNK ; BOOT/SETUP BANK
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LD (HB_CURBNK),A ; INIT CURRENT BANK
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;#IFDEF ROMLOAD
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; CALL BNKSEL ; SELECT IT
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;#ENDIF
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;
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; INSTALL HBIOS CODE BANK
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;
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;#IFDEF ROMLOAD
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; LD A,BID_BIOSIMG ; SOURCE BANK
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;#ELSE
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LD A,(HB_CURBNK) ; SOURCE BANK
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;#ENDIF
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LD (HB_SRCBNK),A ; SET IT
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LD A,BID_BIOS ; DESTINATION BANK
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LD (HB_DSTBNK),A ; SET IT
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LD HL,0 ; SOURCE ADDRESS IS ZERO
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#IFNDEF ROMLOAD
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LD BC,LDR_END ; SIZE OF LOADER
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ADD HL,BC ; OFFSET SOURCE ADDRESS
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#ENDIF
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LD DE,0 ; TARGET ADDRESS IS ZERO
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LD BC,HB_END ; COPY ALL OF HBIOS IMAGE
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CALL HB_BNKCPY ; DO IT
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;
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; INITIALIZE HBIOS
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;
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LD A,BID_BIOS ; HBIOS BANK
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LD HL,0 ; ADDRESS 0 IS HBIOS INIT ENTRY ADDRESS
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CALL HB_BNKCALL ; DO IT
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;
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; CHAIN TO OS LOADER
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;
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#IFDEF ROMLOAD
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; PERFORM BANK CALL TO OS IMAGES BANK
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LD A,BID_OSIMG ; CHAIN TO OS IMAGES BANK
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LD HL,0 ; ENTER AT ADDRESS 0
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CALL HB_BNKCALL ; GO THERE
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HALT ; WE SHOULD NEVER COME BACK!
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#ELSE
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; SLIDE OS IMAGES BLOB DOWN TO $0000
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LD HL,LDR_END ; SOURCE IS LOADER END
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LD BC,HB_END ; PLUS HBIOS IMAGE SIZE
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ADD HL,BC ; FINAL SOURCE ADDRESS
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LD DE,0 ; TARGET ADDRESS IS ZERO
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LD BC,BNKTOP ; MAX SIZE OF OS IMAGES
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LDIR ; DO IT
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; JUMP TO START
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JP 0 ; AND CHAIN
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#ENDIF
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;
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;==================================================================================================
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; MEMORY MANAGER
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;==================================================================================================
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;
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#IFDEF ROMLOAD
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#INCLUDE "memmgr.asm"
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#ENDIF
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;
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;==================================================================================================
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; CLEAN UP
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;==================================================================================================
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;
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.ORG $ - P2LOC ; BACK TO IMAGE-BASED ADDRESSING
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LDR_END .EQU $ ; MARK END OF LOADER
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