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681 lines
14 KiB
681 lines
14 KiB
;
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;==================================================================================================
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; PPIDE DISK DRIVER
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;==================================================================================================
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;
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; 11/29/2011 dwg - DOUGDEBUG controls the embedded NOPs which adjust for
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; recovery time while using the parallel port to talk to the PPIDE and IDE
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; device. Using this stabilized by Zeta (8MHz) with a CF chip.
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;
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; 12/02/2011 wbw - renamed DOUGDEBUG to PPIDESLOW and exposed in config
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; PPIDESLOW now controls the RECOVERY macro definition.
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;
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#IF (PPIDESLOW)
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#DEFINE RECOVERY NOP\ NOP\ NOP\ NOP
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#ELSE
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#DEFINE RECOVERY ;
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#ENDIF
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;
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; MAP PPI PORTS TO PPIDE PORTS
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;
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#IF (PPIDEMODE == PPIDEMODE_DIO3)
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IDELSB .EQU 20H ; LSB
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IDEMSB .EQU 21H ; MSB
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IDECTL .EQU 22H ; CONTROL SIGNALS
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PPI1CONT .EQU 23H ; CONTROL BYTE PPI 82C55
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#ELSE
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IDELSB .EQU PPIA ; LSB
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IDEMSB .EQU PPIB ; MSB
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IDECTL .EQU PPIC ; CONTROL SIGNALS
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PPI1CONT .EQU PPIX ; CONTROL BYTE PPI 82C55
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#ENDIF
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;
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; PPI control bytes for read and write to IDE drive
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;
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RD_IDE_8255 .EQU 10010010B ; IDE_8255_CTL OUT, IDE_8255_LSB/MSB INPUT
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WR_IDE_8255 .EQU 10000000B ; ALL THREE PORTS OUTPUT
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;
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; IDE CONTROL LINES FOR USE WITH IDE_8255_CTL. CHANGE THESE 8
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; CONSTANTS TO REFLECT WHERE EACH SIGNAL OF THE 8255 EACH OF THE
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; IDE CONTROL SIGNALS IS CONNECTED. ALL THE CONTROL SIGNALS MUST
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; BE ON THE SAME PORT, BUT THESE 8 LINES LET YOU CONNECT THEM TO
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; WHICHEVER PINS ON THAT PORT.
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;
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PPIDE_A0_LINE .EQU 01H ; DIRECT FROM 8255 TO IDE INTERFACE
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PPIDE_A1_LINE .EQU 02H ; DIRECT FROM 8255 TO IDE INTERFACE
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PPIDE_A2_LINE .EQU 04H ; DIRECT FROM 8255 TO IDE INTERFACE
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PPIDE_CS0_LINE .EQU 08H ; INVERTER BETWEEN 8255 AND IDE INTERFACE
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PPIDE_CS1_LINE .EQU 10H ; INVERTER BETWEEN 8255 AND IDE INTERFACE
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PPIDE_WR_LINE .EQU 20H ; INVERTER BETWEEN 8255 AND IDE INTERFACE
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PPIDE_RD_LINE .EQU 40H ; INVERTER BETWEEN 8255 AND IDE INTERFACE
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PPIDE_RST_LINE .EQU 80H ; INVERTER BETWEEN 8255 AND IDE INTERFACE
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;
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;------------------------------------------------------------------
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; MORE SYMBOLIC CONSTANTS... THESE SHOULD NOT BE CHANGED, UNLESS OF
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; COURSE THE IDE DRIVE INTERFACE CHANGES, PERHAPS WHEN DRIVES GET
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; TO 128G AND THE PC INDUSTRY WILL DO YET ANOTHER KLUDGE.
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;
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; SOME SYMBOLIC CONSTANTS FOR THE IDE REGISTERS, WHICH MAKES THE
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; CODE MORE READABLE THAN ALWAYS SPECIFYING THE ADDRESS PINS
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;
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PPIDE_DATA .EQU PPIDE_CS0_LINE
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PPIDE_ERROR .EQU PPIDE_CS0_LINE + PPIDE_A0_LINE
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PPIDE_SEC_CNT .EQU PPIDE_CS0_LINE + PPIDE_A1_LINE
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PPIDE_SECTOR .EQU PPIDE_CS0_LINE + PPIDE_A1_LINE + PPIDE_A0_LINE
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PPIDE_CYL_LSB .EQU PPIDE_CS0_LINE + PPIDE_A2_LINE
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PPIDE_CYL_MSB .EQU PPIDE_CS0_LINE + PPIDE_A2_LINE + PPIDE_A0_LINE
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PPIDE_HEAD .EQU PPIDE_CS0_LINE + PPIDE_A2_LINE + PPIDE_A1_LINE
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PPIDE_COMMAND .EQU PPIDE_CS0_LINE + PPIDE_A2_LINE + PPIDE_A1_LINE + PPIDE_A0_LINE
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PPIDE_STTS .EQU PPIDE_CS0_LINE + PPIDE_A2_LINE + PPIDE_A1_LINE + PPIDE_A0_LINE
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PPIDE_CONTROL .EQU PPIDE_CS1_LINE + PPIDE_A2_LINE + PPIDE_A1_LINE
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PPIDE_ASTTS .EQU PPIDE_CS1_LINE + PPIDE_A2_LINE + PPIDE_A1_LINE + PPIDE_A0_LINE
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;
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; IDE COMMAND CONSTANTS. THESE SHOULD NEVER CHANGE.
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;
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PPIDECMD_RECAL .EQU 010H
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PPIDECMD_READ .EQU 020H
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PPIDECMD_WRITE .EQU 030H
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PPIDECMD_INIT .EQU 091H
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PPIDECMD_ID .EQU 0ECH
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PPIDECMD_SPINDOWN .EQU 0E0H
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PPIDECMD_SPINUP .EQU 0E1H
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PPIDECMD_SETFEAT .EQU 0EFH
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;
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PPIDERC_OK .EQU 0
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PPIDERC_CMDERR .EQU 1
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PPIDERC_RDYTO .EQU 2
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PPIDERC_BUFTO .EQU 3
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;
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; UNIT CONFIGURATION
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;
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PPIDE0_DEVICE .DB 11100000B ; LBA, MASTER DEVICE
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PPIDE1_DEVICE .DB 11110000B ; LBA, SLAVE DEVICE
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;
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;
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;
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PPIDE_DISPATCH:
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LD A,B ; GET REQUESTED FUNCTION
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AND $0F
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JR Z,PPIDE_RD
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DEC A
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JR Z,PPIDE_WR
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DEC A
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JR Z,PPIDE_ST
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DEC A
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JR Z,PPIDE_MED
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CALL PANIC
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;
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PPIDE_RD:
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JP PPIDE_XREAD
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PPIDE_WR:
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JP PPIDE_XWRITE
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PPIDE_ST:
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JP PPIDE_STATUS
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PPIDE_MED:
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JP PPIDE_MEDIA
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;
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; PPIDE_MEDIA
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;
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PPIDE_MEDIA:
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LD A,MID_HD
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RET
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;
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;
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;
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PPIDE_INIT:
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PRTS("PPIDE: IO=0x$")
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LD A,IDELSB
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CALL PRTHEXBYTE
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PRTS(" UNITS=2$")
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#IF (PPIDESLOW)
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PRTS(" SLOW$")
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#ENDIF
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CALL PPIDE_RESET
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XOR A
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DEC A ; INITIAL STATUS IS NOT READY $FF
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LD (PPIDE_STAT),A ; SAVE IT
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RET
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;
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;
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;
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PPIDE_STATUS:
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LD A,(PPIDE_STAT) ; LOAD STATUS
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OR A ; SET FLAGS
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RET
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;
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;
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;
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PPIDE_XREAD:
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LD A,PPIDECMD_READ
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LD (PPIDEP_CMD),A
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JP PPIDE_RW
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;
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;
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;
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PPIDE_XWRITE:
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LD A,PPIDECMD_WRITE
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LD (PPIDEP_CMD),A
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JP PPIDE_RW
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;
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;
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;
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PPIDE_RW:
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; CLEAR RESULTS
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XOR A ; A = 0
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LD (PPIDE_RC),A ; CLEAR RETURN CODE
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LD (PPIDEP_STTS),A ; CLEAR SAVED STTS
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LD (PPIDEP_ERR),A ; CLEAR SAVED ERR
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; INIT REQUIRED?
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LD A,(PPIDE_STAT)
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OR A ; SET FLAGS
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JR Z,PPIDE_RW0 ; IF STATUS OK, BYPASS RESET
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CALL PPIDE_RESET ; DO THE RESET
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#IF (PPIDE8BIT)
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CALL PPIDE_WAITRDY
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LD C,01H
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LD A,PPIDE_ERROR
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CALL PPIDE_WRITE
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LD C,PPIDECMD_SETFEAT
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LD A,PPIDE_COMMAND
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CALL PPIDE_WRITE
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CALL PPIDE_WAITRDY
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JP NC,PPIDE_ERR
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CALL PPIDE_CHKERR ; CHECK FOR ERRORS
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JP NC,PPIDE_ERR
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#IF (PPIDETRACE >= 2)
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CALL IDE_PRT
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#ENDIF
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#ENDIF
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PPIDE_RW0:
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CALL PPIDE_WAITRDY ; WAIT FOR DRIVE READY
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JP NC,PPIDE_ERR
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CALL PPIDE_SETUP ; SETUP CYL, TRK, HEAD
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LD A,(PPIDEP_CMD)
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LD C,A
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LD A,PPIDE_COMMAND
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CALL PPIDE_WRITE
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CALL PPIDE_WAITRDY ; WAIT FOR DRIVE READY
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JP NC,PPIDE_ERR
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CALL PPIDE_CHKERR ; CHECK FOR ERRORS
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JP NC,PPIDE_ERR
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CALL PPIDE_WAITBUF ; WAIT FOR BUFFER READY
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JP NC,PPIDE_ERR
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LD A,(PPIDEP_CMD) ; DISPATCH TO READ OR WRITE SPECIFIC LOGIC
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CP PPIDECMD_WRITE
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JP Z,PPIDE_RW1
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CALL PPIDE_BUFRD ; READ BUFFER
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CALL PPIDE_WAITRDY ; WAIT FOR DRIVE READY
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JP NC,PPIDE_ERR
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CALL PPIDE_CHKERR ; CHECK FOR ERRORS
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JP NC,PPIDE_ERR
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JP PPIDE_OK
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PPIDE_RW1:
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CALL PPIDE_BUFWR ; WRITE BUFFER
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CALL PPIDE_WAITRDY ; WAIT FOR DRIVE READY
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JP NC,PPIDE_ERR
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CALL PPIDE_CHKERR ; CHECK FOR ERRORS
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JP NC,PPIDE_ERR
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JP PPIDE_OK
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PPIDE_ERR:
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XOR A
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DEC A ; A = $FF TO SIGNAL ERROR
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LD (PPIDE_STAT),A ; SAVE IT
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#IF (PPIDETRACE >= 1)
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PUSH AF
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CALL PPIDE_PRT
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POP AF
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#ENDIF
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RET
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PPIDE_OK:
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#IF (PPIDETRACE >= 2)
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CALL PPIDE_PRT
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#ENDIF
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XOR A
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RET
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;
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;
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;
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PPIDE_RESET:
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LD C,000001110B ; NO INTERRUPTS, ASSERT RESET BOTH DRIVES
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LD A,PPIDE_CONTROL
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CALL PPIDE_WRITE
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LD DE,8 ; DELAY ABOUT 200ms
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CALL VDELAY
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LD C,000000010B ; NO INTERRUPTS, DEASSERT RESET
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LD A,PPIDE_CONTROL
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CALL PPIDE_WRITE
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XOR A ; STATUS OK
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LD (PPIDE_STAT),A ; SAVE IT
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RET
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;
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;
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;
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PPIDE_WAITRDY:
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LD DE,0 ; TIMEOUT IS 250us * 65536 = 15 SECONDS
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PPIDE_WBSY:
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PUSH DE
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LD DE,10 ; INNER LOOP DELAY IS 250us (25us * 10)
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CALL VDELAY
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POP DE
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DEC DE
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LD A,D
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OR E
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JP Z,PPIDE_TO
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LD A,PPIDE_STTS
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CALL PPIDE_READ
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LD A,C
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LD (PPIDEP_STTS),A ; SAVE IT
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AND 011000000B ; ISOLATE BUSY AND RDY BITS
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XOR 001000000B ; WE WANT BUSY(7) TO BE 0 AND RDY(6) TO BE 1
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JP NZ,PPIDE_WBSY
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SCF ; CARRY 1 = OK
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RET
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PPIDE_TO:
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LD A,PPIDERC_RDYTO
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LD (PPIDE_RC),A
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XOR A ; CARRY 0 = TIMEOUT
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RET
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;
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;
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;
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PPIDE_CHKERR:
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LD A,PPIDE_STTS
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CALL PPIDE_READ
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LD A,C
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LD (PPIDEP_STTS),A ; SAVE IT
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AND 000000001B ; ERROR BIT SET?
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SCF ; ASSUME NO ERR
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RET Z ; NO ERR, RETURN WITH CF SET
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LD A,PPIDE_ERROR
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CALL PPIDE_READ
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LD A,C
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LD (PPIDEP_ERR),A ; SAVE IT
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LD A,PPIDERC_CMDERR ; COMMAND ERROR
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LD (PPIDE_RC),A ; SAVE IT
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OR A ; CLEAR CF TO SIGNAL ERROR
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RET
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;
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;
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;
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PPIDE_WAITBUF:
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LD DE,0
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PPIDE_WDRQ:
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CALL DELAY
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INC DE
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LD A,D
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OR E
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JP Z,PPIDE_TO2
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LD A,PPIDE_STTS
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CALL PPIDE_READ
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LD A,C
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LD (PPIDEP_STTS),A ; SAVE IT
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AND 010001000B ; TO FILL (OR READY TO FILL)
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XOR 000001000B
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JP NZ,PPIDE_WDRQ
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SCF ; CARRY 1 = OK
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RET
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PPIDE_TO2:
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LD A,PPIDERC_BUFTO
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LD (PPIDE_RC),A
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XOR A ; CARRY 0 = TIMED OUT
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RET
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;
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;
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;
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#IF (PPIDE8BIT)
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PPIDE_BUFRD:
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LD HL,(DIOBUF)
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LD DE,200H
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PPIDE_BUFRD1:
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LD A,PPIDE_DATA
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CALL PPIDE_READ
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LD (HL),C
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INC HL
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DEC DE
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LD A,D
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OR E
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JP NZ,PPIDE_BUFRD1
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RET
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#ELSE
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PPIDE_BUFRD:
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LD HL,(DIOBUF)
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LD D,0
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PPIDE_BUFRD1:
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LD A,PPIDE_DATA
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CALL PPIDE_READ
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LD (HL),C
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INC HL
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LD (HL),B
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INC HL
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DEC D
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JP NZ,PPIDE_BUFRD1
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RET
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#ENDIF
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;
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;
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;
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#IF (PPIDE8BIT)
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PPIDE_BUFWR:
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LD HL,(DIOBUF)
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LD DE,200H
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PPIDE_BUFWR1:
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LD C,(HL)
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LD A,PPIDE_DATA
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CALL PPIDE_WRITE
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INC HL
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DEC DE
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LD A,D
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OR E
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JP NZ,PPIDE_BUFWR1
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#ELSE
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PPIDE_BUFWR:
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LD HL,(DIOBUF)
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LD D,0
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PPIDE_BUFWR1:
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LD C,(HL)
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INC HL
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LD B,(HL)
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INC HL
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LD A,PPIDE_DATA
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CALL PPIDE_WRITE
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DEC D
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JP NZ,PPIDE_BUFWR1
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RET
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#ENDIF
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;
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;
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;
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PPIDE_SETUP:
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LD C,1
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LD A,PPIDE_SEC_CNT
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CALL PPIDE_WRITE
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LD A,(HSTDSK) ; HSTDSK -> HEAD BIT 4 TO SELECT UNIT
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AND 0FH
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CP 0
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JP Z,PPIDE_SETUP_UNIT0
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CP 1
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JP Z,PPIDE_SETUP_UNIT1
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CALL PANIC
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PPIDE_SETUP_UNIT0:
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LD A,(PPIDE0_DEVICE)
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; LD DE,(PPIDE0_OFFSET)
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JP PPIDE_SETUP1
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PPIDE_SETUP_UNIT1:
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LD A,(PPIDE1_DEVICE)
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; LD DE,(PPIDE1_OFFSET)
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JP PPIDE_SETUP1
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PPIDE_SETUP1:
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LD (PPIDEP_HEAD),A
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LD C,A
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LD A,PPIDE_HEAD
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CALL PPIDE_WRITE
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LD HL,(HSTTRK) ; HSTTRK -> IDECYLHI/LO
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LD A,H
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LD (PPIDEP_CYLHI),A
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LD C,A
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LD A,PPIDE_CYL_MSB
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CALL PPIDE_WRITE
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LD A,L
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LD (PPIDEP_CYLLO),A
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LD C,A
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LD A,PPIDE_CYL_LSB
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CALL PPIDE_WRITE
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LD BC,(HSTSEC) ; HSTSEC -> IDESECTN
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LD A,C
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LD (PPIDEP_SEC),A
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LD C,A
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LD A,PPIDE_SECTOR
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CALL PPIDE_WRITE
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#IF (DSKYENABLE)
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CALL PPIDE_DSKY
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#ENDIF
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RET
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;
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;
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;
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PPIDE_READ:
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PUSH AF ; save register value
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LD A,RD_IDE_8255
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OUT (PPI1CONT),A ; Config 8255 chip, read mode
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RECOVERY
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POP AF ; restore register value
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OUT (IDECTL),A ; Drive address onto control lines
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RECOVERY
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OR PPIDE_RD_LINE ; assert RD pin
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OUT (IDECTL),A
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RECOVERY
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PUSH AF ; save register value
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IN A,(IDELSB) ; read lower byte
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RECOVERY
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LD C,A ; save in reg C
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IN A,(IDEMSB) ; read upper byte
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RECOVERY
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LD B,A ; save in reg C
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POP AF ; restore register value
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XOR PPIDE_RD_LINE ; de-assert RD signal
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OUT (IDECTL),A
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RECOVERY
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XOR A
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OUT (IDECTL),A ; Deassert all control pins
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RECOVERY
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RET
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;
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;
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;
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PPIDE_WRITE:
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PUSH AF ; save IDE register value
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LD A,WR_IDE_8255
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OUT (PPI1CONT),A ; Config 8255 chip, write mode
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RECOVERY
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LD A,C ; get value to be written
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OUT (IDELSB),A
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RECOVERY
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LD A,B ; get value to be written
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OUT (IDEMSB),A
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RECOVERY
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POP AF ; get saved IDE register
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OUT (IDECTL),A ; Drive address onto control lines
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RECOVERY
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OR PPIDE_WR_LINE ; assert write pin
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OUT (IDECTL),A
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RECOVERY
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XOR PPIDE_WR_LINE ; de assert WR pin
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OUT (IDECTL),A ; Drive address onto control lines
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RECOVERY
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XOR A
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OUT (IDECTL),A ; release bus signals
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RECOVERY
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RET
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;
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;
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;
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#IF (DSKYENABLE)
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PPIDE_DSKY:
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LD HL,DSKY_HEXBUF
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LD A,(PPIDEP_HEAD)
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LD (HL),A
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INC HL
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LD A,(PPIDEP_CYLHI)
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LD (HL),A
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INC HL
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LD A,(PPIDEP_CYLLO)
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LD (HL),A
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INC HL
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LD A,(PPIDEP_SEC)
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LD (HL),A
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CALL DSKY_HEXOUT
|
|
RET
|
|
#ENDIF
|
|
;
|
|
;
|
|
;
|
|
PPIDE_PRT:
|
|
CALL NEWLINE
|
|
|
|
LD DE,PPIDESTR_PREFIX
|
|
CALL WRITESTR
|
|
|
|
CALL PC_SPACE
|
|
LD DE,PPIDESTR_CMD
|
|
CALL WRITESTR
|
|
LD A,(PPIDEP_CMD)
|
|
CALL PRTHEXBYTE
|
|
|
|
CALL PC_SPACE
|
|
CALL PC_LBKT
|
|
LD A,(PPIDEP_CMD)
|
|
LD DE,PPIDESTR_READ
|
|
CP PPIDECMD_READ
|
|
JP Z,PPIDE_PRTCMD
|
|
LD DE,PPIDESTR_WRITE
|
|
CP PPIDECMD_READ
|
|
JP Z,PPIDE_PRTCMD
|
|
LD DE,PPIDESTR_UNKCMD
|
|
PPIDE_PRTCMD:
|
|
CALL WRITESTR
|
|
CALL PC_RBKT
|
|
|
|
CALL PC_SPACE
|
|
LD A,(PPIDEP_HEAD)
|
|
CALL PRTHEXBYTE
|
|
LD A,(PPIDEP_CYLHI)
|
|
CALL PRTHEXBYTE
|
|
LD A,(PPIDEP_CYLLO)
|
|
CALL PRTHEXBYTE
|
|
LD A,(PPIDEP_SEC)
|
|
CALL PRTHEXBYTE
|
|
|
|
CALL PC_SPACE
|
|
LD DE,PPIDESTR_ARROW
|
|
CALL WRITESTR
|
|
|
|
CALL PC_SPACE
|
|
LD A,PPIDE_STTS
|
|
CALL PPIDE_READ
|
|
LD A,C
|
|
CALL PRTHEXBYTE
|
|
|
|
CALL PC_SPACE
|
|
LD A,PPIDE_ERROR
|
|
CALL PPIDE_READ
|
|
LD A,C
|
|
CALL PRTHEXBYTE
|
|
|
|
CALL PC_SPACE
|
|
LD DE,PPIDESTR_RC
|
|
CALL WRITESTR
|
|
LD A,(PPIDE_RC)
|
|
CALL PRTHEXBYTE
|
|
|
|
CALL PC_SPACE
|
|
CALL PC_LBKT
|
|
LD A,(PPIDE_RC)
|
|
LD DE,PPIDESTR_RCOK
|
|
CP PPIDERC_OK
|
|
JP Z,PPIDE_PRTRC
|
|
LD DE,PPIDESTR_RCCMDERR
|
|
CP PPIDERC_CMDERR
|
|
JP Z,PPIDE_PRTRC
|
|
LD DE,PPIDESTR_RCRDYTO
|
|
CP PPIDERC_RDYTO
|
|
JP Z,PPIDE_PRTRC
|
|
LD DE,PPIDESTR_RCBUFTO
|
|
CP PPIDERC_BUFTO
|
|
JP Z,PPIDE_PRTRC
|
|
LD DE,PPIDESTR_RCUNK
|
|
PPIDE_PRTRC:
|
|
CALL WRITESTR
|
|
CALL PC_RBKT
|
|
|
|
RET
|
|
;
|
|
;
|
|
;
|
|
PPIDESTR_PREFIX .TEXT "PPIDE:$"
|
|
PPIDESTR_CMD .TEXT "CMD=$"
|
|
PPIDESTR_RC .TEXT "RC=$"
|
|
PPIDESTR_ARROW .TEXT "-->$"
|
|
PPIDESTR_READ .TEXT "READ$"
|
|
PPIDESTR_WRITE .TEXT "WRITE$"
|
|
PPIDESTR_UNKCMD .TEXT "UNKCMD"
|
|
PPIDESTR_RCOK .TEXT "OK$"
|
|
PPIDESTR_RCCMDERR .TEXT "COMMAND ERROR$"
|
|
PPIDESTR_RCRDYTO .TEXT "READY TIMEOUT$"
|
|
PPIDESTR_RCBUFTO .TEXT "BUFFER TIMEOUT$"
|
|
PPIDESTR_RCUNK .TEXT "UNKNOWN ERROR$"
|
|
;
|
|
;==================================================================================================
|
|
; PPIDE DISK DRIVER - DATA
|
|
;==================================================================================================
|
|
;
|
|
PPIDE_STAT .DB 0
|
|
PPIDE_RC .DB 0
|
|
;
|
|
; PPIDE PARAMETERS
|
|
;
|
|
PPIDEP_CMD .DB 0
|
|
PPIDEP_HEAD .DB 0
|
|
PPIDEP_CYLHI .DB 0
|
|
PPIDEP_CYLLO .DB 0
|
|
PPIDEP_SEC .DB 0
|
|
PPIDEP_STTS .DB 0
|
|
PPIDEP_ERR .DB 0
|
|
;
|
|
;
|
|
;
|
|
;
|
|
;
|
|
;
|
|
;
|
|
; Error Register (ERR bit being set in the Status Register)
|
|
;
|
|
; Bit 7: BBK (Bad Block Detected) Set when a Bad Block is detected.
|
|
; Bit 6: UNC (Uncorrectable Data Error) Set when Uncorrectable Error is encountered.
|
|
; Bit 5: MC (Media Changed) Set to 0.
|
|
; Bit 4: IDNF (ID Not Found) Set when Sector ID not found.
|
|
; Bit 3: MCR (Media Change Request) Set to 0.
|
|
; Bit 2: ABRT (Aborted Command) Set when Command Aborted due to drive error.
|
|
; Bit 1: TKONF (Track 0 Not Found) Set when Executive Drive Diagnostic Command.
|
|
; Bit 0: AMNF (Address mark Not Found) Set in case of a general error.
|
|
;
|
|
; Status Register (When the contents of this register are read by the host, the IREQ# bit is cleared)
|
|
;
|
|
; Bit 7: BSY (Busy) Set when the drive is busy and unable to process any new ATA commands.
|
|
; Bit 6: DRDY (Data Ready) Set when the device is ready to accept ATA commands from the host.
|
|
; Bit 5: DWF (Drive Write Fault) Always set to 0.
|
|
; Bit 4: DSC (Drive Seek Complete) Set when the drive heads have been positioned over a specific track.
|
|
; Bit 3: DRQ (Data Request) Set when device is ready to transfer a word or byte of data to or from the host and the device.
|
|
; Bit 2: CORR (Corrected Data) Always set to 0.
|
|
; Bit 1: IDX (Index) Always set to 0.
|
|
; Bit 0: ERR (Error) Set when an error occurred during the previous ATA command.
|