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95 lines
3.7 KiB
95 lines
3.7 KiB
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; Z180 REGISTERS
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;
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CPU_BASE .EQU 40H ; ONLY RELEVANT FOR Z180
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;
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CPU_CNTLA0 .EQU CPU_BASE + $00 ;ASCI0 control A
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CPU_CNTLA1: .EQU CPU_BASE+$01 ;ASCI1 control A
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CPU_CNTLB0: .EQU CPU_BASE+$02 ;ASCI0 control B
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CPU_CNTLB1: .EQU CPU_BASE+$03 ;ASCI1 control B
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CPU_STAT0: .EQU CPU_BASE+$04 ;ASCI0 status
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CPU_STAT1: .EQU CPU_BASE+$05 ;ASCI1 status
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CPU_TDR0: .EQU CPU_BASE+$06 ;ASCI0 transmit
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CPU_TDR1: .EQU CPU_BASE+$07 ;ASCI1 transmit
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CPU_RDR0: .EQU CPU_BASE+$08 ;ASCI0 receive
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CPU_RDR1: .EQU CPU_BASE+$09 ;ASCI1 receive
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CPU_CNTR: .EQU CPU_BASE+$0A ;CSI/O control
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CPU_TRDR: .EQU CPU_BASE+$0B ;CSI/O transmit/receive
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CPU_TMDR0L: .EQU CPU_BASE+$0C ;Timer 0 data lo
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CPU_TMDR0H: .EQU CPU_BASE+$0D ;Timer 0 data hi
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CPU_RLDR0L: .EQU CPU_BASE+$0E ;Timer 0 reload lo
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CPU_RLDR0H: .EQU CPU_BASE+$0F ;Timer 0 reload hi
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CPU_TCR: .EQU CPU_BASE+$10 ;Timer control
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;
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CPU_ASEXT0: .EQU CPU_BASE+$12 ;ASCI0 extension control (Z8S180)
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CPU_ASEXT1: .EQU CPU_BASE+$13 ;ASCI1 extension control (Z8S180)
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;
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CPU_TMDR1L: .EQU CPU_BASE+$14 ;Timer 1 data lo
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CPU_TMDR1H: .EQU CPU_BASE+$15 ;Timer 1 data hi
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CPU_RLDR1L: .EQU CPU_BASE+$16 ;Timer 1 reload lo
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CPU_RLDR1H: .EQU CPU_BASE+$17 ;Timer 1 reload hi
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CPU_FRC: .EQU CPU_BASE+$18 ;Free running counter
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CPU_ASTC0L: .EQU CPU_BASE+$1A ;ASCI0 Time constant lo (Z8S180)
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CPU_ASTC0H: .EQU CPU_BASE+$1B ;ASCI0 Time constant hi (Z8S180)
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CPU_ASTC1L: .EQU CPU_BASE+$1C ;ASCI1 Time constant lo (Z8S180)
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CPU_ASTC1H: .EQU CPU_BASE+$1D ;ASCI1 Time constant hi (Z8S180)
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CPU_CMR: .EQU CPU_BASE+$1E ;Clock multiplier (latest Z8S180)
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CPU_CCR: .EQU CPU_BASE+$1F ;CPU control (Z8S180)
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;
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CPU_SAR0L: .EQU CPU_BASE+$20 ;DMA0 source addr lo
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CPU_SAR0H: .EQU CPU_BASE+$21 ;DMA0 source addr hi
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CPU_SAR0B: .EQU CPU_BASE+$22 ;DMA0 source addr bank
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CPU_DAR0L: .EQU CPU_BASE+$23 ;DMA0 dest addr lo
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CPU_DAR0H: .EQU CPU_BASE+$24 ;DMA0 dest addr hi
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CPU_DAR0B: .EQU CPU_BASE+$25 ;DMA0 dest addr bank
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CPU_BCR0L: .EQU CPU_BASE+$26 ;DMA0 byte count lo
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CPU_BCR0H: .EQU CPU_BASE+$27 ;DMA0 byte count hi
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CPU_MAR1L: .EQU CPU_BASE+$28 ;DMA1 memory addr lo
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CPU_MAR1H: .EQU CPU_BASE+$29 ;DMA1 memory addr hi
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CPU_MAR1B: .EQU CPU_BASE+$2A ;DMA1 memory addr bank
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CPU_IAR1L: .EQU CPU_BASE+$2B ;DMA1 I/O addr lo
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CPU_IAR1H: .EQU CPU_BASE+$2C ;DMA1 I/O addr hi
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CPU_IAR1B: .EQU CPU_BASE+$2D ;DMA1 I/O addr bank (Z8S180)
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CPU_BCR1L: .EQU CPU_BASE+$2E ;DMA1 byte count lo
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CPU_BCR1H: .EQU CPU_BASE+$2F ;DMA1 byte count hi
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CPU_DSTAT: .EQU CPU_BASE+$30 ;DMA status
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CPU_DMODE: .EQU CPU_BASE+$31 ;DMA mode
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CPU_DCNTL: .EQU CPU_BASE+$32 ;DMA/WAIT control
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CPU_IL: .EQU CPU_BASE+$33 ;Interrupt vector load
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CPU_ITC: .EQU CPU_BASE+$34 ;INT/TRAP control
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;
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CPU_RCR: .EQU CPU_BASE+$36 ;Refresh control
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;
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CPU_CBR: .EQU CPU_BASE+$38 ;MMU common base register
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CPU_BBR: .EQU CPU_BASE+$39 ;MMU bank base register
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CPU_CBAR .EQU CPU_BASE+$3A ;MMU common/bank area register
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;
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CPU_OMCR: .EQU CPU_BASE+$3E ;Operation mode control
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CPU_ICR: .EQU $3F ;I/O control register (not relocated!!!)
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;
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; N8 ONBOARD I/O REGISTERS
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;
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N8_BASE .EQU $80
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;
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PPIBASE .EQU N8_BASE + $00
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PPIA .EQU PPIBASE + 0 ; PORT A
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PPIB .EQU PPIBASE + 1 ; PORT B
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PPIC .EQU PPIBASE + 2 ; PORT C
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
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;
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PPI2BASE .EQU N8_BASE + $04
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PPI2A .EQU PPI2BASE + 0 ; PORT A
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PPI2B .EQU PPI2BASE + 1 ; PORT B
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PPI2C .EQU PPI2BASE + 2 ; PORT C
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PPI2X .EQU PPI2BASE + 3 ; PPI CONTROL PORT
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;
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RTC: .EQU N8_BASE + $08 ;RTC latch and buffer
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;FDC: .EQU N8_BASE + $0C ;Floppy disk controller
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;UTIL: .EQU N8_BASE + $10 ;Floppy disk utility
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ACR: .EQU N8_BASE + $14 ;auxillary control register
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RMAP: .EQU N8_BASE + $16 ;ROM page register
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VDP: .EQU N8_BASE + $18 ;Video Display Processor (TMS9918A)
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PSG: .EQU N8_BASE + $1C ;Programmable Sound Generator (AY-3-8910)
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;
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DEFACR .EQU $1B
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