mirror of https://github.com/wwarthen/RomWBW.git
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
65 lines
2.5 KiB
65 lines
2.5 KiB
;
|
|
; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
|
|
;
|
|
CPUKHZ .EQU CPUOSC ; FOR SBC 1/2, CPUFREQ == OSCILLATOR FREQ
|
|
CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN KHZ
|
|
;
|
|
#IF ((PLATFORM == PLT_N8VEM) | (PLATFORM == PLT_ZETA))
|
|
MPCL_RAM .EQU $78 ; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH (WRITE ONLY)
|
|
MPCL_ROM .EQU $7C ; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH (WRITE ONLY)
|
|
#ENDIF
|
|
;
|
|
#IF (PLATFORM == PLT_ZETA2)
|
|
MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
|
|
MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
|
|
MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
|
|
MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
|
|
MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
|
|
#ENDIF
|
|
;
|
|
RTC .EQU $70 ; ADDRESS OF RTC LATCH AND INPUT PORT
|
|
;
|
|
; PPI 82C55 I/O IS DECODED TO PORT 60-67
|
|
;
|
|
PPIBASE .EQU $60
|
|
PPIA .EQU PPIBASE + 0 ; PORT A
|
|
PPIB .EQU PPIBASE + 1 ; PORT B
|
|
PPIC .EQU PPIBASE + 2 ; PORT C
|
|
PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
|
|
;
|
|
; 16C550 SERIAL LINE UART
|
|
;
|
|
SIO_BASE .EQU $68
|
|
SIO_RBR .EQU SIO_BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
|
|
SIO_THR .EQU SIO_BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
|
|
SIO_IER .EQU SIO_BASE + 1 ; DLAB=0: INT ENABLE REG
|
|
SIO_IIR .EQU SIO_BASE + 2 ; INT IDENT REGISTER (READ ONLY)
|
|
SIO_FCR .EQU SIO_BASE + 2 ; FIFO CONTROL REG (WRITE ONLY)
|
|
SIO_LCR .EQU SIO_BASE + 3 ; LINE CONTROL REG
|
|
SIO_MCR .EQU SIO_BASE + 4 ; MODEM CONTROL REG
|
|
SIO_LSR .EQU SIO_BASE + 5 ; LINE STATUS REG
|
|
SIO_MSR .EQU SIO_BASE + 6 ; MODEM STATUS REG
|
|
SIO_SCR .EQU SIO_BASE + 7 ; SCRATCH REGISTER
|
|
SIO_DLL .EQU SIO_BASE + 0 ; DLAB=1: DIVISOR LATCH (LS)
|
|
SIO_DLM .EQU SIO_BASE + 1 ; DLAB=1: DIVISOR LATCH (MS)
|
|
;
|
|
; MEMORY BANK CONFIGURATION
|
|
;
|
|
BID_ROM0 .EQU $00
|
|
BID_ROMN .EQU (BID_ROM0 + ((ROMSIZE / 32) - 1))
|
|
BID_RAM0 .EQU $80
|
|
BID_RAMN .EQU (BID_RAM0 + ((RAMSIZE / 32) - 1))
|
|
|
|
BID_BOOT .EQU BID_ROM0 ; BOOT BANK
|
|
BID_BIOSIMG .EQU BID_ROM0 + 1 ; BIOS IMAGE BANK
|
|
BID_OSIMG .EQU BID_ROM0 + 2 ; ROM LOADER AND IMAGES BANK
|
|
BID_FSFAT .EQU BID_ROM0 + 3 ; FAT FILESYSTEM DRIVER BANK
|
|
BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK
|
|
BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK
|
|
|
|
BID_RAMD0 .EQU BID_RAM0 ; FIRST RAM DRIVE BANK
|
|
BID_RAMDN .EQU BID_RAMN - 4 ; LAST RAM DRIVE BANK
|
|
BID_AUX .EQU BID_RAMN - 3 ; AUX BANK (BPBIOS, ETC.)
|
|
BID_BIOS .EQU BID_RAMN - 2 ; BIOS BANK
|
|
BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.)
|
|
BID_COM .EQU BID_RAMN ; COMMON BANK, UPPER 32K
|
|
|