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RomWBW/Source/BPBIOS/hbios.z80
b1ackmai1er 78f65522b7 Dev (#108) 
* added hack to handle tunes

* quiet clean

* added chmod for execution

* suppress warnings

* Multi-boot fixes

* the windows build somehow thinks that these filesystems are cpm3.

* credit and primitive instructions

* Update sd.asm

Cosmetic fix.

* make compile shut up about conditionals

* Add bin2asm for linus and update build to process font files under linix

* fixed quoted double quote bug, added tests

* added tests

* added bin2asm for font file source creation

* Revert linux bin2asm font stuff

* added rule for font source generation

* build fonts

* added directory mapping cache.  if the same directory is being hit
as last run, we don't need to rebuild the map.  will likely break if
you are running more than one at a time, in that the cache will be
ineffective.  also, if the directory contents change, this will also break.

* removed strip.  breaks osx

* added directory tag so . isn't matched all over the place

* added real cache validation

* fixed build

* this file is copied from optdsk.lib or optcmd.lib

* install to ../HBIOS

* prerequisite verbosity

* diff soft failure and casefn speedup

* added lzsa

* added lzsa

* removed strip. breaks on osx

* added clobber

* added code to handle multiple platform rom builds with rom size override

* added align and 0x55 hex syntax

* default to hd64180

* added N8 capability

* added SBC_std.rom to default build

* added support for binary diff

* diff fixes

* clean, identical build.  font source generator emitted .align.  this does not match the windows build

* Upgrade NZCOM to latest

* Misc. Cleanup

* fixed expression parser bug : ~(1|2) returned 0xfe

* added diff build option

* Update Makefile

Makefile enhancement to better handle ncurses library from Bob Dunlop.

* Update sd.asm

Back out hack for uz80as now that Curt fixed it.

* Misc. Cleanup

* UNA Catchup

UNA support was lacking some of the more recent behavior changes.  This corrects most of it.

* Add github action for building RomWBW

* Bump Pre-release Version

* Update build.yml

Added "make clean" which will remove temporary files without removing final binary outputs.

* Update Makefile

Build all ROM variants by default in Linux/Mac build.

* Update Makefile

* Update Makefile

* Update Makefile

* Update Makefile

* Update Makefile

* Update Makefile

* Update Makefile

* Update Makefile

* Update Makefile

* Update for GitHub Build

Case issue in TASM includes showing up in GitHub build.  This should correct that.

* Added an gitignore files to exclude generated files

* Removed Tunes/clean.cmd and Tunes/ReadMe.txt - as make clean removes them

* Build.sh: marked as executable

chmod +x Build.sh

* Fix to HBIOS/build.sh

When adding files to rom disk, if files were missing, it would error out.

It appears the intent is to skip non-existing files.

Updated to log out correctly for missing files - and continue operation.

* Update Microsoft NASCOM BASIC.docx

Nascom manual, text version by Jan S (full name unknown)

* Fix issue with Apps/Tune not making

If dest directory does not exist, fails to make Apps

* Create ReadMe.txt

* Update Makefile

* Update Build.sh

* Make .gitignores for Tools/unix more specific

* cpmtools Update

Updated cpmtools applications (Windows only).  Removed hack in diskdefs that is no longer required.

* HBIOS Proxy Temp Stack Enhancement

Reuse the bounce buffer area as the temporary stack space required briefly in HBX_INVOKE when transitioning banks.  Increases size of temporary stack space to 64 bytes.

* Update ReadMe.txt

* HBIOS - clean up TMPSTK

* Update hbios.asm

Minor cosmetic changes.

* Build Process Updates

Minor udpates to build process to improve consistency between Windows and Mac/Linux builds.

* Update hbios.asm

Add improved interrupt protection to HBIOS PEEK, POKE, and BNKCPY functions.

* hbios - wrap hbx_bnkcpy

* hbios - adjust hbx_peek hbx_poke guards

* Update hbios.asm

Adjusted used of DI/EI for PEEK and POKE to regain a bit of INTSTK space.  Added code so that HB_INVBNK can be used as a flag indicating if HBIOS is active, $FF is inactive, anything else means active.

* Add HBIOS MuTex

* Initial Nascom basic ecb-vdu graphics

set and reset for 80x25b screen with 256 character mod

* Finalize Pre-release 34

Final support for FreeRTOS

* Update nascom.asm

Optimization, cleanup, tabs and white spaces

* IDE & PPIDE Cleanup

* Clean up

Make version include files common.

* Update Makefile

* Update Makefile

* Build Test

* Build Test

* Build Fixes

* Update nascom.asm

Cleanup

* Update nascom.asm

Optimization

* hbios - temp stack tweak

* Update hbios.asm

Comments on HBX_BUF usage.

* Update nascom.asm

Optimization

* Update nascom.asm

Setup ECB-VDU build option, remove debug code

* Update nascom.asm

Set default build. update initialization

* Update nascom.asm

Make CLS clear vdu screen

* Update nascom.asm

Fixup top screen line not showing

* Add SC131 Support

Also cleaned up some ReadMe files.

* HBIOS SCZ180 - remove mutex special files

* HBIOS SCZ180 - adjust mutex comment

* Misc. Cleanup

Includes some minor improvements to contents in some disk images.

* Delete FAT.COM

Changing case of FAT.COM extension to lowercase.

* Create FAT.com

Completing change of case in extension of FAT.com.

* Update Makefile

Remove ROM variants that just have the HBIOS MUTEX enabled.  Users can easily enable this in a custom build.

* Cleanup

Removed hack from Images Makefile.  Fixed use of DEFSERCFG in various places.

* GitHub CI Updates

Adds automation of build and release assets upon release.

* Prerelease 36

General cleanup

* Build Script Cleanups

* Config File Cleanups

* Update RomWBW Architecture

General refresh for v2.9.2

* Update vdu.asm

Removed a hack in VDU driver that has existed for 8 years.  :-)

* Fix CONSOLE Constant

Rename CIODEV_CONSOLE constant to CIO_CONSOLE because it is a unit code, not a device type code.

Retabify TastyBasic.

* Minor Bug Fixes

- Disk assignment edge case
- CP/M 3 accidental fall thru
- Cosmetic updates

* Update util.z80

* Documentation Cleanup

* Documentation Update

* Documentation Update

* Documentation Updates

* Documentation Updates

* Create Common.inc

* Documentation Updates

* Documentation Updates

* doc - a few random fixes

* Documentation Cleanup

* Fix IM 0 Build Error in ACIA

* Documentation Updates

* Documentation Cleanup

* Remove OSLDR

The OSLDR application was badly broken and almost impossible to fix with new expanded OS support.

* Bug Fixes

- Init RAM disk at boot under CP/M 3
- Fix ACR activation in TUNE

* FD Motor Timeout

- Made FDC motor timeout smaller and more consistent across different speed CPUs
- Added "boot" messaging to RTC

* Cleanup

* Cleanup

- Fix SuperZAP to work under NZCOM and ZPM3
- Finalize standard config files

* Minor Changes

- Slight change to ZAP configuration
- Added ZSDOS.ZRL to NZCOM image

* ZDE Upgrade

- Upgraded ZDE 1.6 -> 1.6a

* Config File Tuning

* Pre-release for Testing

* cfg - mutex consistent config language

* Bump to Version 3.0

* Update SD Card How-To

Thanks David!

* update ReadMe.md

Remove some odd `\`.

* Update ReadMe.txt

* Update ReadMe.md

* Update Generated Doc Files

* Improve XModem Startup

- Extended startup timeout for XM.COM so that it doesn't timeout so quickly while host is selecing a file to send.
- Updated SD Card How-To from David Reese.

* XModem Timing Refinements

* TMS Driver Z180 Improvements

- TMS driver udpated to insert Z180 I/O waitstates internally so other code can run at full speed.
- Updated How-To documents from David.
- Fixed TUNE app to properly restore Z180 I/O waitstates after manipulating them.

* CLRDIR and ZDE updates

- CLRDIR has been updated by Max Scane for CP/M 3 compatibility.
- A minor issue in the preconfigured ZDE VT100 terminal escape sequences was corrected.

* Fix Auto CRT Console Switch on CP/M 3

* Handle lack of RTC better

DSRTC driver now correctly returns an error if there is no RTC present.

* Minor RTC Updates

* Finalize v3.0.1

Cleanup release for v3.0

* New ROMLDR and INTRTC driver

- Refactored romldr.asm
- Added new periodic timer based RTC driver

* CP/M 3 Date Hack

- Hack to allow INTRTC to increment time without destroying the date

* Update romldr.asm

Work around minor Linux build inconsistency

* Update Apps for New Version

* Revert "Update Apps for New Version"

This reverts commit ad80432252.

* Revert "Update romldr.asm"

This reverts commit 4a9825cd57.

* Revert "CP/M 3 Date Hack"

This reverts commit 153b494e61.

* Revert "New ROMLDR and INTRTC driver"

This reverts commit d9bed4563e.

* Start v3.1 Development

* Update FDISK80.COM

Updated FDISK80 to allow reserving up to 256 slices.

* Update sd.asm

For Z180 CSIO, ensure that xmit is finished, before asserting CS for next transaction.

* Add RC2014 UART, Improve SD protocol fix

- RC2014 and related platforms will autodetect a UART at 0xA0 and 0xA8
- Ensure that CS fully brackets all SD I/O

* ROMLDR Improvements

.com files can now be started from CP/M and size of .com files has been reduced so they always fit.

* Update commit.yml

Run commit build in all branches

* Update commit.yml

Run commit build for master and dev branches

* Improved clock driver auto-detect/fallback

* SIO driver now CTC aware

The SIO driver can now use a CTC (if available) to provide much more flexible baud rate programming.

* CTC driver fine tuning

* Update xmdm125.asm

Fixed a small issue in core XM125 code that caused a file write error message to not be displayed when it should be.

* CF Card compatibility improvement

Older CF Cards did not reset IDE registers to defaults values when reset.  Implemented a work around.

* Update ACIA detection

ACIA should no longer be detected if there is also a UART module in the system.

* Handle CTC anomaly

Small update to accommodate CTC behavior that occurs when the CTC trigger is more than half the CTC clock.

* Update acia.asm

Updated ACIA detection to use primary ACIA port instead of phantom port.

* Update acia.asm

Fix bug in ACIA detection.

Thanks Alan!

* MacOS Build Improvement

Build script updated to improve compatibility with MacOS.

Credit to Fredrik Axtelius for this.

* HBIOS Makefile - use env vars for target

Allow build ROM targets to be restricted to just one platform thru use of ENV vars:

ROM_PLATFORM - if defined to a known platform, only this platform is build - defaults to std config
ROM_CONFIG - sets the desired platform config - defaults to std

if the above ENVs are not defined, builds all ROMs

* Added some more gitignores

* Whitespace changes (crlf)

* HBIOS: Force the assembly to fail for vdu drivers if function table count is not correct

* Whitespace: trailing whitespaces

* makefile: updated some make scripts to use  when calling subdir makefiles

* linux build: update to Build.sh fix for some platforms

The initialization of the Rom dat file used the pipe (|) operator to build an initial empty file.

But the pipe operator | may sometimes return a non-zero exit code for some linux platforms, if the
the streams are closed before dd has fully processed the stream.

This issue occured on a travis linux ubuntu image.

Solution was to change to redirection.

* Bump version

* Enhance CTC periodic timer

Add ability to use TIMER mode in CTC driver to generate priodic interrupts.

* HBIOS: Added support for sound drivers

New sound driver support with initial support for the SN76489 chip

New build configuration entry:
* SN76489ENABLE

Ports are currently locked in with:
* SN76489_PORT_LEFT       .EQU    $FC     ; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
* SN76489_PORT_RIGHT      .EQU    $F8     ; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)

* Miscellaneous Cleanup

No functional changes.

Co-authored-by: curt mayer <curt@zen-room.org>
Co-authored-by: Wayne Warthen <wwarthen@gmail.com>
Co-authored-by: ed <linux@maidavale.org>
Co-authored-by: Dean Netherton <dnetherton@dius.com.au>
Co-authored-by: ed <ed@maidavale.org>
Co-authored-by: Phillip Stevens <phillip.stevens@gmail.com>
Co-authored-by: Dean Netherton <dean.netherton@gmail.com>
2020-04-24 06:17:22 +08:00

464 lines
10 KiB
Z80 Assembly
Raw Blame History

;:::::::::::::::::::::::::::::::::::::::*****************************
; HBIOS - HBios Interface Routines ***** Hardware-Specific *****
; *****************************
;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;
HB_DEFBNK EQU BID_USR ; Default bank number
;
; LOCATION OF DISPATCH ENTRY IN HBIOS BANK
;
HB_DISPATCH EQU 403H
HB_STACK EQU 500H
;
; PLATFORM SPECIFIC CONSTANTS
;
IF N8VEM OR ZETA OR ZETA2
SBC_BASE EQU 60H
ENDIF
IF N8VEM OR ZETA
MPCL_RAM EQU SBC_BASE + 18H ; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
MPCL_ROM EQU SBC_BASE + 1CH ; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
ENDIF
IF ZETA2
MPGSEL_0 EQU SBC_BASE + 18H
MPGSEL_1 EQU SBC_BASE + 19H
MPGSEL_2 EQU SBC_BASE + 1AH
MPGSEL_3 EQU SBC_BASE + 1BH
MPGENA EQU SBC_BASE + 1CH
ENDIF
IF N8
N8_BASE EQU 80H ; BASE I/O ADDRESS BOARD PERIPHERALS (NON-CPU)
ACR EQU N8_BASE + 14H ; AUXILLARY CONTROL REGISTER
DEFACR EQU 1BH ; DEFAULT VALUE FOR ACR
CPU_BBR EQU 40H + 39H
ENDIF
IF MK4
CPU_BBR EQU 40H + 39H
ENDIF
CSEG
IF INTPXY
DB 0 ; Prevents link error in BPBUILD
HB_XFC EQU 0FFE0H
HB_XFCIMG EQU $
.PHASE HB_XFC
HB_CURBNK DB 0
HB_INVBNK DB 0
HB_SRCADR DW 0
HB_SRCBNK DB 0
HB_DSTADR DW 0
HB_DSTBNK DB 0
HB_CPYLEN DW 0
DB 0,0,0,0,0,0
HB_INVOKE JP HBX_INVOKE
HB_BNKSEL JP HBX_BNKSEL
HB_BNKCPY JP HBX_BNKCPY
HB_BNKCALL JP 0 ; HBX_BNKCALL (NOT IMPLEMENTED)
DB 0,0 ; RESERVED
HB_IDENT DW 0 ; HBX_IDENT
.DEPHASE
HB_XFCSIZ EQU $ - HB_XFCIMG
ELSE
HBX_INVOKE EQU 0FFF0H
HBX_BNKSEL EQU 0FFF3H
HBX_BNKCPY EQU 0FFF6H
HBX_BNKCALL EQU 0FFF9H
HB_CURBNK EQU 0FFE0H
HB_INVBNK EQU 0FFE1H
HB_SRCADR EQU 0FFE2H
HB_SRCBNK EQU 0FFE4H
HB_DSTADR EQU 0FFE5H
HB_DSTBNK EQU 0FFE7H
HB_CPYLEN EQU 0FFE8H
ENDIF
;
;==================================================================================================
; HBIOS INTERFACE
;==================================================================================================
;
HBX_INIT:
IF INTPXY
; Copy HB_XFCIMG to target location
LD HL,HB_XFCIMG
LD DE,HB_XFC ; point to HBIOS comm block
LD BC,HB_XFCSIZ
LDIR
; Setup RST 08 vector
LD A,0C3H ; $C3 = JP
LD (08H),A
LD HL,HBX_INVOKE
LD (09H),HL
ENDIF
; Init HB data fields
LD A,BID_USR
LD (HB_CURBNK),A
LD (HB_SRCBNK),A
LD (HB_DSTBNK),A
IF BANKED
; Copy vectors from TPA page zero to SYS page zero
LD BC,(TPABNK) ; C := TPABNK, B := SYSBNK
CALL XMOVE ; Set source/dest banks for copy
LD HL,0 ; Source address is zero
LD DE,0 ; Destination address is zero
LD BC,40H ; Copy 40H bytes
CALL MOVE ; Do it
LD A,(TPABNK) ; Set all Bank regs to TPA
ENDIF
; CSEG
;ORG_CSEG EQU $
; DSEG
;ORG_DSEG EQU $
IF BANKED
COMMON /BANK2/
ORG_BANK2 EQU $
COMMON /B2RAM/
ORG_B2RAM EQU $
ENDIF
CSEG
CALL NEWLINE2
LD DE,HB_STR_TAG
CALL WRITESTR
IF INTPXY
LD DE,HB_STR_INTPXY
ELSE
LD DE,HB_STR_EXTPXY
ENDIF
CALL WRITESTR
CALL NEWLINE
LD DE,HB_STR_CSEG
CALL WRITESTR
LD BC,BIOSJT
CALL PRTHEXWORD
LD DE,HB_STR_DSEG
CALL WRITESTR
LD BC,CBOOT
CALL PRTHEXWORD
IF BANKED
LD DE,HB_STR_BANK2
CALL WRITESTR
LD BC,ROMJT
CALL PRTHEXWORD
LD DE,HB_STR_B2RAM
CALL WRITESTR
LD BC,CBOOT0
CALL PRTHEXWORD
LD DE,HB_STR_RESVD
CALL WRITESTR
LD BC,ALV$50
CALL PRTHEXWORD
ENDIF
CALL NEWLINE
RET
HB_STR_TAG DB "HBIOS: $"
HB_STR_INTPXY DB "Internal Proxy$"
HB_STR_EXTPXY DB "External Proxy$"
HB_STR_CSEG DB "CSEG=$"
HB_STR_DSEG DB ", DSEG=$"
HB_STR_BANK2 DB ", BANK2=$"
HB_STR_B2RAM DB ", B2RAM=$"
HB_STR_RESVD DB ", RESVD=$"
HBX_XCOPY:
LD A,C
LD (HB_SRCBNK),A
LD A,B
LD (HB_DSTBNK),A
RET
HBX_COPY:
JP HBX_BNKCPY
IF INTPXY
;==================================================================================================
; SELECT MEMORY BANK FOR LOWER 32K
;==================================================================================================
HBX_BNKSEL:
LD (HB_CURBNK),A
IF N8VEM OR ZETA
OUT (MPCL_ROM),A
OUT (MPCL_RAM),A
RET
ENDIF
IF ZETA2
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE
RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT
ADD A,16 ; ADD 16 x 32K - RAM STARTS FROM 512K
;
HBX_ROM:
RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
OUT (MPGSEL_0),A ; BANK_0: 0K - 16K
INC A ;
OUT (MPGSEL_1),A ; BANK_1: 16K - 32K
RET
ENDIF
IF N8
BIT 7,A
JR Z,HBX_ROM
;
HBX_RAM:
RES 7,A
RLCA
RLCA
RLCA
OUT0 (CPU_BBR),A
LD A,DEFACR | 80H
OUT0 (ACR),A
RET
;
HBX_ROM:
OUT0 (RMAP),A
XOR A
OUT0 (CPU_BBR),A
LD A,DEFACR
OUT0 (ACR),A
RET
ENDIF
IF MK4
RLCA
JR NC,HBX_BNKSEL1
XOR 00100001B
HBX_BNKSEL1:
RLCA
RLCA
OUT0 (CPU_BBR),A
RET
ENDIF
;==================================================================================================
; INTERBANK MEMORY COPY
;==================================================================================================
HBX_BNKCPY:
HB_DI ; NOTE: ONLY REQUIRED WHEN USING IM 1
LD (HBX_STKSAV),SP
LD SP,HBX_TMPSTK
LD A,(HB_CURBNK) ; GET CURRENT BANK
PUSH AF ; AND SAVE TO RESTORE LATER
PUSH BC ; CUR LEN -> (SP)
;
HBX_BC_LOOP:
EX (SP),HL ; HL := CUR LEN, (SP) := CUR SRC
LD BC,HBX_BUFSIZ ; SET BC TO BOUNCE BUFFER SIZE
OR A ; CLEAR CARRY FLAG
SBC HL,BC ; CUR LEN := CUR LEN - BBUF SIZE
JR C,HBX_BC_LAST ; END GAME, LESS THAN BBUF BYTES LEFT
EX (SP),HL ; HL := CUR SRC, (SP) := REM LEN
CALL HBX_BC_ITER ; DO A FULL BBUF SIZE CHUNK
JR HBX_BC_LOOP ; AND REPEAT TILL DONE
;
HBX_BC_LAST:
; HL IS BETWEEN -(BBUF SIZE) AND -1, BC = BBUF SIZE
OR A ; CLEAR CARRY
ADC HL,BC ; HL := REM LEN (0 - 127)
EX (SP),HL ; HL := CUR SRC, (SP) := REM LEN
POP BC ; BC := REM LEN
CALL NZ,HBX_BC_ITER ; DO FINAL CHUNK, BUT ONLY IF NOT ZERO BYTES
POP AF ; RECOVER ORIGINAL BANK
CALL HBX_BNKSEL ; SWITCH TO CURRENT BANK AND EXIT
LD SP,(HBX_STKSAV)
HB_EI ; NOTE: ONLY REQUIRED WHEN USING IM 1
RET
;
HBX_BC_ITER:
; HL = SRC ADR, DE = DEST ADR, BC = LEN
PUSH BC ; SAVE COPY LEN
PUSH DE ; FINAL DEST ON STACK
LD DE,HBX_BUF ; SET DEST TO BUF
LD A,(HB_SRCBNK) ; GET SOURCE BANK
CALL HBX_BNKSEL ; SWITCH TO SOURCE BANK
LDIR ; HL -> BUF (DE), BC BYTES, HL UPDATED SRC ADR
POP DE ; DE := FINAL DEST
POP BC ; GET LEN BACK IN BC
PUSH HL ; SAVE UPDATED SRC ADR
LD HL,HBX_BUF ; SET SRC ADR TO BUF
LD A,(HB_DSTBNK) ; GET DEST BANK
CALL HBX_BNKSEL ; SWITCH TO DEST BANK
LDIR ; BUF (HL) -> DE, BC BYTES, DE UPDATED DEST ADR
POP HL ; RECOVER UPDATED SRC ADR
; HL = UPD SRC, DE = UPD DEST, BC = 0
RET
;==================================================================================================
; ENTRY POINT FOR BIOS FUNCTIONS (TARGET OF RST 08)
;==================================================================================================
HBX_INVOKE:
LD (HBX_INVSP),SP ; SAVE ORIGINAL STACK FRAME
LD A,(HB_CURBNK) ; GET CURRENT BANK
LD (HB_INVBNK),A ; SAVE INVOCATION BANK
; HB_DI
LD SP,HBX_TMPSTK ; USE SMALL TEMP STACK FRAME IN HI MEM FOR BANK SWITCH
LD A,BID_HB ; HBIOS BANK
CALL HBX_BNKSEL ; SELECT IT
LD SP,HB_STACK ; NOW USE FULL HBIOS STACK IN HBIOS BANK
; HB_EI
CALL HB_DISPATCH ; CALL HBIOS FUNCTION DISPATCHER
; HB_DI
LD SP,HBX_TMPSTK ; USE SMALL TEMP STACK FRAME IN HI MEM FOR BANK SWITCH
PUSH AF ; SAVE AF (FUNCTION RETURN)
LD A,(HB_INVBNK) ; LOAD ORIGINAL BANK
CALL HBX_BNKSEL ; SELECT IT
POP AF ; RESTORE AF
LD SP,0 ; RESTORE ORIGINAL STACK FRAME
HBX_INVSP EQU $ - 2
; HB_EI
RET ; RETURN TO CALLER
ENDIF
;==================================================================================================
; LD A,(C:HL)
;==================================================================================================
HBX_FRGETB:
LD (HBX_STKSAV),SP ; Save current stack
LD SP,HBX_TMPSTK ; Activate our private stack
LD A,(HB_CURBNK) ; Get current bank
LD (HBX_BNKSAV),A ; Save current bank
PUSH BC
LD A,C
HB_DI
CALL HBX_BNKSEL
LD C,(HL)
LD A,(HBX_BNKSAV)
CALL HBX_BNKSEL
HB_EI
LD A,C
POP BC
LD SP,(HBX_STKSAV) ; RESTORE ORIGINAL STACK FRAME
RET
;==================================================================================================
; LD DE,(C:HL)
;==================================================================================================
HBX_FRGETW:
LD (HBX_STKSAV),SP ; Save current stack
LD SP,HBX_TMPSTK ; Activate our private stack
LD A,(HB_CURBNK) ; Get current bank
LD (HBX_BNKSAV),A ; Save current bank
LD A,C
HB_DI
CALL HBX_BNKSEL
LD E,(HL)
INC HL
LD D,(HL)
DEC HL
LD A,(HBX_BNKSAV)
CALL HBX_BNKSEL
HB_EI
LD SP,(HBX_STKSAV) ; RESTORE ORIGINAL STACK FRAME
RET
;==================================================================================================
; LD (C:HL),A
;==================================================================================================
HBX_FRPUTB:
LD (HBX_STKSAV),SP ; Save current stack
LD SP,HBX_TMPSTK ; Activate our private stack
PUSH AF
LD A,(HB_CURBNK) ; Get current bank
LD (HBX_BNKSAV),A ; Save current bank
POP AF
PUSH BC
LD B,A
LD A,C
HB_DI
CALL HBX_BNKSEL
LD (HL),B
LD A,(HBX_BNKSAV)
CALL HBX_BNKSEL
HB_EI
POP BC
LD SP,(HBX_STKSAV) ; RESTORE ORIGINAL STACK FRAME
RET
;==================================================================================================
; LD (C:HL),DE
;==================================================================================================
HBX_FRPUTW:
LD (HBX_STKSAV),SP ; Save current stack
LD SP,HBX_TMPSTK ; Activate our private stack
LD A,(HB_CURBNK) ; Get current bank
LD (HBX_BNKSAV),A ; Save current bank
LD A,C
HB_DI
CALL HBX_BNKSEL
LD (HL),E
INC HL
LD (HL),D
DEC HL
LD A,(HBX_BNKSAV)
CALL HBX_BNKSEL
HB_EI
LD SP,(HBX_STKSAV) ; RESTORE ORIGINAL STACK FRAME
RET
;==================================================================================================
; PRIVATE DATA
;==================================================================================================
DSEG
HB_DSKBUF DEFW 0 ; Address of physical disk buffer in HBIOS bank
HBX_BNKSAV DEFB 0 ; Saved bank id during HBIOS calls
HBX_STKSAV DEFW 0 ; Saved stack pointer during HBIOS calls
DEFS 32 ; Private stack for HBIOS
HBX_TMPSTK EQU $ ; Top of private stack
IF INTPXY
HBX_BUFSIZ EQU 40H
HBX_BUF DEFS HBX_BUFSIZ ; Interbank copy buffer
ENDIF
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