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507 lines
27 KiB
507 lines
27 KiB
;
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;==================================================================================================
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; ROMWBW GLOBAL MASTER CONFIGURATION FILE
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;==================================================================================================
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;
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; THIS FILE IS THE GLOBAL MASTER CONFIGURATION FILE FOR THE ROMWBW
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; BUILD PROCESS. IT DEFINES ALL POSSIBLE CONFIGURATION SETTINGS
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; AVAILABLE WITHIN ROMWBW. MANY SETTINGS WILL NOT BE APPLICABLE TO
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; ALL OF THE DIFFERENT ROMWBW PLATFORMS.
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;
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; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE
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; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A
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; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
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;
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; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
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;
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; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
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; |
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; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
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; |
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; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
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; |
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; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
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;
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; EACH FILE BELOW THIS TOP MASTER CONFIGURATION FILE INHERITS THE
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; CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY OVERRIDE THESE
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; SETTINGS AS DESIRED.
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;
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; OTHER THAN THIS TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
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; FILE. THE TOP TWO FILES SHOULD NOT BE MODIFIED. TO CUSTOMIZE YOUR
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; BUILD SETTINGS, YOU SHOULD MODIFY THE DEFAULT BUILD SETTINGS
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; (Config/<platform>_std.asm) OR PREFERABLY CREATE AN OPTIONAL CUSTOM
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; USER SETTINGS FILE THAT INCLUDES THE DEFAULT BUILD SETTINGS FILE (SEE
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; EXAMPLE Config/SBC_custom.asm).
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;
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; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
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; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
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; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
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;
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; *** NOTE: THIS FILE USES ".EQU" TO DEFINE ALL SETTINGS. ALL OTHER
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; CONFIGURATION FILES BELOW THIS FILE MUST USE ".SET" TO OVERRIDE
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; SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT TO USE ".EQU"
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; TO REDEFINE A PREVIOUS DEFINITION.
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;
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#DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
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#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
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#DEFINE DEFSERCFG SER_9600_8N1 ; DEFAULT SERIAL CONFIGURATION
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;
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#INCLUDE "hbios.inc"
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;
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PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
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CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
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BIOS .EQU BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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USELZSA2 .EQU FALSE ; ENABLE FONT COMPRESSION
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
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;
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
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BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
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BOOT_PRETTY .EQU FALSE ; BOOT WITH PRETTY PLATFORM NAME
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BT_REC_TYPE .EQU BT_REC_NONE ; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI]
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AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
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STRICTPART .EQU TRUE ; ENFORCE STRICT PARTITION TABLE VALIDATION
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;
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CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
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CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
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CPUOSC .EQU 1000000 ; CPU OSC FREQ IN MHZ
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INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
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;
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
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APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
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MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512]
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RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
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MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
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MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
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MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
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MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
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;
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Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
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Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
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Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
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Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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Z180_TIMER .EQU FALSE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
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;
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Z280_MEMLOWAIT .EQU 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
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Z280_MEMHIWAIT .EQU 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
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Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3)
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Z280_TIMER .EQU FALSE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
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;
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N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
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N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
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N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR
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N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
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N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
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N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
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;
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RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
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RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR
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RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
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RPH_DEFACR .EQU $00 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
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;
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MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
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MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
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MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR
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MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR
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;
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RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
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;
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
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;
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
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CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
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CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
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CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
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CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
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CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
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CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
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CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY
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;
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PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
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PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
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PCFCLK .EQU PCFCLK_12 ; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12]
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PCFTRNS .EQU PCFTRNS_90 ; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15]
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;
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EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
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;
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SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
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SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
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;
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WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
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WDOGIO .EQU $6F ; WATCHDOG REGISTER ADR
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;
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FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
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FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
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FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
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FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
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FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
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FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
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FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
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;
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DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
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;
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LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
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LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
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LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
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LEDDISKIO .EQU FALSE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
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;
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DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
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DSKYDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
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ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
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ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
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PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
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PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
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PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
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H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
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LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
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LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
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GM7303ENABLE .EQU FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD
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GM7303BASE .EQU $30 ; BASE ADDRESS FOR GM3703 BOARD
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;
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BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
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SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE
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CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
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VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
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ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
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KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
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KBDINTS .EQU FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
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;
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DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
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DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
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;
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DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
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DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
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;
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BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
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BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
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;
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INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
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;
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RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
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;
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HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
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SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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;
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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PCRTCENABLE .EQU FALSE ; PCRTC: DISABLE DS12885 etc. RTC
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PCRTC_BASE .EQU $C0 ; Default port for PCRTC, like DSRTC.
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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SSERDATA .EQU $FF ; SSER: DATA PORT
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SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
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SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED
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SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK
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SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
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;
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DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
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DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
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DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
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DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
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DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
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DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
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DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
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;
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UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
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UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
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UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
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UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
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UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
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UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
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UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
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UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
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UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
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UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
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UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
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UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
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UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
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UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
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UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
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UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
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UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
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UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
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UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
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UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
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UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
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;
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ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
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Z2UOSC .EQU 1843200 ; Z2U: OSC FREQUENCY IN MHZ
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Z2UOSCEXT .EQU TRUE ; Z2U: USE EXTERNAL OSCILLATOR
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Z2U0BASE .EQU $10 ; Z2U 0: BASE I/O ADDRESS
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Z2U0CFG .EQU DEFSERCFG ; Z2U 0: SERIAL LINE CONFIG
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Z2U0HFC .EQU FALSE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL
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;
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ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
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ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
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ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
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ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ
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ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
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ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
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ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
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ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ
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ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
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ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
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;
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SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
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SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
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SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
|
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
|
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
|
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
|
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
|
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
|
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
|
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
|
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
|
;
|
|
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
|
;
|
|
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
|
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
|
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
|
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
|
CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
|
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
|
GDCMODE .EQU GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
|
|
GDCMON .EQU GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
|
|
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
|
TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
|
|
TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
|
|
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
|
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
|
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
|
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
|
SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
|
|
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
|
|
FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
|
|
XOSENABLE .EQU FALSE ; XOSERA: ENABLE XOSERA VIDEO DRIVERS (XOSERA.ASM)
|
|
XOS_BASE .EQU $20 ; XOSERA: I/O BASE ADDRESS (REQUIRES 32 BYTES)
|
|
XOSSIZ .EQU V80X30 ; XOSERA: DISPLAY FORMAT [V80X30|V80X60]
|
|
;
|
|
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
|
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
|
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
|
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
|
;
|
|
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
|
FDMODE .EQU FDMODE_NONE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
|
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
|
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
|
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
|
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
|
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
|
;
|
|
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
|
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
|
;
|
|
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
|
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
|
IDE0MODE .EQU IDEMODE_NONE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
|
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
|
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
|
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
|
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
|
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
|
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
|
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
|
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
|
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
|
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
|
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
|
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
|
|
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
|
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
|
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
|
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
|
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
|
;
|
|
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
|
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
|
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
|
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
|
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
|
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
|
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
|
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
|
PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
|
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
|
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
|
;
|
|
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
|
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
|
|
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
|
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
|
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
|
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
|
;
|
|
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
|
|
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
|
|
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS
|
|
CH0USBENABLE .EQU FALSE ; CH 0: ENABLE USB DISK
|
|
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK
|
|
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS
|
|
CH1USBENABLE .EQU FALSE ; CH 1: ENABLE USB DISK
|
|
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
|
|
;
|
|
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
|
PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
|
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
|
;
|
|
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
|
PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS
|
|
PPPSDENABLE .EQU FALSE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
|
|
PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
PPPCONENABLE .EQU FALSE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
|
|
;
|
|
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
|
|
ESPCONENABLE .EQU FALSE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
|
|
;
|
|
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
|
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
;
|
|
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
|
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
|
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
|
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
|
;
|
|
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
|
LPTMODE .EQU LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
|
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
|
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR
|
|
LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR
|
|
;
|
|
PPAENABLE .EQU FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM)
|
|
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
|
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
PPAMODE .EQU PPAMODE_NONE ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
|
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
|
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
|
;
|
|
IMMENABLE .EQU FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM)
|
|
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
|
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
IMMMODE .EQU IMMMODE_NONE ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
|
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
|
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
|
;
|
|
SYQENABLE .EQU FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
|
|
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
|
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
|
SYQMODE .EQU IMMMODE_NONE ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
|
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
|
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
|
;
|
|
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
|
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
|
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
|
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
|
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
|
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
|
;
|
|
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
|
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
|
|
;
|
|
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
|
SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
|
|
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
|
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
|
SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
|
|
;
|
|
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
|
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
|
AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
|
|
AY_FORCE .EQU FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
|
|
;
|
|
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
|
;
|
|
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
|
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
|
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
|
|
;
|
|
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
|
|
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
|
|
;
|
|
; EZ80 SETTINGS
|
|
;
|
|
EZ80TMR_NONE .EQU 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS
|
|
EZ80TMR_INT .EQU 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS
|
|
EZ80TMR_FIRM .EQU 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED)
|
|
;
|
|
EZ80UARTENABLE .EQU FALSE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
|
|
EZ80RTCENABLE .EQU FALSE ; EZ80 ON CHIP RTC
|
|
EZ80TIMER .EQU EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
|
|
EZ80IOBASE .EQU $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
|
|
;
|
|
; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
|
|
EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
|
|
EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
|
|
EZ80_MEM_MIN_BC .SET 1 ; MINIMUM BUS CYCLES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
|
|
;
|
|
; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
|
|
EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
|
|
EZ80_IO_MIN_NS .SET 250 ; CALCULATE AT BOOT TIME THE REQUIRED B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
|
|
EZ80_IO_MIN_BC .SET 4 ; MINIMUM BUS CYCLES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
|
|
;
|
|
; APPLY BUS CYCLES OR CALCULATE CYCLES BASED ON DESIRED PERIOD
|
|
EZ80_WSMD_TYP .SET EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES]
|
|
;
|
|
; BUS TIMING FOR ON CHIP ROM
|
|
;
|
|
EZ80_FLSH_WS .SET 1 ; WAIT STATES FOR ON CHIP FLASH (0-7)
|
|
EZ80_FLSH_MIN_NS .SET 60 ; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
|
|
EZ80_FWSMD_TYP .SET EZ80WSMD_CALC ; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)
|
|
|
|
CHNATIVEENABLE .EQU FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER
|
|
CHSCSIENABLE .EQU FALSE ; CH376: ENABLE CH376 NATIVE MASS STORAGE DEVICES (REQUIRES CHNATIVEENABLE)
|
|
CHUFIENABLE .EQU FALSE ; CH376: ENABLE CH376 NATIVE UFI FLOPPY DISK DEVICES (REQUIRES CHNATIVEENABLE)
|
|
CHNATIVEFORCE .EQU FALSE ; CH376: DISABLE AUTO-DETECTION OF MODULE - ASSUME ITS INSTALLED (REQUIRES CHNATIVEENABLE)
|
|
CHNATIVEEZ80 .EQU FALSE ; CH376: DELEGATE USB DRIVERS TO EZ80'S FIRMWARE
|
|
|