mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
b75153d263
Create an equate for changing baud rate through custom config rather than the driver. Add recovermode mode option to use Ring indicator line.
631 lines
17 KiB
NASM
631 lines
17 KiB
NASM
;
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;==================================================================================================
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; UART DRIVER (SERIAL PORT)
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;==================================================================================================
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;
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; SETUP PARAMETER WORD:
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; +-------+---+-------------------+ +---+---+-----------+---+-------+
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; | |RTS| ENCODED BAUD RATE | |DTR|XON| PARITY |STP| 8/7/6 |
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; +-------+---+---+---------------+ ----+---+-----------+---+-------+
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; F E D C B A 9 8 7 6 5 4 3 2 1 0
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; -- MSB (D REGISTER) -- -- LSB (E REGISTER) --
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;
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; UART CONFIGURATION REGISTERS:
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; +-------+---+-------------------+ +---+---+-----------+---+-------+
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; | 0 0 |AFE|LP OT2 OT1 RTS DTR| |DLB|BRK|STK EPS PEN|STB| WLS |
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; +-------+---+-------------------+ +---+---+-----------+---+-------+
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; F E D C B A 9 8 7 6 5 4 3 2 1 0
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; -- MCR -- -- LCR --
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;
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;
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UART_DEBUG .EQU FALSE
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;
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UART_NONE .EQU 0 ; UNKNOWN OR NOT PRESENT
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UART_8250 .EQU 1
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UART_16450 .EQU 2
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UART_16550 .EQU 3
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UART_16550A .EQU 4
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UART_16550C .EQU 5
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UART_16650 .EQU 6
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UART_16750 .EQU 7
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UART_16850 .EQU 8
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;
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UART_RBR .EQU 0 ; DLAB=0: RCVR BUFFER REG (READ)
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UART_THR .EQU 0 ; DLAB=0: XMIT HOLDING REG (WRITE)
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UART_IER .EQU 1 ; DLAB=0: INT ENABLE REG (READ)
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UART_IIR .EQU 2 ; INT IDENT REGISTER (READ)
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UART_FCR .EQU 2 ; FIFO CONTROL REG (WRITE)
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UART_LCR .EQU 3 ; LINE CONTROL REG (READ/WRITE)
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UART_MCR .EQU 4 ; MODEM CONTROL REG (READ/WRITE)
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UART_LSR .EQU 5 ; LINE STATUS REG (READ)
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UART_MSR .EQU 6 ; MODEM STATUS REG (READ)
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UART_SCR .EQU 7 ; SCRATCH REGISTER (READ/WRITE)
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UART_DLL .EQU 0 ; DLAB=1: DIVISOR LATCH (LS) (READ/WRITE)
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UART_DLM .EQU 1 ; DLAB=1: DIVISOR LATCH (MS) (READ/WRITE)
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UART_EFR .EQU 2 ; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE)
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;;
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;UART_FIFO .EQU 0 ; FIFO ENABLE BIT
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;UART_AFC .EQU 1 ; AUTO FLOW CONTROL ENABLE BIT
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;
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#DEFINE UART_INP(RID) CALL UART_INP_IMP \ .DB RID
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#DEFINE UART_OUTP(RID) CALL UART_OUTP_IMP \ .DB RID
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;
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;
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;
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UART_PREINIT:
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;
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; INIT UART4 BOARD CONFIG REGISTER (NO HARM IF IT IS NOT THERE)
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;
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LD A,$80 ; SELECT 7.3728MHZ OSC & LOCK CONFIG REGISTER
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OUT ($CF),A ; DO IT
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;
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; SETUP THE DISPATCH TABLE ENTRIES
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;
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LD B,UART_CNT ; LOOP CONTROL
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LD C,0 ; PHYSICAL UNIT INDEX
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XOR A ; ZERO TO ACCUM
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LD (UART_DEV),A ; CURRENT DEVICE NUMBER
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UART_PREINIT0:
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PUSH BC ; SAVE LOOP CONTROL
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LD A,C ; PHYSICAL UNIT TO A
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RLCA ; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES)
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RLCA ; ...
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RLCA ; ... TO GET OFFSET INTO CFG TABLE
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LD HL,UART_CFG ; POINT TO START OF CFG TABLE
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CALL ADDHLA ; HL := ENTRY ADDRESS
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PUSH HL ; SAVE IT
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PUSH HL ; COPY CFG DATA PTR
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POP IY ; ... TO IY
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CALL UART_INITUNIT ; HAND OFF TO GENERIC INIT CODE
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POP DE ; GET ENTRY ADDRESS BACK, BUT PUT IN DE
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POP BC ; RESTORE LOOP CONTROL
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;
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LD A,(IY + 1) ; GET THE UART TYPE DETECTED
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OR A ; SET FLAGS
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JR Z,UART_PREINIT2 ; SKIP IT IF NOTHING FOUND
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;
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PUSH BC ; SAVE LOOP CONTROL
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LD BC,UART_FNTBL ; BC := FUNCTION TABLE ADDRESS
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CALL NZ,CIO_ADDENT ; ADD ENTRY IF UART FOUND, BC:DE
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POP BC ; RESTORE LOOP CONTROL
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;
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UART_PREINIT2:
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INC C ; NEXT PHYSICAL UNIT
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DJNZ UART_PREINIT0 ; LOOP UNTIL DONE
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XOR A ; SIGNAL SUCCESS
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RET ; AND RETURN
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;
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; UART INITIALIZATION ROUTINE
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;
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UART_INITUNIT:
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; DETECT THE UART TYPE
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CALL UART_DETECT ; DETERMINE UART TYPE
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LD (IY + 1),A ; ALSO SAVE IN CONFIG TABLE
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OR A ; SET FLAGS
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RET Z ; ABORT IF NOTHING THERE
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; UPDATE WORKING UART DEVICE NUM
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LD HL,UART_DEV ; POINT TO CURRENT UART DEVICE NUM
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LD A,(HL) ; PUT IN ACCUM
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INC (HL) ; INCREMENT IT (FOR NEXT LOOP)
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LD (IY),A ; UDPATE UNIT NUM
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; SET DEFAULT CONFIG
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LD DE,-1 ; LEAVE CONFIG ALONE
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JP UART_INITDEV ; IMPLEMENT IT AND RETURN
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;
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;
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;
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UART_INIT:
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LD B,UART_CNT ; COUNT OF POSSIBLE UART UNITS
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LD C,0 ; INDEX INTO UART CONFIG TABLE
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UART_INIT1:
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PUSH BC ; SAVE LOOP CONTROL
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LD A,C ; PHYSICAL UNIT TO A
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RLCA ; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES)
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RLCA ; ...
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RLCA ; ... TO GET OFFSET INTO CFG TABLE
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LD HL,UART_CFG ; POINT TO START OF CFG TABLE
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CALL ADDHLA ; HL := ENTRY ADDRESS
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PUSH HL ; COPY CFG DATA PTR
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POP IY ; ... TO IY
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LD A,(IY + 1) ; GET UART TYPE
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OR A ; SET FLAGS
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CALL NZ,UART_PRTCFG ; PRINT IF NOT ZERO
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POP BC ; RESTORE LOOP CONTROL
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INC C ; NEXT UNIT
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DJNZ UART_INIT1 ; LOOP TILL DONE
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;
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XOR A ; SIGNAL SUCCESS
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RET ; DONE
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;
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; DRIVER FUNCTION TABLE
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;
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UART_FNTBL:
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.DW UART_IN
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.DW UART_OUT
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.DW UART_IST
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.DW UART_OST
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.DW UART_INITDEV
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.DW UART_QUERY
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.DW UART_DEVICE
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#IF (($ - UART_FNTBL) != (CIO_FNCNT * 2))
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.ECHO "*** INVALID UART FUNCTION TABLE ***\n"
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#ENDIF
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;
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;
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;
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UART_IN:
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CALL UART_IST ; RECEIVED CHAR READY?
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JR Z,UART_IN ; LOOP IF NOT
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LD C,(IY + 2) ; C := BASE UART PORT (WHICH IS ALSO RBR REG)
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IN E,(C) ; CHAR READ TO E
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XOR A ; SIGNAL SUCCESS
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RET ; AND DONE
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;
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;
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;
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UART_OUT:
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CALL UART_OST ; READY FOR CHAR?
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JR Z,UART_OUT ; LOOP IF NOT
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LD C,(IY + 2) ; C := BASE UART PORT (WHICH IS ALSO THR REG)
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OUT (C),E ; SEND CHAR FROM E
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XOR A ; SIGNAL SUCCESS
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RET
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;
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;
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;
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UART_IST:
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LD C,(IY + 3) ; C := LINE STATUS REG (LSR)
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IN A,(C) ; GET STATUS
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AND $01 ; ISOLATE BIT 0 (RECEIVE DATA READY)
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JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING
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XOR A ; ZERO ACCUM
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INC A ; ACCUM := 1 TO SIGNAL 1 CHAR WAITING
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RET ; DONE
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;
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;
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;
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UART_OST:
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LD C,(IY + 3) ; C := LINE STATUS REG (LSR)
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IN A,(C) ; GET STATUS
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AND $20 ; ISOLATE BIT 5 ()
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JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING
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XOR A ; ZERO ACCUM
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INC A ; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION
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RET ; DONE
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;
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;
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;
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UART_INITDEV:
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; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
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LD A,D ; TEST DE FOR
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AND E ; ... VALUE OF -1
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INC A ; ... SO Z SET IF -1
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JR NZ,UART_INITDEV1 ; IF DE == -1, REINIT CURRENT CONFIG
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;
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; LOAD EXISTING CONFIG TO REINIT
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LD E,(IY + 4) ; LOW BYTE
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LD D,(IY + 5) ; HIGH BYTE
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;
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UART_INITDEV1:
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; DETERMINE DIVISOR
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PUSH DE ; SAVE CONFIG
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CALL UART_COMPDIV ; COMPUTE DIVISOR TO BC
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POP DE ; RESTORE CONFIG
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RET NZ ; ABORT IF COMPDIV FAILS!
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;
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; GOT A DIVISOR, COMMIT NEW CONFIG
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LD (IY + 4),E ; SAVE LOW WORD
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LD (IY + 5),D ; SAVE HI WORD
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;
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; START OF ACTUAL UART CONFIGURATION
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LD A,80H ; DLAB IS BIT 7 OF LCR
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UART_OUTP(UART_LCR) ; DLAB ON
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LD A,B
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UART_OUTP(UART_DLM) ; SET DIVISOR (MS)
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LD A,C
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UART_OUTP(UART_DLL) ; SET DIVISOR (LS)
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;
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; SETUP FCR (DLAB MUST STILL BE ON FOR ACCESS TO BIT 5)
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LD A,%00100111 ; FIFO ENABLE & RESET, 64 BYTE FIFO ENABLE ON 750+
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UART_OUTP(UART_FCR) ; DO IT
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;
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; SETUP LCR FROM SECOND CONFIG BYTE (DLAB IS CLEARED)
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LD A,(IY + 4) ; GET CONFIG BYTE
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AND ~$C0 ; ISOLATE PARITY, STOP/DATA BITS
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UART_OUTP(UART_LCR) ; SAVE IT
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;
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; SETUP MCR FROM FIRST CONFIG BYTE
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LD A,(IY + 5) ; GET CONFIG BYTE
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AND ~$1F ; REMOVE ENCODED BAUD RATE BITS
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OR $03 ; FORCE RTS & DTR
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UART_OUTP(UART_MCR) ; SAVE IT
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;
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; TEST FOR EFR CAPABLE CHIPS
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LD A,(IY + 1) ; GET UART TYPE
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CP UART_16650 ; 16650?
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JR Z,UART_INITDEV2 ; USE EFR REGISTER
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CP UART_16850 ; 16850?
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JR Z,UART_INITDEV2 ; USE EFR REGISTER
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JR UART_INITDEV4 ; NO EFR, SKIP AHEAD
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;
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UART_INITDEV2:
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; WE HAVE AN EFR CAPABLE CHIP, SET EFR REGISTER
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UART_INP(UART_LCR) ; GET CURRENT LCR VALUE
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PUSH AF ; SAVE IT
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LD A,$BF ; VALUE TO ACCESS EFR
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UART_OUTP(UART_LCR) ; SET VALUE IN LCR
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LD A,(IY + 5) ; GET CONFIG BYTE
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BIT 5,A ; AFC REQUESTED?
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LD A,$C0 ; ASSUME AFC ON
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JR NZ,UART_INITDEV3 ; YES, IMPLEMENT IT
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XOR A ; NO AFC REQEUST, EFR := 0
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;
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UART_INITDEV3:
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UART_OUTP(UART_EFR) ; SAVE IT
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POP AF ; RECOVER ORIGINAL LCR VALUE
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UART_OUTP(UART_LCR) ; AND PUT IT BACK
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;
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UART_INITDEV4:
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#IF (UART_DEBUG)
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PRTS(" [$")
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; DEBUG: DUMP UART TYPE
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LD A,(IY + 1)
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CALL PRTHEXBYTE
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; DEBUG: DUMP IIR
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UART_INP(UART_IIR)
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CALL PC_SPACE
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CALL PRTHEXBYTE
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; DEBUG: DUMP LCR
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UART_INP(UART_LCR)
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CALL PC_SPACE
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CALL PRTHEXBYTE
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; DEBUG: DUMP MCR
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UART_INP(UART_MCR)
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CALL PC_SPACE
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CALL PRTHEXBYTE
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; DEBUG: DUMP EFR
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UART_INP(UART_LCR)
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PUSH AF
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LD A,$BF
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UART_OUTP(UART_LCR)
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UART_INP(UART_EFR)
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LD H,A
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EX (SP),HL
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LD A,H
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UART_OUTP(UART_LCR)
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POP AF
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CALL PC_SPACE
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CALL PRTHEXBYTE
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PRTC(']')
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#ENDIF
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;
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XOR A ; SIGNAL SUCCESS
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RET
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;
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;
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;
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UART_QUERY:
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LD E,(IY + 4) ; FIRST CONFIG BYTE TO E
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LD D,(IY + 5) ; SECOND CONFIG BYTE TO D
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XOR A ; SIGNAL SUCCESS
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RET ; DONE
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;
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;
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;
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UART_DEVICE:
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LD D,CIODEV_UART ; D := DEVICE TYPE
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LD E,(IY) ; E := PHYSICAL UNIT
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LD C,$00 ; C := DEVICE TYPE, 0x00 IS RS-232
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XOR A ; SIGNAL SUCCESS
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RET
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;
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; UART DETECTION ROUTINE
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;
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UART_DETECT:
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;
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; SEE IF UART IS THERE BY CHECKING DLAB FUNCTIONALITY
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XOR A ; ZERO ACCUM
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UART_OUTP(UART_IER) ; IER := 0
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LD A,$80 ; DLAB BIT ON
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UART_OUTP(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW ACTIVE)
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LD A,$5A ; LOAD TEST VALUE
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UART_OUTP(UART_DLM) ; OUTPUT TO DLM
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UART_INP(UART_DLM) ; READ IT BACK
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CP $5A ; CHECK FOR TEST VALUE
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JP NZ,UART_DETECT_NONE ; NOPE, UNKNOWN UART OR NOT PRESENT
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XOR A ; DLAB BIT OFF
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UART_OUTP(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW INACTIVE)
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UART_INP(UART_IER) ; READ IER
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CP $5A ; CHECK FOR TEST VALUE
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JP Z,UART_DETECT_NONE ; IF STILL $5A, UNKNOWN OR NOT PRESENT
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;
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; TEST FOR FUNCTIONAL SCRATCH REG, IF NOT, WE HAVE AN 8250
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LD A,$5A ; LOAD TEST VALUE
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UART_OUTP(UART_SCR) ; PUT IT IN SCRATCH REGISTER
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UART_INP(UART_SCR) ; READ IT BACK
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CP $5A ; CHECK IT
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JR NZ,UART_DETECT_8250 ; STUPID 8250
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;
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; TEST FOR EFR REGISTER WHICH IMPLIES 16650/850
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LD A,$BF ; VALUE TO ENABLE EFR
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UART_OUTP(UART_LCR) ; WRITE IT TO LCR
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UART_INP(UART_SCR) ; READ SCRATCH REGISTER
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CP $5A ; SPR STILL THERE?
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JR NZ,UART_DETECT1 ; NOPE, HIDDEN, MUST BE 16650/850
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;
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; RESET LCR TO DEFAULT
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LD A,$80 ; DLAB BIT ON
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UART_OUTP(UART_LCR) ; RESET LCR
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;
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; TEST FCR TO ISOLATE 16450/550/550A
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LD A,$E7 ; TEST VALUE
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UART_OUTP(UART_FCR) ; PUT IT IN FCR
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UART_INP(UART_IIR) ; READ BACK FROM IIR
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BIT 6,A ; BIT 6 IS FIFO ENABLE, LO BIT
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JR Z,UART_DETECT_16450 ; IF NOT SET, MUST BE 16450
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BIT 7,A ; BIT 7 IS FIFO ENABLE, HI BIT
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JR Z,UART_DETECT_16550 ; IF NOT SET, MUST BE 16550
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BIT 5,A ; BIT 5 IS 64 BYTE FIFO
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JR Z,UART_DETECT2 ; IF NOT SET, MUST BE 16550A/C
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JR UART_DETECT_16750 ; ONLY THING LEFT IS 16750
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;
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UART_DETECT1: ; PICK BETWEEN 16650/850
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; NOT SURE HOW TO DIFFERENTIATE 16650 FROM 16850 YET
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JR UART_DETECT_16650 ; ASSUME 16650
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RET
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;
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UART_DETECT2: ; PICK BETWEEN 16550A/C
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; SET AFC BIT IN FCR
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LD A,$20 ; SET AFC BIT, MCR:5
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UART_OUTP(UART_MCR) ; WRITE NEW FCR VALUE
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;
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; READ IT BACK, IF SET, WE HAVE 16550C
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UART_INP(UART_MCR) ; READ BACK MCR
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BIT 5,A ; CHECK AFC BIT
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JR Z,UART_DETECT_16550A ; NOT SET, SO 16550A
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JR UART_DETECT_16550C ; IS SET, SO 16550C
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;
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UART_DETECT_NONE:
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LD A,(IY + 2) ; BASE IO PORT
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CP $68 ; IS THIS PRIMARY SBC PORT?
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JR Z,UART_DETECT_8250 ; SPECIAL CASE FOR PRIMARY UART!
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LD A,UART_NONE ; IF SO, TREAT AS 8250 NO MATTER WHAT
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RET
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;
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UART_DETECT_8250:
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LD A,UART_8250
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RET
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;
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UART_DETECT_16450:
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LD A,UART_16450
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RET
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;
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UART_DETECT_16550:
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LD A,UART_16550
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RET
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;
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UART_DETECT_16550A:
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LD A,UART_16550A
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RET
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;
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UART_DETECT_16550C:
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LD A,UART_16550C
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RET
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;
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UART_DETECT_16650:
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LD A,UART_16650
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RET
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;
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UART_DETECT_16750:
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LD A,UART_16750
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RET
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;
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UART_DETECT_16850:
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LD A,UART_16850
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RET
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;
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; COMPUTE DIVISOR TO BC
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;
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UART_COMPDIV:
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; WE WANT TO DETERMINE A DIVISOR FOR THE UART CLOCK
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; THAT RESULTS IN THE DESIRED BAUD RATE.
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; BAUD RATE = UART CLK / DIVISOR, OR TO SOLVE FOR DIVISOR
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; DIVISOR = UART CLK / BAUDRATE.
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; THE UART CLOCK IS THE UART OSC PRESCALED BY 16. ALSO, WE CAN
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; TAKE ADVANTAGE OF ENCODED BAUD RATES ALWAYS BEING A FACTOR OF 75.
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; SO, WE CAN USE (UART OSC / 16 / 75) / (BAUDRATE / 75)
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;
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; FIRST WE DECODE THE BAUDRATE, BUT WE USE A CONSTANT OF 1 INSTEAD
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; OF THE NORMAL 75. THIS PRODUCES (BAUDRATE / 75).
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;
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LD A,D ; GET CONFIG MSB
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AND $1F ; ISOLATE ENCODED BAUD RATE
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LD L,A ; PUT IN L
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LD H,0 ; H IS ALWAYS ZERO
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LD DE,1 ; USE 1 FOR ENCODING CONSTANT
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CALL DECODE ; DE:HL := BAUD RATE, ERRORS IGNORED
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EX DE,HL ; DE := (BAUDRATE / 75), DISCARD HL
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LD HL,UARTOSC / 16 / 75 ; HL := (UART OSC / 16 / 75)
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|
JP DIV16 ; BC := HL/DE == DIVISOR AND RETURN
|
|
;
|
|
;
|
|
;
|
|
UART_PRTCFG:
|
|
; ANNOUNCE PORT
|
|
CALL NEWLINE ; FORMATTING
|
|
PRTS("UART$") ; FORMATTING
|
|
LD A,(IY) ; DEVICE NUM
|
|
CALL PRTDECB ; PRINT DEVICE NUM
|
|
PRTS(": IO=0x$") ; FORMATTING
|
|
LD A,(IY + 2) ; GET BASE PORT
|
|
CALL PRTHEXBYTE ; PRINT BASE PORT
|
|
|
|
; PRINT THE UART TYPE
|
|
CALL PC_SPACE ; FORMATTING
|
|
LD A,(IY + 1) ; GET UART TYPE BYTE
|
|
RLCA ; MAKE IT A WORD OFFSET
|
|
LD HL,UART_TYPE_MAP ; POINT HL TO TYPE MAP TABLE
|
|
CALL ADDHLA ; HL := ENTRY
|
|
LD E,(HL) ; DEREFERENCE
|
|
INC HL ; ...
|
|
LD D,(HL) ; ... TO GET STRING POINTER
|
|
CALL WRITESTR ; PRINT IT
|
|
;
|
|
; ALL DONE IF NO UART WAS DETECTED
|
|
LD A,(IY + 1) ; GET UART TYPE BYTE
|
|
OR A ; SET FLAGS
|
|
RET Z ; IF ZERO, NOT PRESENT
|
|
;
|
|
PRTS(" MODE=$") ; FORMATTING
|
|
LD E,(IY + 4) ; LOAD CONFIG
|
|
LD D,(IY + 5) ; ... WORD TO DE
|
|
CALL PS_PRTSC0 ; PRINT CONFIG
|
|
;
|
|
; ; PRINT FEATURES ENABLED
|
|
; LD A,(UART_FEAT)
|
|
; BIT UART_FIFO,A
|
|
; JR Z,UART_INITUNIT2
|
|
; PRTS(" FIFO$")
|
|
;UART_INITUNIT2:
|
|
; BIT UART_AFC,A
|
|
; JR Z,UART_INITUNIT3
|
|
; PRTS(" AFC$")
|
|
;UART_INITUNIT3:
|
|
;
|
|
XOR A
|
|
RET
|
|
;
|
|
; ROUTINES TO READ/WRITE PORTS INDIRECTLY
|
|
;
|
|
; READ VALUE OF UART PORT ON TOS INTO REGISTER A
|
|
;
|
|
UART_INP_IMP:
|
|
EX (SP),HL ; SWAP HL AND TOS
|
|
PUSH BC ; PRESERVE BC
|
|
LD A,(IY + 2) ; GET UART IO BASE PORT
|
|
OR (HL) ; OR IN REGISTER ID BITS
|
|
LD C,A ; C := PORT
|
|
IN A,(C) ; READ PORT INTO A
|
|
POP BC ; RESTORE BC
|
|
INC HL ; BUMP HL PAST REG ID PARM
|
|
EX (SP),HL ; SWAP BACK HL AND TOS
|
|
RET
|
|
;
|
|
; WRITE VALUE IN REGISTER A TO UART PORT ON TOS
|
|
;
|
|
UART_OUTP_IMP:
|
|
EX (SP),HL ; SWAP HL AND TOS
|
|
PUSH BC ; PRESERVE BC
|
|
LD B,A ; PUT VALUE TO WRITE IN B
|
|
LD A,(IY + 2) ; GET UART IO BASE PORT
|
|
OR (HL) ; OR IN REGISTER ID BITS
|
|
LD C,A ; C := PORT
|
|
OUT (C),B ; WRITE VALUE TO PORT
|
|
POP BC ; RESTORE BC
|
|
INC HL ; BUMP HL PAST REG ID PARM
|
|
EX (SP),HL ; SWAP BACK HL AND TOS
|
|
RET
|
|
;
|
|
;
|
|
;
|
|
UART_TYPE_MAP:
|
|
.DW UART_STR_NONE
|
|
.DW UART_STR_8250
|
|
.DW UART_STR_16450
|
|
.DW UART_STR_16550
|
|
.DW UART_STR_16550A
|
|
.DW UART_STR_16550C
|
|
.DW UART_STR_16650
|
|
.DW UART_STR_16750
|
|
.DW UART_STR_16850
|
|
|
|
UART_STR_NONE .DB "<NOT PRESENT>$"
|
|
UART_STR_8250 .DB "8250$"
|
|
UART_STR_16450 .DB "16450$"
|
|
UART_STR_16550 .DB "16550$"
|
|
UART_STR_16550A .DB "16550A$"
|
|
UART_STR_16550C .DB "16550C$"
|
|
UART_STR_16650 .DB "16650$"
|
|
UART_STR_16750 .DB "16750$"
|
|
UART_STR_16850 .DB "16850$"
|
|
;
|
|
UART_PAR_MAP .DB "NONENMNS"
|
|
;
|
|
; WORKING VARIABLES
|
|
;
|
|
UART_DEV .DB 0 ; DEVICE NUM USED DURING INIT
|
|
;
|
|
; UART PORT TABLE
|
|
;
|
|
UART_CFG:
|
|
#IF (UARTSBC)
|
|
; SBC/ZETA ONBOARD SERIAL PORT
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $68 ; IO PORT BASE (RBR, THR)
|
|
.DB $68 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW DEFSERCFG ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
#ENDIF
|
|
#IF (UARTCAS)
|
|
; CASSETTE INTERFACE SERIAL PORT
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $80 ; IO PORT BASE (RBR, THR)
|
|
.DB $80 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW UARTCASSPD ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
#ENDIF
|
|
#IF (UARTMFP)
|
|
; MF/PIC SERIAL PORT
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $48 ; IO PORT BASE (RBR, THR)
|
|
.DB $48 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW DEFSERCFG ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
#ENDIF
|
|
#IF (UART4)
|
|
; 4UART SERIAL PORT A
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $C0 ; IO PORT BASE (RBR, THR)
|
|
.DB $C0 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW DEFSERCFG ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
; 4UART SERIAL PORT B
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $C8 ; IO PORT BASE (RBR, THR)
|
|
.DB $C8 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW DEFSERCFG ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
; 4UART SERIAL PORT C
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $D0 ; IO PORT BASE (RBR, THR)
|
|
.DB $D0 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW DEFSERCFG ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
; 4UART SERIAL PORT D
|
|
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
|
|
.DB 0 ; UART TYPE
|
|
.DB $D8 ; IO PORT BASE (RBR, THR)
|
|
.DB $D8 + UART_LSR ; LINE STATUS PORT (LSR)
|
|
.DW DEFSERCFG ; LINE CONFIGURATION
|
|
.FILL 2,$FF ; FILLER
|
|
#ENDIF
|
|
;
|
|
UART_CNT .EQU ($ - UART_CFG) / 8
|