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14 lines
612 B
14 lines
612 B
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; ZETA HARDWARE DEFINITIONS
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;
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SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
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;
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; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)
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MPCL_RAM .EQU SBC_BASE + $18 ; MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY)
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MPCL_ROM .EQU SBC_BASE + $1C ; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
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;
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RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
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PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
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SIOBASE .EQU $B0 ; ZILOG PERIPHERALS DEFAULT
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PIOZBASE .EQU SIOBASE+8 ; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
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PIO4BASE .EQU $90 ; ECB-4PIO DEFAULT PIO DEFAULT
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