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334 lines
9.2 KiB
334 lines
9.2 KiB
;:::::::::::::::::::::::::::::::::::::::::::::::::*************************
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; Byte I/O Routines *** Hardware Specific ***
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; - D-X Designs Pty Ltd P112 - *************************
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;
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; Several serial and parallel options exist on the P112, with two serial
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; ports available at RS-232 signalling levels. The primary port defined here
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; as COM1 uses SCC Channel A of the Z80182. A 16550-compatible serial port
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; on the SMC FDC37C665 is used as COM2. Three other serial ports (the two
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; ACSI ports in the Z180 core, and SCC Channel B) are available at TTL
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; voltage levels on a single header and may be defined as COM3-5 if the pins
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; from the Z182 are not otherwise used.
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; This code supports the additional serial channels if the MORDEV equate
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; is set to YES. If any of the three additional serial ports are defined
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; (ESCC_B, ASCI_0, ASCI_1), then the System Configuration Register is set to
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; Zero activating the additional signals in the conditions specified herein
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; as activated by options in DEF-DX.LIB.
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; A full Parallel port on the SMC FDC37C655 (in Normal Centronics mode) is
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; used as the primary List (Printer) Device.
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;
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; NOTE: At the present time, it appears that port 0D9H (ENH182) cannot be set
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; so ESCC operation at 24 MHz will occur at the full clock rate instead
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; of being divided by Two as specified in Zilog documentation. Code
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; managing ENH182 is commented out with ";;--" markers (HFB).
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;
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; 1.2 - 28 Aug 01 - Final scrub for GPL release. HFB
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; 1.1a- 11 May 97 - Cleaned code, fixed added port accesses. HFB
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; 1.1 - 25 Jan 97 - Revised ESCC Baud rate calcs, added COM3-5. HFB
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; 1.0 - 19 Jun 96 - Initial Release for the P112 from YASBEC. HFB
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; Place constants for Expansions here
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CSEG
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; Byte Device Control Tables
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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DEVCFG:
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; The Clock Rate for the SCC channels on the Z80182 is based on a divider
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; constant loaded in extended registers, the Processor Crystal frequency,
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; and the setting of the divider in the SCC Register (1FH).
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;
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; NOTE: Divisor values are computed based on a compromise between the Crystal
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; rates considered "standard" (6.144, 9.216, 12.288 MHz, etc) and the
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; 16.000 MHz initially placed on the P112. Higher data rates (38.4 kbps
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; and higher) may be out of tolerance, particularly at low CPU speeds.
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;
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; Clock rates for the serial port on the SMC 37C655 are based on a software
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; programmable divider from the 24 MHz crystal driving the chip.
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COM1: DEFB 'COM1' ; 4-Char ID
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DEFB 11101011B ; Baud Rate
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; ||||++++--- Baud Rate setting (19.2 kbps)
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; ++++------- Maximum Baud Rate (115.2 kbps)
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; Rates are as:
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; 0000 = None 0001 = 134.5 0011 = 50 0011 = 75
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; 0100 = 150 0101 = 300 0110 = 600 0111 = 1200
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; 1000 = 2400 1001 = 4800 1010 = 9600 1011 = 19200
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; 1100 = 38400 1101 = 76800 1110 = 115200 1111 = Fixed
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DEFB 11100001B ; Config Byte (In,Out,CTS/RTS control,1 Stop)
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; |||||||+---------- Stop Bits 1 (1), 2 (0)
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; ||||||+----------- Parity Enable (1), Disable (0)
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; |||||+------------ Parity Even (1), Odd (0)
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; ||||+------------- Data Bits 8 (0), 7 (1)
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; |||+-------------- Xon-Xoff Handshake
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; ||+--------------- CTS/RTS Handshake
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; |+---------------- Input Device No (0), Yes (1)
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; +----------------- Output Device No (0), Yes (1)
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DEFB 0FFH ; Input Data Mask
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DEFB 0FFH ; Output Data Mask
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DEFW COM1OT ; COM 1 Byte Output
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DEFW COM1OS ; COM 1 Output Status
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DEFW COM1IN ; COM 1 Byte Input
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DEFW COM1IS ; COM 1 Input Status
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COM2: DEFB 'COM2' ; 4-Char ID
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DEFB 11101010B ; Baud Rate (115.2k Max, 9600 Set)
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DEFB 11100001B ; Config Byte (In,Out,CTS/RTS control,1 Stop)
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DEFB 0FFH ; Input Data Mask
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DEFB 0FFH ; Output Data Mask
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DEFW COM2OT ; COM 2 Byte Output
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DEFW COM2OS ; COM 2 Output Status
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DEFW COM2IN ; COM 2 Byte Input
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DEFW COM2IS ; COM 2 Input Status
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PIO1: DEFB 'PIO1' ; 4-Char ID
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DEFB 00000000B ; Baud Rate (None)
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DEFB 10000000B ; Config Byte (Output Only)
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DEFB 0FFH ; Input Data Mask
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DEFB 07FH ; Output Data Mask
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DEFW PIO1OT ; PIO Byte Output
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DEFW PIO1OS ; PIO Output Status
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DEFW PIO1IN ; PIO Byte Input
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DEFW PIO1IS ; PIO Input Status
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IF MOVCPM OR [MORDEV AND NOT [ESCC_B OR ASCI_0 OR ASCI_1]]
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DEFB 'NULL' ; 4-Char ID
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DEFB 00000000B ; Baud Rate (None)
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DEFB 11000000B ; Config Byte
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DEFB 0FFH ; Input Data Mask
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DEFB 0FFH ; Output Data Mask
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DEFW ISFALSE ; Null Output
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DEFW ISTRUE ; Null Output Status
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DEFW ISFALSE ; Null Input
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DEFW ISTRUE ; Null Input Status
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ENDIF
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DEFB 0 ; - End-of-Table marker
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MAXBDV EQU [$-DEVCFG-1]/[COM2-COM1] ; Number of Character Devices Defined
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DEVTBL: LD HL,DEVCFG ; BYTE device table
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RET ; CP/M-3 device init
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; COM1 Drivers
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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IF HBIOS
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; Uses HBIOS
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;.....
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; COM1 Input Status Test
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COM1IS:
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PUSH BC
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PUSH DE
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PUSH HL
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LD BC,0200H + HB_IODEV ; Func=$02 (IS), Device/Unit=HB_IODEV
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CALL HBX_INVOKE
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POP HL
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POP DE
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POP BC
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RET
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;.....
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; COM1 Input Routine
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; Remain in Loop until Char ready, then Return Char in A
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COM1IN:
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PUSH BC
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PUSH DE
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PUSH HL
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LD BC,0000H + HB_IODEV ; Func=$00 (IN), Device/Unit=HB_IODEV
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CALL HBX_INVOKE
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LD A,E
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POP HL
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POP DE
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POP BC
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RET
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;.....
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; COM1 Output Status Test
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COM1OS:
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PUSH BC
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PUSH DE
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PUSH HL
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LD BC,0300H + HB_IODEV ; Func=$03 (OS), Device/Unit=HB_IODEV
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CALL HBX_INVOKE
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POP HL
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POP DE
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POP BC
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RET
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;.....
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; COM1 Output Routine (Byte to Send in C)
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COM1OT:
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PUSH BC
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PUSH DE
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PUSH HL
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LD E,C ; Character to E
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LD BC,0100H + HB_IODEV ; Func=$01 (OT), Device/Unit=HB_IODEV
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CALL HBX_INVOKE
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POP HL
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POP DE
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POP BC
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RET
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ELSE
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;.....
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; COM1 Input Status Test
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COM1IS: IN A,(_LSR) ; Input Status Reg Byte
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RRA ; Rcv Rdy Bit[0] -> Carry
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SBC A,A ; A=00 if Not Ready, FF if Char received
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RET
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;.....
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; COM1 Input Routine
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COM1IN: CALL COM1IS ; Char Ready?
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JR Z,COM1IN ; ..loop if Not
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IN A,(_RBR) ; Else Read Receive Buffer
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LD C,A ; Save byte
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LD A,(COM1+6) ; .get mask
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AND C ; ..apply it
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RET
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;.....
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; COM1 Output Status Test
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COM1OS:
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IN A,(_LSR) ; Read Status Reg
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AND 20H ; Mask Bit of interest
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RET Z ; ..return if nothing valid
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OR 0FFH ; Else set flags for Ready
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RET
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;.....
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; COM1 Output Routine
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COM1OT: CALL COM1OS ; Test if ready
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JR Z,COM1OT ; ..loop if not
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LD A,(COM1+7) ; Get output mask
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AND C ; apply
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OUT (_THR),A ; and send char to Xmt Holding Reg
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RET
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ENDIF
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PAGE
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; COM2 Drivers
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; Uses generic 16550 UART
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;.....
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; COM2 Input Status Test
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COM2IS: IN A,(_LSR) ; Input Status Reg Byte
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RRA ; Rcv Rdy Bit[0] -> Carry
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SBC A,A ; A=00 if Not Ready, FF if Char received
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RET
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;.....
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; COM2 Input Routine
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COM2IN: CALL COM2IS ; Char Ready?
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JR Z,COM2IN ; ..loop if Not
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IN A,(_RBR) ; Else Read Receive Buffer
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LD C,A ; Save byte
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LD A,(COM2+6) ; .get mask
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AND C ; ..apply it
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RET
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;.....
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; COM2 Output Status Test
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COM2OS:
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IN A,(_LSR) ; Read Status Reg
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SOSTV: AND 20H ; Mask Bit of interest
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RETST: RET Z ; ..return if nothing valid
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ISTRUE: OR 0FFH ; Else set flags for Ready
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RET
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;.....
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; COM2 Output Routine
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COM2OT: CALL COM2OS ; Test if ready
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JR Z,COM2OT ; ..loop if not
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LD A,(COM2+7) ; Get output mask
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AND C ; apply
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OUT (_THR),A ; and send char to Xmt Holding Reg
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RET
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PAGE
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; Parallel I/O Drivers
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;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; Uses "Standard" Parallel Centronics mode of SMC37C655 (output only)
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;.....
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; Parallel Input Status Test
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PIO1IS: JR ISTRUE ; Not implemented
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;.....
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; Parallel Input Data fetch
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PIO1IN: JP ISFALSE ; Not implemented
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;.....
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; Parallel Output Status Test
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PIO1OS: JP ISTRUE ; Not implemented
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;.....
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; Parallel Output Routine
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PIO1OT: JP ISFALSE ; Not implemented
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;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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;:: I n t e r r u p t T a b l e ::
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;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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; The Z80182 Interrupt Vector table is placed here on a 32-byte
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; boundary for internal peripherals.
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DEFS 32-[$-BIOSJT AND 31] ; Align
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INTTBL:
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DEFW BADINT ; FDC Controller w/Ints (FDCINT if Real Ints)
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DEFW BADINT ; Parallel output port (INTPIO if Real Ints)
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DEFW TIMER ; Timer0
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DEFW BADINT ; Timer1
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DEFW BADINT ; DMA Channel 0
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DEFW BADINT ; DMA Channel 1
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DEFW BADINT ; Clocked Serial IO
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DEFW BADINT ; ASCI 0 if Not Interrupt/Mordev
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DEFW BADINT ; ASCI 1 if Not Interrupt/Mordev
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; Error trap for unimplemented Interrupts
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BADINT: CALL PRINT
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DEFC CR,LF,'Bad Int.'
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JP WBOOT
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;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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;:: D e v i c e I n i t i a l i z a t i o n ::
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;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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CSEG
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DEVINI:
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IF BANKED
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CALL BIOSTK
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CALL GOSYSB
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JP JDVINI
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COMMON /BANK2/
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JDVINI:
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ENDIF
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RET ; WW
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