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386 lines
11 KiB
386 lines
11 KiB
;___XIO________________________________________________________________________________________________________________
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;
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; DIRECT SERIAL I/O
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;
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; PROVIDES INTERFACE TO PLATFORM BASE SERIAL I/O DEVICE
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; ALLOWS USER MESSAGING/INTERACTION PRIOR TO AND DURING HBIOS INIT
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;______________________________________________________________________________________________________________________
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;
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;
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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;
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UARTIOB .EQU $68
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;
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SIO_RBR .EQU UARTIOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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SIO_THR .EQU UARTIOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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SIO_IER .EQU UARTIOB + 1 ; DLAB=0: INT ENABLE REG
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SIO_IIR .EQU UARTIOB + 2 ; INT IDENT REGISTER (READ ONLY)
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SIO_FCR .EQU UARTIOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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SIO_LCR .EQU UARTIOB + 3 ; LINE CONTROL REG
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SIO_MCR .EQU UARTIOB + 4 ; MODEM CONTROL REG
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SIO_LSR .EQU UARTIOB + 5 ; LINE STATUS REG
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SIO_MSR .EQU UARTIOB + 6 ; MODEM STATUS REG
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SIO_SCR .EQU UARTIOB + 7 ; SCRATCH REGISTER
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SIO_DLL .EQU UARTIOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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SIO_DLM .EQU UARTIOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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;XIO_DIV .EQU (UARTOSC / (16 * CONBAUD))
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;
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#ENDIF
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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#ENDIF
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XIO_INIT: ; MINIMAL UART INIT
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#IF (PLATFORM == PLT_UNA)
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; SHOULD UNA SERIAL I/O BE RESET HERE???
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#ENDIF
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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; INIT ASCI0 WITH BASIC VALUES AND FAILSAFE DIVISOR
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LD A,$66 ; IGNORE CTS/DCD, NO BREAK DETECT
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OUT0 (Z180_ASEXT0),A ; -> ASEXT0
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LD A,$64 ; ENABLE XMT/RCV, 8 DATA, NO PARITY, 1 STOP
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OUT0 (Z180_CNTLA0),A ; -> CNTLA0
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;LD A,$20 ; FAILSAFE VALUE, 38400 BAUD AT 18.432 MHZ
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;LD A,$22 ; FAILSAFE VALUE, 9600 BAUD AT 18.432 MHZ
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;OUT0 (Z180_CNTLB0),A ; -> CNTLB0
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; TRY TO IMPLEMENT CONFIGURED BAUD RATE
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LD HL,DEFSERCFG ; SERIAL CONFIG WORD
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LD A,H ; BYTE W/ ENCODED BAUD RATE
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AND $1F ; ISOLATE BITS
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LD L,A ; MOVE TO L
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LD H,0 ; CLEAR MSB
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CALL XIO_CNTLB ; DERIVE CNTLB VALUE
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JR Z,XIO_INIT1 ; SUCCESS, IMPLEMENT IT
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LD C,$21 + Z180_CLKDIV ; FAILSAFE VALUE, 9600 BAUD IF OSC=18.432 MHZ
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XIO_INIT1:
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LD A,C ; MOVE VALUE TO ACCUM
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OUT0 (Z180_CNTLB0),A ; AND SET THE VALUE
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#ENDIF
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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LD DE,DEFSERCFG ; SERIAL CONFIG WORD
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CALL XIO_COMPDIV ; COMPUTE DIVISOR TO BC
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LD A,$80 ; LCR := DLAB ON
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OUT (SIO_LCR),A ; SET LCR
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;LD A,XIO_DIV % $100 ; BAUD RATE DIVISOR (LSB)
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LD A,C ; LOW BYTE OF DIVISOR
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OUT (SIO_DLL),A ; SET DIVISOR (LSB)
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;LD A,XIO_DIV / $100 ; BAUD RATE DIVISOR (MSB)
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LD A,B ; HIGH BYTE OF DIVISOR
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OUT (SIO_DLM),A ; SET DIVISOR (MSB)
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LD A,03H ; VALUE FOR LCR AND MCR
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OUT (SIO_LCR),A ; LCR := 3, DLAB OFF, 8 DATA, 1 STOP, NO PARITY
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OUT (SIO_MCR),A ; MCR := 3, DTR ON, RTS ON
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LD A,6 ; DISABLE & RESET FIFO'S
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OUT (SIO_FCR),A ; DO IT
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#ENDIF
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RET
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;
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XIO_SYNC: ; WAIT FOR FOR PENDING DATA IN FIFO TO CLEAR
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;
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#IF (PLATFORM == PLT_UNA)
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; NOT SURE ANYTHING IS POSSIBLE HERE...
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#ENDIF
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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; IMPLEMENT THIS... OR MAYBE NOT.
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#ENDIF
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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LD DE,CPUMHZ * 25 ; FAILSAFE TIMEOUT COUNTER
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XIO_SYNC1:
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IN A,(SIO_LSR) ; GET LINE STATUS REGISTER
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BIT 6,A ; TEST BIT 6 (TRANSMITTER EMPTY)
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JR NZ,XIO_SYNC2 ; EMPTY, MOVE ON
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DEC DE ; DECREMENT TIMEOUT COUNTER
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LD A,D ; TEST TIMEOUT COUNTER
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OR E ; ... FOR ZERO
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JR NZ,XIO_SYNC1 ; LOOP UNTIL TIMEOUT
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XIO_SYNC2:
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#ENDIF
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RET
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;
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XIO_CRLF2: ; OUTPUT 2 NEWLINES
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CALL XIO_CRLF ; SEND CRLF, FALL THRU FOR ANOTHER
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XIO_CRLF: ; OUTPUT A NEWLINE
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LD A,13 ; A = CR
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CALL XIO_OUTC ; WRITE IT
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LD A,10 ; A = LF
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JR XIO_OUTC ; WRITE IT AND RETURN
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;
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XIO_SPACE: ; OUTPUT A SPACE CHARACTER
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LD A,' '
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JR XIO_OUTC
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;
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XIO_DOT: ; OUTPUT A DOT (MARK PROGRESS)
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LD A,'.'
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;
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XIO_OUTC: ; OUTPUT BYTE IN A
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#IF (PLATFORM == PLT_UNA)
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PUSH BC ; PRESERVE BC
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PUSH DE ; PRESERVE DE
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LD BC,$0012 ; UNA UNIT = 0, FUNC = WRITE CHAR
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LD E,A ; CHAR TO E
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CALL $FFFD ; DO IT (RST 08 NOT SETUP YET)
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POP DE ; RESTORE DE
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POP BC ; RESTORE BC
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RET ; DONE
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#ENDIF
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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PUSH AF ; SAVE INCOMING BYTE
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XIO_OUTC1:
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IN0 A,(Z180_STAT0) ; GET LINE STATUS
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AND $02 ; ISOLATE TDRE
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JR Z,XIO_OUTC1 ; LOOP TILL READY (EMPTY)
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POP AF ; RECOVER INCOMING BYTE TO OUTPUT
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OUT0 (Z180_TDR0),A ; WRITE THE CHAR TO ASCI
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RET
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#ENDIF
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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PUSH AF ; SAVE INCOMING BYTE
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XIO_OUTC1:
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IN A,(SIO_LSR) ; READ LINE STATUS REGISTER
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AND $20 ; ISOLATE THRE
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JR Z,XIO_OUTC1 ; LOOP TILL READY (EMPTY)
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POP AF ; RECOVER BYTE TO WRITE
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OUT (SIO_THR),A ; WRITE THE CHAR TO UART
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RET
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#ENDIF
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;
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XIO_INC: ; INPUT BYTE TO A
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#IF (PLATFORM == PLT_UNA)
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PUSH BC ; PRESERVE BC
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PUSH DE ; PRESERVE DE
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LD BC,$0011 ; UNA UNIT = 0, FUNC = READ CHAR
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CALL $FFFD ; DO IT (RST 08 NOT SETUP YET)
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LD A,E ; CHAR TO A
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POP DE ; RESTORE DE
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POP BC ; RESTORE BC
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RET ; DONE
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#ENDIF
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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XIO_INC1:
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IN0 A,(Z180_STAT0) ; READ LINE STATUS
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AND $80 ; ISOLATE RDRF
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JR Z,XIO_INC1 ; LOOP TILL CHAR AVAILABLE
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IN0 A,(Z180_RDR0) ; READ THE CHAR
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RET
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#ENDIF
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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XIO_INC1:
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IN A,(SIO_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; ISOLATE RDR
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JR Z,XIO_INC1 ; LOOP TILL CHAR AVAILABLE
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IN A,(SIO_RBR) ; READ THE CHAR
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RET
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#ENDIF
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;
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XIO_IST: ; INPUT STATUS TO A (NUM CHARS WAITING)
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#IF (PLATFORM == PLT_UNA)
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PUSH BC ; PRESERVE BC
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PUSH DE ; PRESERVE DE
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LD BC,$0013 ; UNA UNIT = 0, FUNC = READ CHAR
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CALL $FFFD ; DO IT (RST 08 NOT SETUP YET)
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LD A,E ; CHAR TO A
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OR A ; UPDATE ZF
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POP DE ; RESTORE DE
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POP BC ; RESTORE BC
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RET ; DONE
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#ENDIF
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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IN0 A,(Z180_STAT0) ; READ LINE STATUS
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AND $80 ; ISOLATE RDRF
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RET Z ; NO CHARS WAITING, A=0, Z SET
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LD A,1 ; SIGNAL 1 CHAR WAITING
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OR A ; UPDATE ZF
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RET
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#ENDIF
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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IN A,(SIO_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; ISOLATE RDR
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RET Z ; NO CHARS WAITING, A=0, Z SET
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LD A,1 ; SIGNAL 1 CHAR WAITING
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OR A ; UPDATE ZF
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RET
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#ENDIF
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;
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XIO_OUTS: ; OUTPUT '$' TERMINATED STRING AT ADDRESS IN HL
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LD A,(HL) ; GET NEXT BYTE
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CP '$' ; END OF STRING?
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RET Z ; YES, GET OUT
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CALL XIO_OUTC ; OTHERWISE, WRITE IT
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INC HL ; POINT TO NEXT BYTE
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JR XIO_OUTS ; AND LOOP
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#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
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;
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; COMPUTE DIVISOR TO BC
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;
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XIO_COMPDIV:
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; WE WANT TO DETERMINE A DIVISOR FOR THE UART CLOCK
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; THAT RESULTS IN THE DESIRED BAUD RATE.
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; BAUD RATE = UART CLK / DIVISOR, OR TO SOLVE FOR DIVISOR
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; DIVISOR = UART CLK / BAUDRATE.
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; THE UART CLOCK IS THE UART OSC PRESCALED BY 16. ALSO, WE CAN
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; TAKE ADVANTAGE OF ENCODED BAUD RATES ALWAYS BEING A FACTOR OF 75.
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; SO, WE CAN USE (UART OSC / 16 / 75) / (BAUDRATE / 75)
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;
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; FIRST WE DECODE THE BAUDRATE, BUT WE USE A CONSTANT OF 1 INSTEAD
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; OF THE NORMAL 75. THIS PRODUCES (BAUDRATE / 75).
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;
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LD A,D ; GET CONFIG MSB
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AND $1F ; ISOLATE ENCODED BAUD RATE
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LD L,A ; PUT IN L
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LD H,0 ; H IS ALWAYS ZERO
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LD DE,1 ; USE 1 FOR ENCODING CONSTANT
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CALL DECODE ; DE:HL := BAUD RATE, ERRORS IGNORED
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EX DE,HL ; DE := (BAUDRATE / 75), DISCARD HL
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LD HL,UARTOSC / 16 / 75 ; HL := (UART OSC / 16 / 75)
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JP XIO_DIV16 ; BC := HL/DE == DIVISOR AND RETURN
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;
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#ENDIF
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;
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;
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;
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
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;
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; DERIVE A CNTLB VALUE BASED ON AN ENCODED BAUD RATE AND CURRENT CPU SPEED
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; ENTRY: HL = ENCODED BAUD RATE
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; EXIT: C = CNTLB VALUE, A=0/Z IFF SUCCESS
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;
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; DESIRED DIVISOR == CPUHZ / BAUD
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; DUE TO ENCODING BAUD IS ALWAYS DIVISIBLE BY 75
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; Z180 DIVISOR IS ALWAYS A FACTOR OF 160
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;
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; X = (CPU_HZ / 160) / 75 ==> SIMPLIFIED ==> X = CPU_KHZ / 12
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; X = X / (BAUD / 75)
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; IF X % 3 == 0, THEN (PS=1, X := X / 3) ELSE PS=0
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; IF X % 4 == 0, THEN (DR=1, X := X / 4) ELSE DR=0
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; SS := LOG2(X)
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;
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XIO_CNTLB:
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LD DE,1 ; USE DECODE CONSTANT OF 1 TO GET BAUD RATE ALREADY DIVIDED BY 75
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CALL DECODE ; DECODE THE BAUDATE INTO DE:HL, DE IS DISCARDED
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;CALL TSTPT
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RET NZ ; ABORT ON ERROR
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PUSH HL ; HL HAS (BAUD / 75), SAVE IT
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;LD HL,(HCB + HCB_CPUKHZ) ; GET CPU CLK IN KHZ
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LD HL,CPUKHZ ; CPU CLK IN KHZ
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;LD HL,9216 ; *DEBUG*
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; DUE TO THE LIMITED DIVISORS POSSIBLE WITH CNTLB, YOU PRETTY MUCH
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; NEED TO USE A CPU SPEED THAT IS A MULTIPLE OF 128KHZ. BELOW, WE
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; ATTEMPT TO ROUND THE CPU SPEED DETECTED TO A MULTIPLE OF 128KHZ
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; WITH ROUNDING. THIS JUST MAXIMIZES OUR CHANCES OF SUCCESS COMPUTING
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; THE DIVISOR.
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LD DE,$0040 ; HALF OF 128 IS 64
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ADD HL,DE ; ADD FOR ROUNDING
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LD A,L ; MOVE TO ACCUM
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AND $80 ; STRIP LOW ORDER 7 BITS
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LD L,A ; ... AND PUT IT BACK
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LD DE,12 ; PREPARE TO DIVIDE BY 12
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CALL XIO_DIV16 ; BC := (CPU_KHZ / 12), REM IN HL, ZF
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;CALL TSTPT
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POP DE ; RESTORE (BAUD / 75)
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RET NZ ; ABORT IF REMAINDER
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PUSH BC ; MOVE WORKING VALUE
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POP HL ; ... BACK TO HL
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CALL XIO_DIV16 ; BC := X / (BAUD / 75)
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;CALL TSTPT
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RET NZ ; ABORT IF REMAINDER
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;
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; DETERMINE PS BIT BY ATTEMPTING DIVIDE BY 3
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PUSH BC ; SAVE WORKING VALUE ON STACK
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PUSH BC ; MOVE WORKING VALUE
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POP HL ; ... TO HL
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LD DE,3 ; SETUP TO DIVIDE BY 3
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CALL XIO_DIV16 ; BC := X / 3, REM IN HL, ZF
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;CALL TSTPT
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POP HL ; HL := PRIOR WORKING VALUE
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LD E,0 ; INIT E := 0 AS WORKING CNTLB VALUE
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JR NZ,XIO_CNTLB1 ; DID NOT WORK, LEAVE PS==0, SKIP AHEAD
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SET 5,E ; SET PS BIT
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PUSH BC ; MOVE NEW WORKING
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POP HL ; ... VALUE TO HL
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;
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XIO_CNTLB1:
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;CALL TSTPT
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; DETERMINE DR BIT BY ATTEMPTING DIVIDE BY 4
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LD A,L ; LOAD LSB OF WORKING VALUE
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AND $03 ; ISOLATE LOW ORDER BITS
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JR NZ,XIO_CNTLB2 ; NOT DIVISIBLE BY 4, SKIP AHEAD
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SET 3,E ; SET PS BIT
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SRL H ; DIVIDE HL BY 4
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RR L ; ...
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SRL H ; ...
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RR L ; ...
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;
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XIO_CNTLB2:
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;CALL TSTPT
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; DETERMINE SS BITS BY RIGHT SHIFTING AND INCREMENTING
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LD B,7 ; LOOP COUNTER, MAX VALUE OF SS IS 7
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LD C,E ; MOVE WORKING CNTLB VALUE TO C
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XIO_CNTLB3:
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BIT 0,L ; CAN WE SHIFT AGAIN?
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JR NZ,XIO_CNTLB4 ; NOPE, DONE
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SRL H ; IMPLEMENT THE
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RR L ; ... SHIFT OPERATION
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INC C ; INCREMENT SS BITS
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DJNZ XIO_CNTLB3 ; LOOP IF MORE SHIFTING POSSIBLE
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;
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; AT THIS POINT HL MUST BE EQUAL TO 1 OR WE FAILED!
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DEC HL ; IF HL == 1, SHOULD BECOME ZERO
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LD A,H ; TEST HL
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OR L ; ... FOR ZERO
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RET NZ ; ABORT IF NOT ZERO
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;
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XIO_CNTLB4:
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;CALL TSTPT
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XOR A
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RET
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;
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#ENDIF
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;
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; COMPUTE HL / DE = BC W/ REMAINDER IN HL & ZF
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;
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XIO_DIV16:
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LD A,H ; HL -> AC
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LD C,L ; ...
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LD HL,0 ; INIT HL
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LD B,16 ; INIT LOOP COUNT
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XIO_DIV16A:
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SCF
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RL C
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RLA
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ADC HL,HL
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SBC HL,DE
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JR NC,XIO_DIV16B
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ADD HL,DE
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DEC C
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XIO_DIV16B:
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DJNZ XIO_DIV16A ; LOOP AS NEEDED
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LD B,A ; AC -> BC
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LD A,H ; SET ZF
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OR L ; ... BASED ON REMAINDER
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RET ; DONE
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