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647 lines
16 KiB
647 lines
16 KiB
;
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;==================================================================================================
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; UART DRIVER (SERIAL PORT)
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;==================================================================================================
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;
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UART_DEBUG .EQU FALSE
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;
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UART_NONE .EQU 0 ; UNKNOWN OR NOT PRESENT
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UART_8250 .EQU 1
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UART_16450 .EQU 2
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UART_16550 .EQU 3
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UART_16550A .EQU 4
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UART_16550C .EQU 5
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UART_16650 .EQU 6
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UART_16750 .EQU 7
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UART_16850 .EQU 8
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;
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UART_RBR .EQU 0 ; DLAB=0: RCVR BUFFER REG (READ)
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UART_THR .EQU 0 ; DLAB=0: XMIT HOLDING REG (WRITE)
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UART_IER .EQU 1 ; DLAB=0: INT ENABLE REG (READ)
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UART_IIR .EQU 2 ; INT IDENT REGISTER (READ)
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UART_FCR .EQU 2 ; FIFO CONTROL REG (WRITE)
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UART_LCR .EQU 3 ; LINE CONTROL REG (READ/WRITE)
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UART_MCR .EQU 4 ; MODEM CONTROL REG (READ/WRITE)
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UART_LSR .EQU 5 ; LINE STATUS REG (READ)
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UART_MSR .EQU 6 ; MODEM STATUS REG (READ)
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UART_SCR .EQU 7 ; SCRATCH REGISTER (READ/WRITE)
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UART_DLL .EQU 0 ; DLAB=1: DIVISOR LATCH (LS) (READ/WRITE)
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UART_DLM .EQU 1 ; DLAB=1: DIVISOR LATCH (MS) (READ/WRITE)
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UART_EFR .EQU 2 ; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE)
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;
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#DEFINE UART_IN(RID) CALL UART_INP \ .DB RID
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#DEFINE UART_OUT(RID) CALL UART_OUTP \ .DB RID
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;
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#IF (UARTCNT >= 1)
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UART0_RBR .EQU UART0IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART0_THR .EQU UART0IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART0_IER .EQU UART0IOB + 1 ; DLAB=0: INT ENABLE REG
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UART0_IIR .EQU UART0IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART0_FCR .EQU UART0IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART0_LCR .EQU UART0IOB + 3 ; LINE CONTROL REG
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UART0_MCR .EQU UART0IOB + 4 ; MODEM CONTROL REG
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UART0_LSR .EQU UART0IOB + 5 ; LINE STATUS REG
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UART0_MSR .EQU UART0IOB + 6 ; MODEM STATUS REG
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UART0_SCR .EQU UART0IOB + 7 ; SCRATCH REGISTER
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UART0_DLL .EQU UART0IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART0_DLM .EQU UART0IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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UART0_EFR .EQU UART0IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
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;
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UART0_DIV .EQU (1843200 / (16 * UART0BAUD))
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;
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#ENDIF
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;
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#IF (UARTCNT >= 2)
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UART1_RBR .EQU UART1IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART1_THR .EQU UART1IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART1_IER .EQU UART1IOB + 1 ; DLAB=0: INT ENABLE REG
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UART1_IIR .EQU UART1IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART1_FCR .EQU UART1IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART1_LCR .EQU UART1IOB + 3 ; LINE CONTROL REG
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UART1_MCR .EQU UART1IOB + 4 ; MODEM CONTROL REG
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UART1_LSR .EQU UART1IOB + 5 ; LINE STATUS REG
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UART1_MSR .EQU UART1IOB + 6 ; MODEM STATUS REG
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UART1_SCR .EQU UART1IOB + 7 ; SCRATCH REGISTER
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UART1_DLL .EQU UART1IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART1_DLM .EQU UART1IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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UART1_EFR .EQU UART1IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
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;
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UART1_DIV .EQU (1843200 / (16 * UART1BAUD))
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#ENDIF
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;
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#IF (UARTCNT >= 3)
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UART2_RBR .EQU UART2IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART2_THR .EQU UART2IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART2_IER .EQU UART2IOB + 1 ; DLAB=0: INT ENABLE REG
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UART2_IIR .EQU UART2IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART2_FCR .EQU UART2IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART2_LCR .EQU UART2IOB + 3 ; LINE CONTROL REG
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UART2_MCR .EQU UART2IOB + 4 ; MODEM CONTROL REG
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UART2_LSR .EQU UART2IOB + 5 ; LINE STATUS REG
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UART2_MSR .EQU UART2IOB + 6 ; MODEM STATUS REG
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UART2_SCR .EQU UART2IOB + 7 ; SCRATCH REGISTER
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UART2_DLL .EQU UART2IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART2_DLM .EQU UART2IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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UART2_EFR .EQU UART2IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
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;
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UART2_DIV .EQU (1843200 / (16 * UART2BAUD))
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#ENDIF
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;
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#IF (UARTCNT >= 4)
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UART3_RBR .EQU UART3IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART3_THR .EQU UART3IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART3_IER .EQU UART3IOB + 1 ; DLAB=0: INT ENABLE REG
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UART3_IIR .EQU UART3IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART3_FCR .EQU UART3IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART3_LCR .EQU UART3IOB + 3 ; LINE CONTROL REG
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UART3_MCR .EQU UART3IOB + 4 ; MODEM CONTROL REG
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UART3_LSR .EQU UART3IOB + 5 ; LINE STATUS REG
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UART3_MSR .EQU UART3IOB + 6 ; MODEM STATUS REG
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UART3_SCR .EQU UART3IOB + 7 ; SCRATCH REGISTER
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UART3_DLL .EQU UART3IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART3_DLM .EQU UART3IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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UART3_EFR .EQU UART3IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
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;
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UART3_DIV .EQU (1843200 / (16 * UART3BAUD))
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#ENDIF
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;
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; CHARACTER DEVICE DRIVER ENTRY
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; A: RESULT (OUT), CF=ERR
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; B: FUNCTION (IN)
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; C: CHARACTER (IN/OUT)
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; E: DEVICE/UNIT (IN)
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;
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;
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UART_INIT:
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#IF (UARTCNT >= 1)
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CALL UART0_INIT
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#ENDIF
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#IF (UARTCNT >= 2)
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CALL UART1_INIT
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#ENDIF
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#IF (UARTCNT >= 3)
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CALL UART2_INIT
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#ENDIF
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#IF (UARTCNT >= 4)
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CALL UART3_INIT
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#ENDIF
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RET
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;
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;
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;
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UART_DISPATCH:
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LD A,C ; GET DEVICE/UNIT
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AND $0F ; ISOLATE UNIT
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#IF (UARTCNT >= 1)
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JP Z,UART0_DISPATCH
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#ENDIF
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#IF (UARTCNT >= 2)
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DEC A
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JP Z,UART1_DISPATCH
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#ENDIF
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#IF (UARTCNT >= 3)
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DEC A
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JP Z,UART2_DISPATCH
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#ENDIF
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#IF (UARTCNT >= 4)
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DEC A
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JP Z,UART3_DISPATCH
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#ENDIF
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CALL PANIC
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;
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;
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;
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#IF (UARTCNT >= 1)
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;
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UART0_INIT:
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PRTS("UART0: IO=0x$")
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LD A,UART0IOB
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CALL PRTHEXBYTE
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;
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; SETUP FOR GENERIC INIT ROUTINE
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LD (UART_BASE),A ; IO BASE ADDRESS
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LD DE,UART0BAUD / 10 ; BAUD RATE / 10
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LD (UART_BAUD),DE ; SAVE IT
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LD DE,UART0_DIV ; DIVISOR
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LD (UART_DIV),DE ; SAVE IT
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;
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; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
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XOR A ; START WITH NO FEATURES
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#IF (UART0FIFO)
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SET UART_FIFO,A ; TURN ON FIFO BIT IF REQUESTED
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#ENDIF
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#IF (UART0AFC)
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SET UART_AFC,A ; TURN ON AFC BIT IF REQUESTED
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#ENDIF
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LD (UART_FUNC),A ; SAVE IT
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;
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JP UART_INITP ; HAND OFF TO GENERIC INIT CODE
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;
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;
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;
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UART0_DISPATCH:
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LD A,B ; GET REQUESTED FUNCTION
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AND $0F ; ISOLATE SUB-FUNCTION
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JP Z,UART0_IN
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DEC A
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JP Z,UART0_OUT
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DEC A
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JP Z,UART0_IST
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DEC A
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JP Z,UART0_OST
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CALL PANIC
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;
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;
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;
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UART0_IN:
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CALL UART0_IST
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OR A
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JR Z,UART0_IN
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IN A,(UART0_RBR) ; READ THE CHAR FROM THE UART
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LD E,A
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RET
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;
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;
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;
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UART0_IST:
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IN A,(UART0_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; TEST IF DATA IN RECEIVE BUFFER
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL CHAR READY, A = 1
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RET
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;
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;
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;
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UART0_OUT:
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CALL UART0_OST
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OR A
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JR Z,UART0_OUT
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LD A,E
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OUT (UART0_THR),A ; THEN WRITE THE CHAR TO UART
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RET
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;
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UART0_OST:
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IN A,(UART0_LSR) ; READ LINE STATUS REGISTER
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AND $20
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL BUFFER EMPTY, A = 1
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RET
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;
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#ENDIF
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;
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;
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;
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#IF (UARTCNT >= 2)
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;
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UART1_INIT:
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CALL NEWLINE
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PRTS("UART1: IO=0x$")
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LD A,UART1IOB
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CALL PRTHEXBYTE
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;
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; SETUP FOR GENERIC INIT ROUTINE
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LD (UART_BASE),A ; IO BASE ADDRESS
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LD DE,UART1BAUD / 10 ; BAUD RATE / 10
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LD (UART_BAUD),DE ; SAVE IT
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LD DE,UART1_DIV ; DIVISOR
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LD (UART_DIV),DE ; SAVE IT
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;
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; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
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XOR A ; START WITH NO FEATURES
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#IF (UART1FIFO)
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SET UART_FIFO,A ; TURN ON FIFO BIT IF REQUESTED
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#ENDIF
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#IF (UART1AFC)
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SET UART_AFC,A ; TURN ON AFC BIT IF REQUESTED
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#ENDIF
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LD (UART_FUNC),A ; SAVE IT
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;
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JP UART_INITP ; HAND OFF TO GENERIC INIT CODE
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;
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;
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;
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UART1_DISPATCH:
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LD A,B ; GET REQUESTED FUNCTION
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AND $0F ; ISOLATE SUB-FUNCTION
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JP Z,UART1_IN
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DEC A
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JP Z,UART1_OUT
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DEC A
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JP Z,UART1_IST
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DEC A
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JP Z,UART1_OST
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CALL PANIC
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;
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;
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;
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UART1_IN:
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CALL UART1_IST
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OR A
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JR Z,UART1_IN
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IN A,(UART1_RBR) ; READ THE CHAR FROM THE UART
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LD E,A
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RET
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;
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;
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;
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UART1_IST:
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IN A,(UART1_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; TEST IF DATA IN RECEIVE BUFFER
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL CHAR READY, A = 1
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RET
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;
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;
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;
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UART1_OUT:
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CALL UART1_OST
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OR A
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JR Z,UART1_OUT
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LD A,E
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OUT (UART1_THR),A ; THEN WRITE THE CHAR TO UART
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RET
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;
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UART1_OST:
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IN A,(UART1_LSR) ; READ LINE STATUS REGISTER
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AND $20
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL BUFFER EMPTY, A = 1
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RET
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;
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#ENDIF
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;
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; UART INITIALIZATION ROUTINE
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;
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UART_INITP:
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LD DE,400 ; WAIT 1/10 SEC FOR UART TO SEND PENDING
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CALL VDELAY
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; DETECT THE UART TYPE
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CALL UART_DETECT ; DETERMINE UART TYPE
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LD (UART_TYPE),A ; SAVE TYPE
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; HL IS USED BELOW TO REFER TO FEATURE BITS ENABLED
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LD HL,UART_FEAT ; HL POINTS TO FEATURE FLAGS BYTE
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XOR A ; RESET ALL FEATRUES
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LD (HL),A ; SAVE IT
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; START OF UART INITIALIZATION, SET BAUD RATE
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LD A,80H
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UART_OUT(UART_LCR) ; DLAB ON
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LD DE,(UART_DIV)
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LD A,E
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UART_OUT(UART_DLL) ; SET DIVISOR (LS)
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LD A,D
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UART_OUT(UART_DLM) ; SET DIVISOR (MS)
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; SET LCR TO DEFAULT
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LD A,$03 ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
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UART_OUT(UART_LCR) ; SAVE IT
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; SET MCR TO DEFAULT
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LD A,$03 ; DTR + RTS
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UART_OUT(UART_MCR) ; SAVE IT
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LD A,(UART_TYPE) ; GET UART TYPE
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CP UART_16550A ; 16550A OR BETTER?
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JR C,UART_INITP1 ; NOPE, SKIP FIFO & AFC FEATURES
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LD B,0 ; START BY ASSUMING NO FIFOS, FCR=0
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LD A,(UART_FUNC) ; LOAD FIFO ENABLE REQUEST VALUE
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BIT UART_FIFO,A ; TEST FOR FIFO REQUESTED
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JR Z,UART_FIFO1 ; NOPE
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LD B,$07 ; VALUE TO ENABLE AND RESET FIFOS
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SET UART_FIFO,(HL) ; RECORD FEATURE ENABLED
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UART_FIFO1:
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LD A,B ; MOVE VALUE TO A
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UART_OUT(UART_FCR) ; DO IT
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LD A,(UART_TYPE) ; GET UART TYPE
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CP UART_16550C ; 16550C OR BETTER?
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JR C,UART_INITP1 ; NOPE, SKIP AFC FEATURES
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; BRANCH BASED ON TYPE AFC CONFIGURATION (EFR OR MCR)
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LD A,(UART_TYPE) ; GET UART TYPE
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CP UART_16650 ; 16650?
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JR Z,UART_AFC2 ; USE EFR REGISTER
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CP UART_16850 ; 16750?
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JR Z,UART_AFC2 ; USE EFR REGISTER
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; SET AFC VIA MCR
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LD B,$03 ; START WITH DEFAULT MCR
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LD A,(UART_FUNC) ; LOAD AFC ENABLE REQUEST VALUE
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BIT UART_AFC,A ; TEST FOR AFC REQUESTED
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JR Z,UART_AFC1 ; NOPE
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SET 5,B ; SET MCR BIT TO ENABLE AFC
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SET UART_AFC,(HL) ; RECORD FEATURE ENABLED
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UART_AFC1:
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LD A,B ; MOVE VALUE TO Ar
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UART_OUT(UART_MCR) ; SET AFC VALUE VIA MCR
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JR UART_INITP1 ; AND CONTINUE
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UART_AFC2: ; SET AFC VIA EFR
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LD A,$BF ; VALUE TO ACCESS EFR
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UART_OUT(UART_LCR) ; SET VALUE IN LCR
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LD B,0 ; ASSUME AFC OFF, EFR=0
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LD A,(UART_FUNC) ; LOAD AFC ENABLE REQUEST VALUE
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BIT UART_AFC,A ; TEST FOR AFC REQUESTED
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JR Z,UART_AFC3 ; NOPE
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LD B,$C0 ; ENABLE CTS/RTS FLOW CONTROL
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SET UART_AFC,(HL) ; RECORD FEATURE ENABLED
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UART_AFC3:
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LD A,B ; MOVE VALUE TO A
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UART_OUT(UART_EFR) ; SAVE IT
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LD A,$03 ; NORMAL LCR VALUE
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UART_OUT(UART_LCR) ; SAVE IT
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UART_INITP1:
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#IF (UART_DEBUG)
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PRTS(" [$")
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; DEBUG: DUMP UART TYPE
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LD A,(UART_TYPE)
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CALL PRTHEXBYTE
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; DEBUG: DUMP IIR
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UART_IN(UART_IIR)
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CALL PC_SPACE
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CALL PRTHEXBYTE
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; DEBUG: DUMP LCR
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UART_IN(UART_LCR)
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CALL PC_SPACE
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CALL PRTHEXBYTE
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; DEBUG: DUMP MCR
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UART_IN(UART_MCR)
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CALL PC_SPACE
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CALL PRTHEXBYTE
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; DEBUG: DUMP EFR
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LD A,$BF
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UART_OUT(UART_LCR)
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UART_IN(UART_EFR)
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PUSH AF
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LD A,$03
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UART_OUT(UART_LCR)
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POP AF
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CALL PC_SPACE
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CALL PRTHEXBYTE
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PRTC(']')
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#ENDIF
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; PRINT THE UART TYPE
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LD A,(UART_TYPE)
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RLCA
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LD HL,UART_TYPE_MAP
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LD D,0
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LD E,A
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ADD HL,DE ; HL NOW POINTS TO MAP ENTRY
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LD A,(HL)
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INC HL
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LD D,(HL)
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LD E,A ; HL NOW POINTS TO STRING
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CALL PC_SPACE
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CALL WRITESTR ; PRINT THE STRING
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;
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; ALL DONE IF NO UART WAS DETECTED
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LD A,(UART_TYPE)
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OR A
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JR Z,UART_INITP3
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;
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; PRINT BAUD RATE
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PRTS(" BAUD=$")
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LD HL,(UART_BAUD)
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CALL PRTDEC
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PRTC('0')
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;
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; PRINT FEATURES ENABLED
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|
LD A,(UART_FEAT)
|
|
BIT UART_FIFO,A
|
|
JR Z,UART_INITP2
|
|
PRTS(" FIFO$")
|
|
UART_INITP2:
|
|
BIT UART_AFC,A
|
|
JR Z,UART_INITP3
|
|
PRTS(" AFC$")
|
|
UART_INITP3:
|
|
;
|
|
RET
|
|
;
|
|
; UART DETECTION ROUTINE
|
|
;
|
|
UART_DETECT:
|
|
;
|
|
; SEE IF UART IS THERE BY CHECKING DLAB FUNCTIONALITY
|
|
XOR A ; ZERO ACCUM
|
|
UART_OUT(UART_IER) ; IER := 0
|
|
LD A,$80 ; DLAB BIT ON
|
|
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW ACTIVE)
|
|
LD A,$5A ; LOAD TEST VALUE
|
|
UART_OUT(UART_DLM) ; OUTPUT TO DLM
|
|
UART_IN(UART_DLM) ; READ IT BACK
|
|
CP $5A ; CHECK FOR TEST VALUE
|
|
JR NZ,UART_DETECT_NONE ; NOPE, UNKNOWN UART OR NOT PRESENT
|
|
XOR A ; DLAB BIT OFF
|
|
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW INACTIVE)
|
|
UART_IN(UART_IER) ; READ IER
|
|
CP $5A ; CHECK FOR TEST VALUE
|
|
JR Z,UART_DETECT_NONE ; IF STILL $5A, UNKNOWN OR NOT PRESENT
|
|
;
|
|
; TEST FOR FUNCTIONAL SCRATCH REG, IF NOT, WE HAVE AN 8250
|
|
LD A,$5A ; LOAD TEST VALUE
|
|
UART_OUT(UART_SCR) ; PUT IT IN SCRATCH REGISTER
|
|
UART_IN(UART_SCR) ; READ IT BACK
|
|
CP $5A ; CHECK IT
|
|
JR NZ,UART_DETECT_8250 ; STUPID 8250
|
|
;
|
|
; TEST FOR EFR REGISTER WHICH IMPLIES 16650/850
|
|
LD A,$BF ; VALUE TO ENABLE EFR
|
|
UART_OUT(UART_LCR) ; WRITE IT TO LCR
|
|
UART_IN(UART_SCR) ; READ SCRATCH REGISTER
|
|
CP $5A ; SPR STILL THERE?
|
|
JR NZ,UART_DETECT1 ; NOPE, HIDDEN, MUST BE 16650/850
|
|
;
|
|
; RESET LCR TO DEFAULT
|
|
LD A,$80 ; DLAB BIT ON
|
|
UART_OUT(UART_LCR) ; RESET LCR
|
|
;
|
|
; TEST FCR TO ISOLATE 16450/550/550A
|
|
LD A,$E7 ; TEST VALUE
|
|
UART_OUT(UART_FCR) ; PUT IT IN FCR
|
|
UART_IN(UART_IIR) ; READ BACK FROM IIR
|
|
BIT 6,A ; BIT 6 IS FIFO ENABLE, LO BIT
|
|
JR Z,UART_DETECT_16450 ; IF NOT SET, MUST BE 16450
|
|
BIT 7,A ; BIT 7 IS FIFO ENABLE, HI BIT
|
|
JR Z,UART_DETECT_16550 ; IF NOT SET, MUST BE 16550
|
|
BIT 5,A ; BIT 5 IS 64 BYTE FIFO
|
|
JR Z,UART_DETECT2 ; IF NOT SET, MUST BE 16550A/C
|
|
JR UART_DETECT_16750 ; ONLY THING LEFT IS 16750
|
|
;
|
|
UART_DETECT1: ; PICK BETWEEN 16650/850
|
|
; NOT SURE HOW TO DIFFERENTIATE 16650 FROM 16850 YET
|
|
JR UART_DETECT_16650 ; ASSUME 16650
|
|
RET
|
|
;
|
|
UART_DETECT2: ; PICK BETWEEN 16650A/C
|
|
; SET AFC BIT IN FCR
|
|
LD A,$20 ; SET AFC BIT, MCR:5
|
|
UART_OUT(UART_MCR) ; WRITE NEW FCR VALUE
|
|
;
|
|
; READ IT BACK, IF SET, WE HAVE 16550C
|
|
UART_IN(UART_MCR) ; READ BACK MCR
|
|
BIT 5,A ; CHECK AFC BIT
|
|
JR Z,UART_DETECT_16550A ; NOT SET, SO 16550A
|
|
JR UART_DETECT_16550C ; IS SET, SO 16550C
|
|
;
|
|
UART_DETECT_NONE:
|
|
LD A,UART_NONE
|
|
RET
|
|
;
|
|
UART_DETECT_8250:
|
|
LD A,UART_8250
|
|
RET
|
|
;
|
|
UART_DETECT_16450:
|
|
LD A,UART_16450
|
|
RET
|
|
;
|
|
UART_DETECT_16550:
|
|
LD A,UART_16550
|
|
RET
|
|
;
|
|
UART_DETECT_16550A:
|
|
LD A,UART_16550A
|
|
RET
|
|
;
|
|
UART_DETECT_16550C:
|
|
LD A,UART_16550C
|
|
RET
|
|
;
|
|
UART_DETECT_16650:
|
|
LD A,UART_16650
|
|
RET
|
|
;
|
|
UART_DETECT_16750:
|
|
LD A,UART_16750
|
|
RET
|
|
;
|
|
UART_DETECT_16850:
|
|
LD A,UART_16850
|
|
RET
|
|
;
|
|
; ROUTINES TO READ/WRITE PORTS INDIRECTLY
|
|
;
|
|
; READ VALUE OF UART PORT ON TOS INTO REGISTER A
|
|
;
|
|
UART_INP:
|
|
EX (SP),HL ; SWAP HL AND TOS
|
|
PUSH BC ; PRESERVE BC
|
|
LD A,(UART_BASE) ; GET UART IO BASE PORT
|
|
OR (HL) ; OR IN REGISTER ID BITS
|
|
LD C,A ; C := PORT
|
|
INC HL ; BUMP HL PAST REG ID PARM
|
|
IN A,(C) ; READ PORT INTO A
|
|
POP BC ; RESTORE BC
|
|
EX (SP),HL ; SWAP BACK HL AND TOS
|
|
RET
|
|
;
|
|
; WRITE VALUE IN REGISTER A TO UART PORT ON TOS
|
|
;
|
|
UART_OUTP:
|
|
EX (SP),HL ; SWAP HL AND TOS
|
|
PUSH BC ; PRESERVE BC
|
|
PUSH AF ; SAVE AF (VALUE TO WRITE)
|
|
LD A,(UART_BASE) ; GET UART IO BASE PORT
|
|
OR (HL) ; OR IN REGISTER ID BITS
|
|
LD C,A ; C := PORT
|
|
INC HL ; BUMP HL PAST REG ID PARM
|
|
POP AF ; RESTORE VALUE TO WRITE
|
|
OUT (C),A ; WRITE VALUE TO PORT
|
|
POP BC ; RESTORE BC
|
|
EX (SP),HL ; SWAP BACK HL AND TOS
|
|
RET
|
|
;
|
|
;
|
|
;
|
|
UART_TYPE_MAP:
|
|
.DW UART_STR_NONE
|
|
.DW UART_STR_8250
|
|
.DW UART_STR_16450
|
|
.DW UART_STR_16550
|
|
.DW UART_STR_16550A
|
|
.DW UART_STR_16550C
|
|
.DW UART_STR_16650
|
|
.DW UART_STR_16750
|
|
.DW UART_STR_16850
|
|
|
|
UART_STR_NONE .DB "<NOT PRESENT>$"
|
|
UART_STR_8250 .DB "8250$"
|
|
UART_STR_16450 .DB "16450$"
|
|
UART_STR_16550 .DB "16550$"
|
|
UART_STR_16550A .DB "16550A$"
|
|
UART_STR_16550C .DB "16550C$"
|
|
UART_STR_16650 .DB "16650$"
|
|
UART_STR_16750 .DB "16750$"
|
|
UART_STR_16850 .DB "16850$"
|
|
;
|
|
; WORKING VARIABLES
|
|
;
|
|
UART_BASE .DB 0 ; BASE IO ADDRESS FOR ACTIVE UART
|
|
UART_TYPE .DB 0 ; UART TYPE DISCOVERED
|
|
UART_FEAT .DB 0 ; UART FEATURES DISCOVERED
|
|
UART_BAUD .DW 0 ; BAUD RATE
|
|
UART_DIV .DW 0 ; BAUD DIVISOR
|
|
UART_FUNC .DB 0 ; UART FUNCTIONS REQUESTED
|
|
;
|
|
;
|
|
;
|
|
UART_FIFO .EQU 0 ; FIFO ENABLE BIT
|
|
UART_AFC .EQU 1 ; AUTO FLOW CONTROL ENABLE BIT
|
|
|