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82 lines
2.8 KiB
82 lines
2.8 KiB
S100 Z80 CPU
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============
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S100 Z80 has only a small monitor ROM at the to of CPU address space
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which is not utilized by RomWBW. RomWBW treats the system as a
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ROMless system. RAM is provided by a separate board. RomWBW assumes
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the RAM board has >= 1024K which is the maximum RAM supported by the
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Z80 CPU memory manager.
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The ROMless startup mode treats the entire 1024KB as RAM. 128KB of RAM
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must be preloaded by the Monitor CF Loader. There will be no ROM
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disk available under RomWBW.
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The RomWBW 32K bank layout is as follows:
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Bank Contents Description
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-------- -------- -----------
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0x0 BIOS HBIOS Bank (operating)
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0x1 IMG0 ROM Loader, Monitor, ROM OSes
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0x2 IMG1 ROM Applications
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0x3 IMG2 Reserved
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0x4-0xF RAMD RAM Disk Banks
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0x10-1B APP Application Banks
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0x1C BUF OS Buffers (CP/M3)
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0x1D AUX Aux Bank (CP/M 3, BPBIOS, etc.)
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0x1E USR User Bank (CP/M TPA, etc.)
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0x1F COM Common Bank, Upper 32KB
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Memory Manager
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--------------
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The Z80 CPU implements a custom memory manager that allows mapping the 2
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lowest 16K portions of CPU address space ($0000-$3FFFF, and $4000-$7FFF).
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Each of these banks can be mapped to any physical 16K bank.
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The physical 16K banks are 16K aligned. The memory manager
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can address a maximum of 1MB of physical memory. Which is
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64 x 16K banks (bank numbers $00-$3F)
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The top 32K of CPU address space ($8000-$FFFF) is statically mapped
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to physical banks $02 & $03. RomWBW is designed to have the top
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32K of CPU address space assigned to the last two banks of
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RAM. So the RomWBW memory manager for this board (MM_SZ80)
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rotates the requested bank numbers by 4. With wrapping, this
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causes a RomWBW request for the top two banks to be mapped to
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physical banks $02 & $03.
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Z80 CPU Physical: 00 01 02 03 ... 38 39 3A 3B 3C 3D 3E 3F
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RomWBW Logical: 04 05 06 07 ... 3C 3D 3E 3F 00 01 02 03
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As a result, the Z80 CPU Monitor loads RomWBW starting at
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physical bank 04.
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S100 FPGA Z80 SBC
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=================
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FPGA Z80 has no real ROM. It has a single onboard 512K RAM chip.
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RomWBW assumes the use of the T35 FPGA with associated firmware.
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The ROMless startup mode treats the entire 512KB as RAM. 384KB of RAM
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must be preloaded by the FPGA Monitor CF Loader. There will be no ROM
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disk available under RomWBW.
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The RomWBW 32K bank layout is as follows:
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Bank Contents Description
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-------- -------- -----------
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0x0 BIOS HBIOS Bank (operating)
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0x1 IMG0 ROM Loader, Monitor, ROM OSes
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0x2 IMG1 ROM Applications
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0x3 IMG2 Reserved
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0x4-0xB RAMD RAM Disk Banks
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0xC BUF OS Buffers (CP/M3)
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0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.)
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0xE USR User Bank (CP/M TPA, etc.)
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0xF COM Common Bank, Upper 32KB
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Memory Manager
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--------------
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The T35 FPGA Z80 implements the Zeta 2 (Z2) memory manager.
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