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332 lines
7.8 KiB
332 lines
7.8 KiB
;
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;==================================================================================================
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; UART DRIVER (SERIAL PORT)
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;==================================================================================================
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;
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#IF (UARTCNT >= 1)
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UART0_RBR .EQU UART0IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART0_THR .EQU UART0IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART0_IER .EQU UART0IOB + 1 ; DLAB=0: INT ENABLE REG
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UART0_IIR .EQU UART0IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART0_FCR .EQU UART0IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART0_LCR .EQU UART0IOB + 3 ; LINE CONTROL REG
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UART0_MCR .EQU UART0IOB + 4 ; MODEM CONTROL REG
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UART0_LSR .EQU UART0IOB + 5 ; LINE STATUS REG
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UART0_MSR .EQU UART0IOB + 6 ; MODEM STATUS REG
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UART0_SCR .EQU UART0IOB + 7 ; SCRATCH REGISTER
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UART0_DLL .EQU UART0IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART0_DLM .EQU UART0IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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UART0_DIV .EQU (1843200 / (16 * UART0BAUD))
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#ENDIF
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;
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#IF (UARTCNT >= 2)
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UART1_RBR .EQU UART1IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART1_THR .EQU UART1IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART1_IER .EQU UART1IOB + 1 ; DLAB=0: INT ENABLE REG
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UART1_IIR .EQU UART1IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART1_FCR .EQU UART1IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART1_LCR .EQU UART1IOB + 3 ; LINE CONTROL REG
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UART1_MCR .EQU UART1IOB + 4 ; MODEM CONTROL REG
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UART1_LSR .EQU UART1IOB + 5 ; LINE STATUS REG
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UART1_MSR .EQU UART1IOB + 6 ; MODEM STATUS REG
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UART1_SCR .EQU UART1IOB + 7 ; SCRATCH REGISTER
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UART1_DLL .EQU UART1IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART1_DLM .EQU UART1IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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UART1_DIV .EQU (1843200 / (16 * UART1BAUD))
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#ENDIF
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;
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#IF (UARTCNT >= 3)
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UART2_RBR .EQU UART2IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART2_THR .EQU UART2IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART2_IER .EQU UART2IOB + 1 ; DLAB=0: INT ENABLE REG
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UART2_IIR .EQU UART2IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART2_FCR .EQU UART2IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART2_LCR .EQU UART2IOB + 3 ; LINE CONTROL REG
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UART2_MCR .EQU UART2IOB + 4 ; MODEM CONTROL REG
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UART2_LSR .EQU UART2IOB + 5 ; LINE STATUS REG
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UART2_MSR .EQU UART2IOB + 6 ; MODEM STATUS REG
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UART2_SCR .EQU UART2IOB + 7 ; SCRATCH REGISTER
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UART2_DLL .EQU UART2IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART2_DLM .EQU UART2IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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UART2_DIV .EQU (1843200 / (16 * UART2BAUD))
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#ENDIF
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;
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#IF (UARTCNT >= 4)
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UART3_RBR .EQU UART3IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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UART3_THR .EQU UART3IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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UART3_IER .EQU UART3IOB + 1 ; DLAB=0: INT ENABLE REG
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UART3_IIR .EQU UART3IOB + 2 ; INT IDENT REGISTER (READ ONLY)
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UART3_FCR .EQU UART3IOB + 2 ; FIFO CONTROL REG (WRITE ONLY)
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UART3_LCR .EQU UART3IOB + 3 ; LINE CONTROL REG
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UART3_MCR .EQU UART3IOB + 4 ; MODEM CONTROL REG
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UART3_LSR .EQU UART3IOB + 5 ; LINE STATUS REG
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UART3_MSR .EQU UART3IOB + 6 ; MODEM STATUS REG
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UART3_SCR .EQU UART3IOB + 7 ; SCRATCH REGISTER
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UART3_DLL .EQU UART3IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
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UART3_DLM .EQU UART3IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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UART3_DIV .EQU (1843200 / (16 * UART3BAUD))
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#ENDIF
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;
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; CHARACTER DEVICE DRIVER ENTRY
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; A: RESULT (OUT), CF=ERR
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; B: FUNCTION (IN)
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; C: CHARACTER (IN/OUT)
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; E: DEVICE/UNIT (IN)
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;
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;
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UART_INIT:
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#IF (UARTCNT >= 1)
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CALL UART0_INIT
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#ENDIF
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#IF (UARTCNT >= 2)
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CALL UART1_INIT
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#ENDIF
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#IF (UARTCNT >= 3)
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CALL UART2_INIT
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#ENDIF
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#IF (UARTCNT >= 4)
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CALL UART3_INIT
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#ENDIF
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RET
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;
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;
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;
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UART_DISPATCH:
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LD A,C ; GET DEVICE/UNIT
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AND $0F ; ISOLATE UNIT
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#IF (UARTCNT >= 1)
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JP Z,UART0_DISPATCH
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#ENDIF
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#IF (UARTCNT >= 2)
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DEC A
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JP Z,UART1_DISPATCH
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#ENDIF
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#IF (UARTCNT >= 3)
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DEC A
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JP Z,UART2_DISPATCH
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#ENDIF
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#IF (UARTCNT >= 4)
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DEC A
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JP Z,UART3_DISPATCH
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#ENDIF
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CALL PANIC
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;
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;
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;
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#IF (UARTCNT >= 1)
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;
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UART0_INIT:
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PRTS("UART0: IO=0x$")
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LD A,UART0IOB
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CALL PRTHEXBYTE
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PRTS(" BAUD=$")
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LD HL,UART0BAUD / 10
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CALL PRTDEC
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PRTC('0')
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LD A,80H
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OUT (UART0_LCR),A ; DLAB ON
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LD A,UART0_DIV % $100
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OUT (UART0_DLL),A ; SET DIVISOR (LS)
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LD A,UART0_DIV / $100
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OUT (UART0_DLM),A ; SET DIVISOR (MS)
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LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
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#IF (UART0AFC)
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PRTS(" AFC$")
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LD A,$55 ; TEST VALUE
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OUT (UART0_SCR),A ; SET SCRATCH REG TO TEST VALUE
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LD A,0BFH
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OUT (UART0_LCR),A ; SET LCR=$BF TO ATTEMPT TO ACCESS EFR
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IN A,(UART0_SCR) ; READ SCRATCH REGISTER
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CP $55 ; IF $55, NO EFR
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JR NZ,UART0_AFC1 ; NZ, HAVE EFR, DO IT
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SET 5,B ; ENABLE AUTO FLOW CONTROL
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JR UART0_AFC2
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UART0_AFC1:
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LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
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OUT (UART0_EFR),A ; SAVE IT
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UART0_AFC2:
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#ENDIF
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LD A,03H
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OUT (UART0_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
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LD A,B ; LOAD MCR VALUE TO SET
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OUT (UART0_MCR),A ; SAVE IT
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#IF (UART0FIFO)
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; LD A,07H ; ENABLE AND RESET FIFOS
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LD A,01H ; ENABLE AND RESET FIFOS
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OUT (UART0_FCR),A ; ENABLE FIFOS
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PRTS(" FIFO$")
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#ENDIF
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RET
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;
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;
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;
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UART0_DISPATCH:
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LD A,B ; GET REQUESTED FUNCTION
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AND $0F ; ISOLATE SUB-FUNCTION
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JP Z,UART0_IN
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DEC A
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JP Z,UART0_OUT
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DEC A
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JP Z,UART0_IST
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DEC A
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JP Z,UART0_OST
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CALL PANIC
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;
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;
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;
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UART0_IN:
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CALL UART0_IST
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OR A
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JR Z,UART0_IN
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IN A,(UART0_RBR) ; READ THE CHAR FROM THE UART
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LD E,A
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RET
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;
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;
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;
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UART0_IST:
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IN A,(UART0_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; TEST IF DATA IN RECEIVE BUFFER
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL CHAR READY, A = 1
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RET
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;
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;
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;
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UART0_OUT:
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CALL UART0_OST
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OR A
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JR Z,UART0_OUT
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LD A,E
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OUT (UART0_THR),A ; THEN WRITE THE CHAR TO UART
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RET
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;
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UART0_OST:
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IN A,(UART0_LSR) ; READ LINE STATUS REGISTER
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AND $20
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL BUFFER EMPTY, A = 1
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RET
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;
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#ENDIF
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;
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;
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;
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#IF (UARTCNT >= 2)
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;
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UART1_INIT:
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CALL NEWLINE
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PRTS("UART1: IO=0x$")
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LD A,UART1IOB
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CALL PRTHEXBYTE
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PRTS(" BAUD=$")
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LD HL,UART1BAUD / 10
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CALL PRTDEC
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PRTC('0')
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LD A,80H
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OUT (UART1_LCR),A ; DLAB ON
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LD A,UART1_DIV % $100
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OUT (UART1_DLL),A ; SET DIVISOR (LS)
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LD A,UART1_DIV / $100
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OUT (UART1_DLM),A ; SET DIVISOR (MS)
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LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
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#IF (UART1AFC)
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PRTS(" AFC$")
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LD A,$55 ; TEST VALUE
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OUT (UART1_SCR),A ; SET SCRATCH REG TO TEST VALUE
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LD A,0BFH
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OUT (UART1_LCR),A ; SET LCR=$BF TO ATTEMPT TO ACCESS EFR
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IN A,(UART1_SCR) ; READ SCRATCH REGISTER
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CP $55 ; IF $55, NO EFR
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JR NZ,UART1_AFC1 ; NZ, HAVE EFR, DO IT
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SET 5,B ; ENABLE AUTO FLOW CONTROL
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JR UART1_AFC2
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UART1_AFC1:
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LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
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OUT (UART1_EFR),A ; SAVE IT
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UART1_AFC2:
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#ENDIF
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LD A,03H
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OUT (UART1_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
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LD A,B ; LOAD MCR VALUE TO SET
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OUT (UART1_MCR),A ; SAVE IT
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#IF (UART1FIFO)
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; LD A,07H ; ENABLE AND RESET FIFOS
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LD A,01H ; ENABLE AND RESET FIFOS
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OUT (UART1_FCR),A ; ENABLE FIFOS
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PRTS(" FIFO$")
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#ENDIF
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RET
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;
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;
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;
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UART1_DISPATCH:
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LD A,B ; GET REQUESTED FUNCTION
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AND $0F ; ISOLATE SUB-FUNCTION
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JP Z,UART1_IN
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DEC A
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JP Z,UART1_OUT
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DEC A
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JP Z,UART1_IST
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DEC A
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JP Z,UART1_OST
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CALL PANIC
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;
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;
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;
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UART1_IN:
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CALL UART1_IST
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OR A
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JR Z,UART1_IN
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IN A,(UART1_RBR) ; READ THE CHAR FROM THE UART
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LD E,A
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RET
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;
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;
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;
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UART1_IST:
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IN A,(UART1_LSR) ; READ LINE STATUS REGISTER
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AND $01 ; TEST IF DATA IN RECEIVE BUFFER
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL CHAR READY, A = 1
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RET
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;
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;
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;
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UART1_OUT:
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CALL UART1_OST
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OR A
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JR Z,UART1_OUT
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LD A,E
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OUT (UART1_THR),A ; THEN WRITE THE CHAR TO UART
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RET
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;
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UART1_OST:
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IN A,(UART1_LSR) ; READ LINE STATUS REGISTER
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AND $20
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JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
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XOR A
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INC A ; SIGNAL BUFFER EMPTY, A = 1
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RET
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;
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#ENDIF
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