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106 lines
3.0 KiB
106 lines
3.0 KiB
;
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;=======================================================================
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; HDIAG UART Driver
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;=======================================================================
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;
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; Assumes the UART conventions for SBC/MBC/Zeta, base port at $68.
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; Assuming a UART clock frequency of 1.8432 MHz, the baud rate
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; will be 38400.
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;
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uart_iob .equ $68
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uart_osc .equ 1843200
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uart_baudrate .equ 38400
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uart_divisor .equ uart_osc / uart_baudrate / 16
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;
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uart_rbr .equ uart_iob + 0 ; dlab=0: rcvr buffer reg (read only)
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uart_thr .equ uart_iob + 0 ; dlab=0: xmit holding reg (write only)
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uart_ier .equ uart_iob + 1 ; dlab=0: int enable reg
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uart_iir .equ uart_iob + 2 ; int ident register (read only)
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uart_fcr .equ uart_iob + 2 ; fifo control reg (write only)
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uart_lcr .equ uart_iob + 3 ; line control reg
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uart_mcr .equ uart_iob + 4 ; modem control reg
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uart_lsr .equ uart_iob + 5 ; line status reg
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uart_msr .equ uart_iob + 6 ; modem status reg
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uart_scr .equ uart_iob + 7 ; scratch register
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uart_dll .equ uart_iob + 0 ; dlab=1: divisor latch (ls)
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uart_dlm .equ uart_iob + 1 ; dlab=1: divisor latch (ms)
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;
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;
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;
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uart_jptbl:
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jp uart_cinit ; Initialize serial port
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jp uart_cin ; Read byte
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jp uart_cout ; Write byte
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jp uart_cist ; Input status
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jp uart_cost ; Output Status
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;
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;
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;
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uart_cinit:
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; Test for existence
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xor a ; zero accum
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out (uart_ier),a ; ier := 0
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ld a,$80 ; dlab bit on
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out (uart_lcr),a ; output to lcr (dlab regs now active)
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ld a,$5A ; load test value
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out (uart_dlm),a ; output to dlm
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in a,(uart_dlm) ; read it back
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cp $5A ; check for test value
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ret nz ; nope, unknown uart or not present
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xor a ; dlab bit off
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out (uart_lcr),a ; output to lcr (dlab regs now inactive)
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in a,(uart_ier) ; read ier
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cp $5A ; check for test value
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jr nz,uart_cinit1 ; if *not* $5A, good to go
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or $FF ; signal error
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ret ; done
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;
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uart_cinit1:
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ld a,$80 ; lcr := dlab on
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out (uart_lcr),a ; set lcr
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ld a,uart_divisor & $ff ; low byte of divisor
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out (uart_dll),a ; set divisor (lsb)
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ld a,uart_divisor / $100 ; high byte of divisor
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out (uart_dlm),a ; set divisor (msb)
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xor a ; zero accum
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out (uart_ier),a ; init ier (no ints)
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ld a,$03 ; value for lcr and mcr
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out (uart_lcr),a ; lcr := 3, dlab off, 8 data, 1 stop, no parity
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out (uart_mcr),a ; mcr := 3, dtr on, rts on
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ld a,$07 ; enable & reset fifo's
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out (uart_fcr),a ; do it
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xor a ; signal success
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ret
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;
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;
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;
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uart_cin:
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call uart_cist ; received char ready?
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jr z,uart_cin ; loop if not
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in a,(uart_rbr) ; read byte
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ret ; and done
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;
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;
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;
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uart_cout:
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push af ; save incoming
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uart_cout1:
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call uart_cost ; ready for char?
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jr z,uart_cout1 ; loop if not
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pop af ; restore incoming
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out (uart_thr),a ; write byte
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ret ; and done
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;
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;
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;
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uart_cist:
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in a,(uart_lsr) ; get status
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and $01 ; isolate bit 0 (receive data ready)
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ret ; a != 0 if char ready, else 0
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;
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;
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;
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uart_cost:
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in a,(uart_lsr) ; get status
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and $20 ; isolate bit 5
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ret ; a != 0 if char ready, else 0
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