mirror of https://github.com/wwarthen/RomWBW.git
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
146 lines
4.0 KiB
146 lines
4.0 KiB
ROM Page 0
|
|
----------
|
|
|
|
Loc Org Size File Contents
|
|
|
|
0000 0000 0100 pgzero Page Zero
|
|
0100 0100 0100 bootrom ROM Bootstrap
|
|
0200 0100 0200 syscfg System Configuration
|
|
0400 8400 0C00 loader Loader
|
|
1000 1000 3000 romfill Filler (for future use?)
|
|
4000 C000 1000 dbgmon Debug Monitor
|
|
5000 D000 0800 <ccp> Command Processor (CCP, ZCPR, etc.)
|
|
5800 D800 0E00 <dos> Disk Operating System (BDOS, ZSDOS, etc.)
|
|
6600 E600 1900 cbios CP/M BIOS
|
|
7F00 FF00 0100 hbfill Filler for HBIOS Proxy (HiMem Stub)
|
|
----
|
|
8000H = 32768
|
|
|
|
|
|
ROM Page 1
|
|
----------
|
|
|
|
Loc Org Size File Contents
|
|
|
|
0000 0000 0100 pgzero Page Zero
|
|
0100 0100 0100 bootrom Reserved (unused, 'bootrom' used as filler)
|
|
0200 0200 0200 syscfg System Configuration
|
|
0400 0400 0C00 loader Reserved (unused, 'loader' used as filler)
|
|
1000 1000 7000 bnk1 Bank 1 BIOS Extension
|
|
----
|
|
8000H = 32768
|
|
|
|
|
|
COM File Image
|
|
--------------
|
|
|
|
Loc Org Size File Contents
|
|
|
|
0100 0100 0100 bootapp Application Bootstrap
|
|
0200 0200 0200 syscfg System Configuration
|
|
0400 8400 0C00 loader Loader
|
|
1000 1000 7000 bnk1 Bank 1 BIOS Extension
|
|
|
|
8000 C000 1000 dbgmon Debug Monitor
|
|
9000 D000 0800 <ccp> Command Processor (CCP, ZCPR, etc.)
|
|
9800 D800 0E00 <dos> Disk Operating System (BDOS, ZSDOS, etc.)
|
|
A600 E600 1900 cbios CP/M BIOS
|
|
----
|
|
BF00H - 0100H = BE00H = 48640
|
|
|
|
|
|
RAM Page 0
|
|
----------
|
|
|
|
Loc Org Size Contents
|
|
|
|
0000 0000 0100 Page Zero
|
|
0100 0100 7F00 TPA
|
|
----
|
|
8000H = 32768
|
|
|
|
|
|
RAM Page 1
|
|
----------
|
|
|
|
Loc Org Size Contents
|
|
|
|
0000 0000 0100 Page Zero
|
|
0100 0100 0100 Reserved (unused)
|
|
0200 0200 0200 System Configuration (dynamic)
|
|
0400 0400 0C00 Command processor cache area
|
|
1000 1000 7000 Bank 1 BIOS Extension
|
|
----
|
|
8000H = 32768
|
|
|
|
|
|
RAM Page N
|
|
----------
|
|
|
|
Loc Org Size Contents
|
|
|
|
8000 8000 TPA
|
|
C000 C000 1000 TPA/Debug Monitor
|
|
D000 D000 0800 Command Processor
|
|
D800 D800 0E00 Disk Operating System
|
|
E600 E600 1900 CP/M CBIOS
|
|
FF00 FF00 0100 HBIOS Proxy (HiMem Stub)
|
|
----
|
|
10000H - 8000H = 8000H = 32768
|
|
|
|
General Startup Strategy
|
|
------------------------
|
|
|
|
A two phase boot strategy is employed. This is necessary
|
|
because at cold start, the CPU is executing code in lower
|
|
memory which is the same area that is bank switched.
|
|
|
|
Phase 1 of booting copies phase 2 code to upper memory
|
|
and jumps to it to continue the boot process.
|
|
|
|
Phase 2 of booting manages the setup of the RAM page
|
|
banks as needed. In the case of a hardware startup,
|
|
phase 2 just copies the code from ROM page 1 into RAM
|
|
page 1 and executes the loader. In the case of an
|
|
application startup (.com file used to load a new
|
|
copy of the system), phase 2 copies the first 32KB
|
|
of the application memory space into RAM page 1
|
|
and executes the loader.
|
|
|
|
See 'bootrom.asm' for the implementation of the ROM
|
|
(hardware) startup. See 'bootapp' for the implementation
|
|
of the application based startup.
|
|
|
|
General Design Strategy
|
|
-----------------------
|
|
|
|
The design goal is to locate as much of the hardware
|
|
dependent code as possible out of normal 64KB CP/M
|
|
address space and into a bank switched area of memory.
|
|
As calls are made to HBIOS, the lower 32KB of memory
|
|
is switched to 'bank 1' which contains all of the
|
|
driver code. The operating system is unaware this
|
|
has occurred. As control is returned to the Operating
|
|
System, the lower 32KB of memory is switched back to
|
|
normal 'bank 0'.
|
|
|
|
HBIOS implements a small 'shim' (proxy) that lives in the
|
|
upper page (256 bytes) of RAM. This shim is responsible
|
|
for handling the HBIOS call invocations. It is the
|
|
target of 'RST 08' and will simply switch in RAM
|
|
bank 1 into lower RAM forward the call to the lower
|
|
memory, then switch lower memory back to RAM bank 0
|
|
on return.
|
|
|
|
In the case of CP/M and ZSDOS, CBIOS is built to
|
|
utilize HBIOS for most of the work. CBIOS contains
|
|
the required CP/M data structures such as DPH and DPB
|
|
and is responsible for translating and forwarding work
|
|
to HBIOS as needed.
|
|
|
|
Notes
|
|
-----
|
|
|
|
1. Size of ROM disk and RAM disk will necessarily be
|
|
decreased by 32KB each. User will need to make sure
|
|
that RAM disk is reformatted (CLRDIR).
|