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141 lines
5.1 KiB
141 lines
5.1 KiB
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; MARK IV HARDWARE DEFINITIONS
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;
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CPU_BASE .EQU $40 ; ONLY RELEVANT FOR Z180
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;
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RAMBIAS .EQU 512 ; RAM STARTS AT 512K
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;
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MK4_BASE .EQU $80
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;
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MK4_IDE .EQU MK4_BASE + $00 ; IDE REGISTERS ($00-$07, $0E-$0F)
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MK4_XAR .EQU MK4_BASE + $08 ; EXTERNAL ADDRESS REGISTER (XAR)
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MK4_SD .EQU MK4_BASE + $09 ; SD CARD CONTROL REGISTER
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MK4_RTC .EQU MK4_BASE + $0A ; RTC INTERFACE REGISTER
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;
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RTC .EQU MK4_RTC ; GENERIC ALIAS FOR RTC PORT
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;
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; DUMMY VALUES BELOW TO ALLOW DBGMON TO BUILD...
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; NEED TO REMOVE AND CLEAN THIS UP LATER.
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;
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PPIBASE .EQU $00
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PPIA .EQU PPIBASE + 0 ; PORT A
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PPIB .EQU PPIBASE + 1 ; PORT B
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PPIC .EQU PPIBASE + 2 ; PORT C
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
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;
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; MEMORY BANK CONFIGURATION
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;
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#IF (PLATFORM == PLT_UNA)
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BID_BOOT .EQU $00 ; HARDWARE COLD BOOT (SETUP)
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; .EQU $01 ; UNA BIOS
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BID_COMIMG .EQU $02 ; LOADER + CP/M IMAGE TO COPY TO BID_COM
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; .EQU $03 ; UNA FATFS DRIVER
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BID_HBIMG .EQU $00 ; NO HBIOS IMAGE FOR UNA
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BID_ROMD .EQU $05 ; FIRST ROM DRIVE BANK
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BID_ROMDN .EQU $0F ; LAST ROM DRIVE BANK
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BID_RAMD .EQU $10 ; START OF RAM DRIVE
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BID_RAMDN .EQU $1B ; LAST RAM DRIVE BANK
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BID_BPB .EQU $1C ; RESERVED FOR BPBIOS BANK
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BID_HB .EQU $00 ; NO HBIOS FOR UNA
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; .EQU $1D ; SHADOW COPY OF UNABIOS IN RAM
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BID_USR .EQU $1E ; LOW 32K OF TPA
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BID_COM .EQU $1F ; COMMON BANK, UPPER 32K
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#ELSE
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#IFDEF UNALOAD
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BID_BOOT .EQU $00 ; HARDWARE COLD BOOT (SETUP)
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BID_COMIMG .EQU $02 ; LOADER + CP/M IMAGE TO COPY TO BID_COM
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BID_HBIMG .EQU $04 ; HBIOS IMAGE TO COPY TO BID_HB
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BID_ROMD .EQU $05 ; FIRST ROM DRIVE BANK
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#ELSE
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BID_BOOT .EQU $00 ; HARDWARE COLD BOOT (SETUP)
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BID_COMIMG .EQU $00 ; LOADER + CP/M IMAGE TO COPY TO BID_COM
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BID_HBIMG .EQU $01 ; HBIOS IMAGE TO COPY TO BID_HB
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BID_ROMD .EQU $02 ; FIRST ROM DRIVE BANK
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#ENDIF
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BID_ROMDN .EQU ($00 + ((ROMSIZE / 32) - 1)) ; LAST ROM DRIVE BANK
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BID_USR .EQU $10 ; LOW 32K OF TPA
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BID_HB .EQU $11 ; WORKING COPY OF HBIOS IN RAM
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BID_BPB .EQU $12 ; BPBIOS BANK
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BID_RAMD .EQU $13 ; START OF RAM DRIVE
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BID_RAMDN .EQU ($10 + ((RAMSIZE / 32) - 2)) ; LAST RAM DRIVE BANK
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BID_COM .EQU $1F ; COMMON BANK, UPPER 32K
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#ENDIF
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;
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; Z180 REGISTERS
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;
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CPU_CNTLA0 .EQU CPU_BASE + $00 ; ASCI0 CONTROL A
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CPU_CNTLA1 .EQU CPU_BASE + $01 ; ASCI1 CONTROL A
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CPU_CNTLB0 .EQU CPU_BASE + $02 ; ASCI0 CONTROL B
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CPU_CNTLB1 .EQU CPU_BASE + $03 ; ASCI1 CONTROL B
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CPU_STAT0 .EQU CPU_BASE + $04 ; ASCI0 STATUS
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CPU_STAT1 .EQU CPU_BASE + $05 ; ASCI1 STATUS
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CPU_TDR0 .EQU CPU_BASE + $06 ; ASCI0 TRANSMIT
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CPU_TDR1 .EQU CPU_BASE + $07 ; ASCI1 TRANSMIT
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CPU_RDR0 .EQU CPU_BASE + $08 ; ASCI0 RECEIVE
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CPU_RDR1 .EQU CPU_BASE + $09 ; ASCI1 RECEIVE
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CPU_CNTR .EQU CPU_BASE + $0A ; CSI/O CONTROL
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CPU_TRDR .EQU CPU_BASE + $0B ; CSI/O TRANSMIT/RECEIVE
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CPU_TMDR0L .EQU CPU_BASE + $0C ; TIMER 0 DATA LO
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CPU_TMDR0H .EQU CPU_BASE + $0D ; TIMER 0 DATA HI
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CPU_RLDR0L .EQU CPU_BASE + $0E ; TIMER 0 RELOAD LO
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CPU_RLDR0H .EQU CPU_BASE + $0F ; TIMER 0 RELOAD HI
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CPU_TCR .EQU CPU_BASE + $10 ; TIMER CONTROL
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;
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CPU_ASEXT0 .EQU CPU_BASE + $12 ; ASCI0 EXTENSION CONTROL (Z8S180)
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CPU_ASEXT1 .EQU CPU_BASE + $13 ; ASCI1 EXTENSION CONTROL (Z8S180)
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;
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CPU_TMDR1L .EQU CPU_BASE + $14 ; TIMER 1 DATA LO
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CPU_TMDR1H .EQU CPU_BASE + $15 ; TIMER 1 DATA HI
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CPU_RLDR1L .EQU CPU_BASE + $16 ; TIMER 1 RELOAD LO
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CPU_RLDR1H .EQU CPU_BASE + $17 ; TIMER 1 RELOAD HI
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CPU_FRC .EQU CPU_BASE + $18 ; FREE RUNNING COUNTER
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CPU_ASTC0L .EQU CPU_BASE + $1A ; ASCI0 TIME CONSTANT LO (Z8S180)
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CPU_ASTC0H .EQU CPU_BASE + $1B ; ASCI0 TIME CONSTANT HI (Z8S180)
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CPU_ASTC1L .EQU CPU_BASE + $1C ; ASCI1 TIME CONSTANT LO (Z8S180)
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CPU_ASTC1H .EQU CPU_BASE + $1D ; ASCI1 TIME CONSTANT HI (Z8S180)
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CPU_CMR .EQU CPU_BASE + $1E ; CLOCK MULTIPLIER (LATEST Z8S180)
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CPU_CCR .EQU CPU_BASE + $1F ; CPU CONTROL (Z8S180)
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;
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CPU_SAR0L .EQU CPU_BASE + $20 ; DMA0 SOURCE ADDR LO
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CPU_SAR0H .EQU CPU_BASE + $21 ; DMA0 SOURCE ADDR HI
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CPU_SAR0B .EQU CPU_BASE + $22 ; DMA0 SOURCE ADDR BANK
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CPU_DAR0L .EQU CPU_BASE + $23 ; DMA0 DEST ADDR LO
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CPU_DAR0H .EQU CPU_BASE + $24 ; DMA0 DEST ADDR HI
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CPU_DAR0B .EQU CPU_BASE + $25 ; DMA0 DEST ADDR BANK
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CPU_BCR0L .EQU CPU_BASE + $26 ; DMA0 BYTE COUNT LO
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CPU_BCR0H .EQU CPU_BASE + $27 ; DMA0 BYTE COUNT HI
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CPU_MAR1L .EQU CPU_BASE + $28 ; DMA1 MEMORY ADDR LO
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CPU_MAR1H .EQU CPU_BASE + $29 ; DMA1 MEMORY ADDR HI
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CPU_MAR1B .EQU CPU_BASE + $2A ; DMA1 MEMORY ADDR BANK
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CPU_IAR1L .EQU CPU_BASE + $2B ; DMA1 I/O ADDR LO
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CPU_IAR1H .EQU CPU_BASE + $2C ; DMA1 I/O ADDR HI
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CPU_IAR1B .EQU CPU_BASE + $2D ; DMA1 I/O ADDR BANK (Z8S180)
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CPU_BCR1L .EQU CPU_BASE + $2E ; DMA1 BYTE COUNT LO
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CPU_BCR1H .EQU CPU_BASE + $2F ; DMA1 BYTE COUNT HI
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CPU_DSTAT .EQU CPU_BASE + $30 ; DMA STATUS
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CPU_DMODE .EQU CPU_BASE + $31 ; DMA MODE
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CPU_DCNTL .EQU CPU_BASE + $32 ; DMA/WAIT CONTROL
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CPU_IL .EQU CPU_BASE + $33 ; INTERRUPT VECTOR LOAD
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CPU_ITC .EQU CPU_BASE + $34 ; INT/TRAP CONTROL
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;
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CPU_RCR .EQU CPU_BASE + $36 ; REFRESH CONTROL
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;
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CPU_CBR .EQU CPU_BASE + $38 ; MMU COMMON BASE REGISTER
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CPU_BBR .EQU CPU_BASE + $39 ; MMU BANK BASE REGISTER
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CPU_CBAR .EQU CPU_BASE + $3A ; MMU COMMON/BANK AREA REGISTER
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;
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CPU_OMCR .EQU CPU_BASE + $3E ; OPERATION MODE CONTROL
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CPU_ICR .EQU $3F ; I/O CONTROL REGISTER (NOT RELOCATED!!!)
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