forked from MirrorRepos/RomWBW
Wayne Warthen
2 years ago
50 changed files with 882 additions and 43 deletions
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@ -0,0 +1,4 @@ |
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@echo off |
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setlocal |
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|
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pushd FZ80 && call Build || exit /b & popd |
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@ -0,0 +1,18 @@ |
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FPGA Z80 has no real ROM. It has a single 512K RAM chip. |
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The ROMless startup mode treats the entire 512KB as RAM. 384KB of RAM |
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must be preloaded by the FPGA Monitor CF Loader. There will be no ROM |
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disk available under RomWBW. There will be a RAM Disk and it's initial |
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contents will be seeded by the image loaded by the CF Loader. |
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|
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Bank Contents Description |
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-------- -------- ----------- |
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0x0 BIOS HBIOS Bank (operating) |
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0x1 IMG0 ROM Loader, Monitor, ROM OSes |
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0x2 IMG1 ROM Applications |
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0x3 IMG2 Reserved |
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0x4-0xB RAMD RAM Disk Banks |
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0xC BUF OS Buffers (CP/M3) |
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0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.) |
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0xE USR User Bank (CP/M TPA, etc.) |
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0xF COM Common Bank, Upper 32KB |
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@ -0,0 +1,21 @@ |
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@echo off |
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setlocal |
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set TOOLS=../../Tools |
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set PATH=%TOOLS%\srecord;%PATH% |
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if exist ..\..\Binary\FZ80_std.rom call :build_fz80 |
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goto :eof |
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:build_fz80 |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\FZ80_std.rom -binary -offset 0x80000 -o temp.dat -binary |
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move temp.dat ..\..\Binary\hd1k_fz80_prefix.dat |
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copy /b ..\..\Binary\hd1k_fz80_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_fz80_combo.img || exit /b |
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goto :eof |
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@ -0,0 +1,3 @@ |
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@echo off |
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setlocal |
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@ -0,0 +1,19 @@ |
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FZ80 Disk Prefix Layout |
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======================= |
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|
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---- Bytes ---- --- Sectors --- |
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Start Length Start Length Description |
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------- ------- ------- ------- --------------------------- |
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0x00000 0x001BE 0 1 Unused |
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0x001B8 0x00048 RomWBW Partition Table |
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0x00200 0x1EE00 1 7FE00 Unused |
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0x80000 0x60000 1024 768 RomWBW |
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0x100000 2048 Start of slices (partition 0x1E) |
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Notes |
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----- |
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|
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- FPGA Z80 Monitor reads 384KB (RomWBW) from sectors 1024-1791 of CF into first 384KB of physical RAM |
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- FPGA Z80 ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000 |
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|
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-- WBW 3:18 PM 6/30/2024 |
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@ -0,0 +1,24 @@ |
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HD1KFZ80PREFIX = hd1k_fz80_prefix.dat |
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HD1KFZ80COMBOIMG = hd1k_fz80_combo.img |
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FZ80ROM = ../../Binary/FZ80_std.rom |
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HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
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../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img |
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OBJECTS := $(HD1KFZ80PREFIX) $(HD1KFZ80COMBOIMG) |
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DEST=../../Binary |
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TOOLS = ../../Tools |
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include $(TOOLS)/Makefile.inc |
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DIFFPATH = $(DIFFTO)/Binary |
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$(HD1KFZ80PREFIX): |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $(FZ80ROM) -binary -offset 0x80000 -o temp.dat -binary |
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mv temp.dat $@ |
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$(HD1KFZ80COMBOIMG): $(HD1KFZ80PREFIX) $(HD1KIMGS) |
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cat $^ > $@ |
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@ -0,0 +1,27 @@ |
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; |
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;================================================================================================== |
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; S100 FPGZ Z80 STANDARD CONFIGURATION |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT |
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; |
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#include "cfg_fz80.asm" |
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@ -0,0 +1,347 @@ |
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; |
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;================================================================================================== |
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; ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 FPGA Z80 |
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;================================================================================================== |
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; |
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; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD |
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; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY |
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; UNDER THIS DIRECTORY. |
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; |
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; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS |
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; FOR THE PLATFORM. |
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; |
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#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]" |
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; |
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#INCLUDE "hbios.inc" |
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; |
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PLATFORM .EQU PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] |
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CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] |
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) |
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USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION |
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) |
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; |
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE |
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BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT |
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AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT |
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; |
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CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO |
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CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW |
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CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ |
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INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) |
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DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) |
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; |
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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ROMSIZE .EQU 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) |
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MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] |
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MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) |
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MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) |
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; |
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RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR |
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; |
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT |
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS |
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; |
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT |
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT |
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CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS |
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CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER |
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CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] |
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CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) |
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CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) |
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CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) |
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CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY |
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; |
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PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER |
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PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS |
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; |
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EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES |
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SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K |
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; |
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WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] |
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WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR |
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; |
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FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS |
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FPLED_IO .EQU $FF ; FP: PORT ADDRESS FOR FP LEDS |
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FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED |
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FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS |
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FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES |
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FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES |
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FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED |
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; |
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DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING |
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; |
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LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) |
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LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] |
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LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS |
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LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
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; |
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DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY |
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DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY |
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ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) |
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ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI |
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PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) |
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PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI |
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PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) |
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H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL |
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; |
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BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE |
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SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE |
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CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
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VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
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VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD |
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ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
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PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] |
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MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) |
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MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] |
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; |
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DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
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DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] |
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DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
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; |
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DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) |
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DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS |
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; |
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BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
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BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS |
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; |
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INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) |
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; |
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RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) |
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; |
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HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT |
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SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
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; |
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) |
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] |
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; |
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SSERENABLE .EQU TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) |
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG |
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SSERSTATUS .EQU $34 ; SSER: STATUS PORT |
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SSERDATA .EQU $35 ; SSER: DATA PORT |
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SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK |
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SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED |
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SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK |
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SSEROINV .EQU TRUE ; SSER: OUTPUT READY BIT INVERTED |
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; |
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DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) |
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DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) |
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DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP |
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DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG |
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DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG |
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DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP |
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DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG |
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DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG |
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; |
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UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ |
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UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 |
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UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS |
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UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART |
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UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) |
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UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART |
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UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART |
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UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART |
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UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART |
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UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART |
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UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART |
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; |
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ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
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; |
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Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) |
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; |
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ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
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ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT |
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ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) |
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ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR |
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ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ |
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ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER |
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ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) |
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ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR |
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ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ |
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ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER |
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ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) |
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; |
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SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT |
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SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) |
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SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
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SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR |
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SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG |
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG |
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] |
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SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR |
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SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG |
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SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG |
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SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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; |
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG |
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; |
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VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
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CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
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GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) |
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TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
|||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] |
|||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
|||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
|||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) |
|||
SCONENABLE .EQU TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) |
|||
EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
|||
; |
|||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
|||
MDROM .EQU FALSE ; MD: ENABLE ROM DISK |
|||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK |
|||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM |
|||
; |
|||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
|||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] |
|||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) |
|||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
|||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
|||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
|||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] |
|||
; |
|||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
|||
; |
|||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
|||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH |
|||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] |
|||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS |
|||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O |
|||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O |
|||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER |
|||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER |
|||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] |
|||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS |
|||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O |
|||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O |
|||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER |
|||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER |
|||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] |
|||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS |
|||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O |
|||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O |
|||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER |
|||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER |
|||
; |
|||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP |
|||
PPIDE0BASE .EQU $30 ; PPIDE 0: PPI REGISTERS BASE ADR |
|||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER |
|||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR |
|||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER |
|||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR |
|||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER |
|||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
; |
|||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
|||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] |
|||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE |
|||
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY |
|||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
|||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 |
|||
; |
|||
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT |
|||
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) |
|||
CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS |
|||
CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK |
|||
CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK |
|||
CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS |
|||
CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK |
|||
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK |
|||
; |
|||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
|||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT |
|||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT |
|||
; |
|||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
|||
; |
|||
ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) |
|||
; |
|||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
|||
; |
|||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) |
|||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
|||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR |
|||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR |
|||
; |
|||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) |
|||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] |
|||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) |
|||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR |
|||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR |
|||
; |
|||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) |
|||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) |
|||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] |
|||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA |
|||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA |
|||
; |
|||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) |
|||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) |
|||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] |
|||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM |
|||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM |
|||
; |
|||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) |
|||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) |
|||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] |
|||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ |
|||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ |
|||
; |
|||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
|||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
|||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
|||
; |
|||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
|||
; |
|||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER |
|||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER |
|||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD |
|||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] |
|||
; |
|||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER |
|||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD |
|||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] |
|||
; |
|||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
|||
; |
|||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) |
|||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS |
|||
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) |
|||
; |
|||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER |
|||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) |
|||
@ -0,0 +1,126 @@ |
|||
; |
|||
;================================================================================================== |
|||
; SIMPLE SERIAL DRIVER |
|||
;================================================================================================== |
|||
; |
|||
; TODO: |
|||
; |
|||
;;;;SSER_IOBASE .EQU $34 |
|||
;;;;; |
|||
;;;;SSER_STATUS .EQU SSER_IOBASE |
|||
;;;;SSER_DATA .EQU SSER_IOBASE + 1 |
|||
;;;;; |
|||
;;;;SSER_IRDY .EQU %00000001 |
|||
;;;;SSER_IINV .EQU FALSE |
|||
;;;;SSER_ORDY .EQU %00000010 |
|||
;;;;SSER_OINV .EQU TRUE |
|||
; |
|||
DEVECHO "SSER: IO=" |
|||
DEVECHO SSERSTATUS |
|||
DEVECHO "\n" |
|||
; |
|||
; |
|||
; |
|||
SSER_PREINIT: |
|||
; |
|||
; ADD OURSELVES TO CIO DISPATCH TABLE |
|||
; |
|||
LD D,0 ; PHYSICAL UNIT IS ZERO |
|||
LD E,CIODEV_SSER ; DEVICE TYPE |
|||
LD BC,SSER_FNTBL ; BC := FUNCTION TABLE ADDRESS |
|||
CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED |
|||
; |
|||
XOR A |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
SSER_INIT: |
|||
CALL NEWLINE |
|||
PRTS("SSER$") |
|||
PRTS(": IO=0x$") ; FORMATTING |
|||
LD A,SSERSTATUS |
|||
CALL PRTHEXBYTE |
|||
; |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
; |
|||
; DRIVER FUNCTION TABLE |
|||
; |
|||
SSER_FNTBL: |
|||
.DW SSER_IN |
|||
.DW SSER_OUT |
|||
.DW SSER_IST |
|||
.DW SSER_OST |
|||
.DW SSER_INITDEV |
|||
.DW SSER_QUERY |
|||
.DW SSER_DEVICE |
|||
#IF (($ - SSER_FNTBL) != (CIO_FNCNT * 2)) |
|||
.ECHO "*** INVALID SSER FUNCTION TABLE ***\n" |
|||
#ENDIF |
|||
; |
|||
; |
|||
; |
|||
SSER_IN: |
|||
CALL SSER_IST ; CHECK FOR CHAR PENDING |
|||
JR Z,SSER_IN ; WAIT FOR IT IF NECESSARY |
|||
IN A,(SSERDATA) ; READ THE CHAR |
|||
LD E,A |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
SSER_IST: |
|||
IN A,(SSERSTATUS) ; READ LINE STATUS REGISTER |
|||
#IF (SSERIINV) |
|||
CPL |
|||
#ENDIF |
|||
AND SSERIRDY ; ISOLATE DATA READY |
|||
JP Z,CIO_IDLE ; RETURN VIA IDLE PROCESSING |
|||
OR $FF ; SET A=$FF TO SIGNAL READY |
|||
RET ; RETURN |
|||
; |
|||
; |
|||
; |
|||
SSER_OUT: |
|||
CALL SSER_OST ; CHECK FOR OUTPUT READY |
|||
JR Z,SSER_OUT ; WAIT IF NECESSARY |
|||
LD A,E ; RECOVER THE CHAR TO WRITE |
|||
OUT (SSERDATA),A ; WRITE THE CHAR |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
SSER_OST: |
|||
IN A,(SSERSTATUS) ; READ LINE STATUS REGISTER |
|||
#IF (SSEROINV) |
|||
CPL |
|||
#ENDIF |
|||
AND SSERORDY ; ISOLATE OUTPUT RDY |
|||
JP Z,CIO_IDLE ; RETURN VIA IDLE PROCESSING |
|||
OR $FF ; SET A=$FF TO SIGNAL READY |
|||
RET ; RETURN |
|||
; |
|||
; |
|||
; |
|||
SSER_INITDEV: |
|||
SYSCHKERR(ERR_NOTIMPL) |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
SSER_QUERY: |
|||
LD DE,SSERCFG |
|||
XOR A |
|||
RET |
|||
; |
|||
; |
|||
; |
|||
SSER_DEVICE: |
|||
LD D,CIODEV_SSER ; D := DEVICE TYPE |
|||
LD E,0 ; E := DEVICE NUM, ALWAYS 0 |
|||
LD C,$00 ; C := DEVICE TYPE, 0x00 IS RS-232 |
|||
LD H,0 ; H := 0, DRIVER HAS NO MODES |
|||
LD L,SSERSTATUS ; L := BASE I/O ADDRESS |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET |
|||
Loading…
Reference in new issue