SIO & ACIA Driver Updates

7 years ago · 0b661442c5
20 changed files with 957 additions and 1101 deletions
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@ -3,8 +3,9 @@ Version 2.9.2
 - PMS: Fixed DS1210-related issue resulting in "Invalid BIOS" errors
 - SCC: Support for SC126 motherboard
 - WBW: Enable Auto-CTS/DCD in SIO driver for pacing output data
- WBW: Support missing pull-up resistors in SD driver (a common occurence)
+- WBW: Support missing pull-up resistors on SPI SD adapter boards (common)
 - WBW: Support two SIO modules w/ auto-detection
+- PMS: Support ECB USB-FIFO board

 Version 2.9.1
 -------------
--- a/ReadMe.txt
+++ b/ReadMe.txt
@ -7,7 +7,7 @@
 ***********************************************************************

 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.2-pre.1, 2019-07-22
+Version 2.9.2-pre.2, 2019-08-04
 https://www.retrobrewcomputers.org/

 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
--- a/Source/CBIOS/ver.inc
+++ b/Source/CBIOS/ver.inc
@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.1"
+#DEFINE BIOSVER	"2.9.2-pre.2"
--- a/Source/HBIOS/Config/EZZ80_std.asm
+++ b/Source/HBIOS/Config/EZZ80_std.asm
@ -6,4 +6,4 @@
 #include "cfg_ezz80.asm"
 ;
 CPUOSC		.SET	10000000	; CPU OSC FREQ
-DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
+DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
--- a/Source/HBIOS/Config/RCZ180_sc126.asm
+++ b/Source/HBIOS/Config/RCZ180_sc126.asm
@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   RC2014 W/ Z180 CPU USING NATIVE Z180 MEMORY MANAGER
+;   SC126
 ;==================================================================================================
 ;
 #include "cfg_rcz180.asm"
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@ -31,17 +31,23 @@ ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT
 SIODEBUG	.EQU	FALSE		; PS
-DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
-DEFSIOCLK	.EQU	1843200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
-SIOCNT		.EQU	1		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
+SIOCNT		.EQU	2		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
 SIO0MODE	.EQU	SIOMODE_EZZ80	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
-SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+SIO0ACLK	.EQU	1843200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0ADIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO0BCLK	.EQU	1843200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0BDIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
-DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1ACLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO1ADIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1BCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO1BDIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@ -27,6 +27,10 @@ DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
+UARTSBC		.EQU	FALSE		; ENABLE SBC/ZETA ONBOARD UART DETECTION
+UARTCAS		.EQU	TRUE		; ENABLE ECB CASSETTE UART DETECTION
+UARTMFP         .EQU	FALSE		; ENABLE MF/PIC UART DETECTION
+UART4           .EQU	TRUE		; ENABLE 4UART UART DETECTION
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@ -27,6 +27,10 @@ DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
+UARTSBC		.EQU	FALSE		; ENABLE SBC/ZETA ONBOARD UART DETECTION
+UARTCAS		.EQU	TRUE		; ENABLE ECB CASSETTE UART DETECTION
+UARTMFP         .EQU	FALSE		; ENABLE MF/PIC UART DETECTION
+UART4           .EQU	TRUE		; ENABLE 4UART UART DETECTION
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@ -29,19 +29,25 @@ UARTENABLE	.EQU	FALSE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TR
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
-SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO SUPPORT
+SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT
 SIODEBUG	.EQU	FALSE		; PS
-DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
-DEFSIOCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
-SIOCNT		.EQU	1		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
+SIOCNT		.EQU	2		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
 SIO0MODE	.EQU	SIOMODE_RC	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
-SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+SIO0ACLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0ADIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0ACFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+SIO0BCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0BDIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0BCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
-DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1ACLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO1ADIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO1ACFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+SIO1BCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO1BDIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO1BCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@ -27,21 +27,40 @@ DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	FALSE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
+;
 ACIAENABLE	.EQU	TRUE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
+ACIADEBUG	.EQU	FALSE		; PS
+ACIACNT		.EQU	1		; 1 OR 2 ACIA CHIPS
+ACIA0MODE	.EQU	ACIAMODE_RC	; TYPE OF FIRST ACIA TO DETECT: SIOMODE_RC
+ACIA0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST ACIA CHIP
+ACIA0CLK	.EQU	CPUOSC		; 7372800 - ACIA FIXED OSC FREQUENCY
+ACIA0DIV	.EQU	1		; 1=RC2014
+ACIA0CFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+ACIA1MODE	.EQU	ACIAMODE_RC	; TYPE OF SECOND ACIA TO DETECT: SIOMODE_RC
+ACIA1BASE	.EQU	$40		; IO PORT ADDRESS BASE FOR SECOND ACIA CHIP
+ACIA1CLK	.EQU	CPUOSC		; 7372800 - ACIA FIXED OSC FREQUENCY
+ACIA1DIV	.EQU	1		; 1=RC2014
+ACIA1CFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT
 SIODEBUG	.EQU	FALSE		; PS
-DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
-DEFSIOCLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
 SIOCNT		.EQU	2		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
 SIO0MODE	.EQU	SIOMODE_RC	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
-SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+SIO0ACLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0ADIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO0BCLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0BDIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
-DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1ACLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO1ADIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO1BCLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO1BDIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@ -27,21 +27,23 @@ DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
+UARTSBC		.EQU	TRUE		; ENABLE SBC/ZETA ONBOARD UART DETECTION
+UARTCAS		.EQU	TRUE		; ENABLE ECB CASSETTE UART DETECTION
+UARTMFP         .EQU	TRUE		; ENABLE MF/PIC UART DETECTION
+UART4           .EQU	TRUE		; ENABLE 4UART UART DETECTION
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
-SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO SUPPORT
+SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT
 SIODEBUG	.EQU	FALSE		; PS
-DEFSIODIV	.EQU	8		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
-DEFSIOCLK	.EQU	4915200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
 SIOCNT		.EQU	1		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
 SIO0MODE	.EQU	SIOMODE_ZP	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
-;SIO1MODE	.EQU	SIOMODE_ZP	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
 SIO0BASE	.EQU	$B0		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
-;SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
-DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-;DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-;DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO0ACLK	.EQU	4915200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0ADIV	.EQU	8		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIO0BCLK	.EQU	4915200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
+SIO0BDIV	.EQU	8		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+SIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
--- a/Source/HBIOS/cfg_una.asm
+++ b/Source/HBIOS/cfg_una.asm
@ -7,6 +7,7 @@
 ;
 CPUOSC		.EQU	18432000	; CPU OSC FREQ
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
+INTMODE		.EQU	0		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
 ;
 DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
 ;
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@ -27,6 +27,10 @@ DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
+UARTSBC		.EQU	TRUE		; ENABLE SBC/ZETA ONBOARD UART DETECTION
+UARTCAS		.EQU	FALSE		; ENABLE ECB CASSETTE UART DETECTION
+UARTMFP         .EQU	FALSE		; ENABLE MF/PIC UART DETECTION
+UART4           .EQU	FALSE		; ENABLE 4UART UART DETECTION
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
 SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@ -67,10 +67,6 @@ MODCNT	.SET	MODCNT + 1
 ;
 ;
 ;
-;#IF ((PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180))
-;#DEFINE	DIAGPORT	$00
-;#ENDIF
-;
 #IF (DIAGENABLE)
 #DEFINE	DIAG(N)	PUSH AF
  #DEFCONT \	LD A,N
@ -266,7 +262,6 @@ HBX_BNKSEL:
 ;
 HBX_BNKSEL_INT:
 ;
-;#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))
 #IF (MEMMGR == MM_SBC)
  #IF (INTMODE == 1)
 	; THIS BIT OF ABSURDITY HANDLES A RARE (BUT FATAL) SITUATION
@ -291,7 +286,6 @@ HBX_ROM:
 	OUT	(MPCL_ROM),A		; SET ROM PAGE SELECTOR
 	RET				; DONE
 #ENDIF
-;#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_EZZ80))
 #IF (MEMMGR == MM_Z2)
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
@ -306,7 +300,6 @@ HBX_ROM:
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
 	RET				; DONE
 #ENDIF
-;#IF (PLATFORM == PLT_N8)
 #IF (MEMMGR == MM_N8)
 	BIT	7,A			; TEST BIT 7 FOR RAM VS. ROM
 	JR	Z,HBX_ROM		; IF NOT SET, SELECT ROM PAGE
@ -330,7 +323,6 @@ HBX_ROM:
 	RET				; DONE
 ;
 #ENDIF
-;#IF (PLATFORM == PLT_MK4)
 #IF (MEMMGR == MM_Z180)
 	RLCA				; RAM FLAG TO CARRY FLAG AND BIT 0
 	JR	NC,HBX_BNKSEL1		; IF NC, WANT ROM PAGE, SKIP AHEAD
@ -481,43 +473,43 @@ HBX_STACK	.EQU	$
 ;
 #IF (INTMODE == 2)
 ;
-; HBIOS INTERRUPT VECTOR TABLE (16 ENTRIES)
-;
-; #	SBC		N8,MK4		ZETA		ZETA2
-; ---	--------------	--------------	--------------	--------------
-; 0	CTC0A		Z180/INT1			CTC0A/PRESCL
-; 1	CTC0B		Z180/INT2			CTC0B/TIMER
-; 2	CTC0C		Z180/TIM0			CTC0C/UART
-; 3	CTC0D		Z180/TIM1			CTC0D/FDC
-; 4			Z180/DMA0
-; 5			Z180/DMA1
-; 6			Z180/CSIO
-; 7	SIO0		Z180/SER0
-; 8	SIO1		Z180/SER1
-; 9	PIO0A		PIO0A
-; 10	PIO0B		PIO0B
-; 11	PIO1A		PIO1A
-; 12	PIO1B		PIO1B
+; HBIOS INTERRUPT SLOT ASSIGNMENTS
+;
+; #	SBC		ZETA		N8,MK4,RCZ180	
+; ---	--------------	--------------	--------------	
+; 0	CTC0A				Z180/INT1	
+; 1	CTC0B				Z180/INT2	
+; 2	CTC0C				Z180/TIM0	
+; 3	CTC0D				Z180/TIM1	
+; 4					Z180/DMA0
+; 5					Z180/DMA1
+; 6					Z180/CSIO
+; 7	SIO0A/B				Z180/SER0
+; 8	SIO1A/B				Z180/SER1
+; 9	PIO0A				PIO0A
+; 10	PIO0B				PIO0B
+; 11	PIO1A				PIO1A
+; 12	PIO1B				PIO1B
 ; 13
 ; 14
 ; 15
 ; 16
 ;
-; #	RCZ80		RCZ180		EZZ80
-; ---	--------------	--------------	-------------
-; 0	CTC0A		Z180/INT1	CTC0A/SIO0CLK
-; 1	CTC0B		Z180/INT2	CTC0B/SIO1CLK
-; 2	CTC0C		Z180/TIM0	CTC0C/PRESCL
-; 3	CTC0D		Z180/TIM1	CTC0D/TIMER
-; 4			Z180/DMA0
-; 5			Z180/DMA1
-; 6			Z180/CSIO
-; 7	SIO0		Z180/SER0	SIO0
-; 8	SIO1		Z180/SER1	SIO1
-; 9	PIO0A		PIO0A		PIO0A
-; 10	PIO0B		PIO0B		PIO0B
-; 11	PIO1A		PIO1A		PIO1A
-; 12	PIO1B		PIO1B		PIO1B
+; #	RCZ80		EZZ80		ZETA2
+; ---	--------------	-------------   --------------
+; 0	CTC0A		CTC0A/SIO0CLK   CTC0A/PRESCL
+; 1	CTC0B		CTC0B/SIO1CLK   CTC0B/TIMER
+; 2	CTC0C		CTC0C/PRESCL    CTC0C/UART
+; 3	CTC0D		CTC0D/TIMER     CTC0D/FDC
+; 4			
+; 5			
+; 6			
+; 7	SIO0A/B		SIO0A/B
+; 8	SIO1A/B		SIO1A/B
+; 9	PIO0A		PIO0A
+; 10	PIO0B		PIO0B
+; 11	PIO1A		PIO1A
+; 12	PIO1B		PIO1B
 ; 13
 ; 14
 ; 15
@ -570,36 +562,6 @@ INT_IM1:
 	RETI				; UNEXPECTED INT, RET W/ INTS LEFT DISABLED
 #ENDIF
 ;
-; *** INTERRUPT HANDLER STUBS ARE DEPRECATED!!!!
-; NO LONGER NEEDED NOR SUPPORTED
-; 
-; INTERRUPT HANDLER STUBS
-;
-; THE FOLLOWING INTERRUPT STUBS RECEIVE CONTROL FROM THE
-; INTERRUPT, SETUP A HANDLER VECTOR IN HBIOS AND THEN
-; BRANCH TO THE COMMON INTERRUPT DISPATCHER
-;
-;#IF (INTMODE == 2)
-;;
-;INT_BAD:	; BAD INTERRUPT HANDLER
-;	PUSH	HL			; SAVE HL
-;	LD	HL,HB_BADINT		; HL := INT HANDLER IN BIOS BANK
-;	JR	HBX_INT			; GO TO ROUTING CODE
-;;
-;INT_TIMER:	; TIMER INTERRUPT HANDLER
-;	PUSH	HL			; SAVE HL
-;	LD	HL,HB_TIMINT		; HL := INT ADR IN BIOS
-;	JR	HBX_INT			; GO TO ROUTING CODE
-;;
-;  #IF (SIOENABLE)
-;INT_SIO:	; SIO INTERRUPT HANDLER
-;	PUSH	HL			; SAVE HL
-;	LD	HL,SIO_INT		; HL := SIO INT HANDLER IN BIOS BANK
-;	JR	HBX_INT			; GO TO ROUTING CODE
-;  #ENDIF
-;;
-;#ENDIF
-;
 #IF (INTMODE > 0)
 ;
 ; COMMON INTERRUPT DISPATCHING CODE
@ -781,7 +743,7 @@ HB_START:
 ;
 	LD	SP,HBX_LOC		; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	; SET BASE FOR CPU IO REGISTERS
 	LD	A,Z180_BASE
 	OUT0	(Z180_ICR),A
@ -805,7 +767,6 @@ HB_START:
 	LD	A,$F0
 	OUT0	(Z180_DCNTL),A

-;#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
 #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
 	; MMU SETUP
 	LD	A,$80
@ -832,7 +793,6 @@ HB_START:

 #ENDIF
 ;
-;#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_EZZ80))
 #IF (MEMMGR == MM_Z2)
 	; SET PAGING REGISTERS
 #IFDEF ROMBOOT
@ -987,7 +947,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 ;
 	LD	HL,0		; L = 0 MEANS Z80
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 ;
 	; TEST FOR ORIGINAL Z180 USING MLT
 	LD	DE,$0506	; 5 X 6
@ -997,13 +957,13 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	JR	NZ,HB_CPU1	; IT IS A Z80 IF != 30
 	INC	L		; FLAG Z80180 OR BETTER
 ;
-	; TEST FOR OLDER S-CLASS
+	; TEST FOR OLDER S-CLASS (REV K)
        IN0     A,(Z180_CCR)	; SUPPOSEDLY ONLY ON S-CLASS
        INC     A		; FF -> 0
 	JR	Z,HB_CPU1
 	INC	L		; FLAG Z8S180 REV K (SL1960) OR BETTER
 ;
-	; TEST FOR NEWER S-CLASS
+	; TEST FOR NEWER S-CLASS (REV N)
        OUT0    (Z180_ASTC1L),D	; D = 0 AT THIS POINT
        IN0     A,(Z180_ASTC1L)	; COUNTER REG
        INC     A		; FF -> 0
@ -1020,7 +980,7 @@ HB_CPU1:
 ;
 	CALL	HB_CPUSPD		; CPU SPEED DETECTION
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 ;
 	; SET DESIRED WAIT STATES
 	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
@ -1057,25 +1017,26 @@ HB_CPU1:
 ;
 ; PRE-CONSOLE INITIALIZATION
 ;
-	LD	A,FORCECON		; CALCULATE PRE-INIT TABLE
-	RLCA				; ENTRY THAT WE WANT TO
-	LD	DE,(PC_INITTBL)		; EXECUTE FIRST
-	LD	HL,PC_INITTBL
-	PUSH	HL
-	PUSH	DE
-	PUSH	HL
-	CALL	ADDHLA
-	POP	DE			; PLACE IT AT THE TOP OF THE
-	PUSH	HL			; TABLE BY SWAPPING IT
-	LDI				; WITH THE FIRST (DUMMY)
-	LDI				; ENTRY
-	POP	HL
-	POP	DE
-	LD	(HL),D
+
+	LD	A,FORCECON		; CALCULATE PRE-INIT TABLE		; A IS INDEX OF CONSOLE DEVICE ENTRY
+	RLCA				; ENTRY THAT WE WANT TO			; A IS OFFSET OF CONSOLE DEVICE ENTRY
+	LD	DE,(PC_INITTBL)		; EXECUTE FIRST				; DE IS VALUE OF TOP ENTRY
+	LD	HL,PC_INITTBL							; HL IS ADDRESS OF TOP OF TABLE
+	PUSH	HL								; PUSH (1) TOP OF TABLE
+	PUSH	DE								; PUSH (2) VALUE OF TOP ENTRY 
+	PUSH	HL								; PUSH (3) TOP OF TABLE
+	CALL	ADDHLA								; HL IS ADDRESS OF DESIRED CONSOLE ENTRY
+	POP	DE			; PLACE IT AT THE TOP OF THE		; POP (3) DE IS TOP OF TABLE
+	PUSH	HL			; TABLE BY SWAPPING IT			; PUSH (3) ADDRESS OF DESIRED CONSOLE ENTRY
+	LDI				; WITH THE FIRST (DUMMY)		; COPY DESIRED ENTRY
+	LDI				; ENTRY					; ... TO TOP OF TABLE
+	POP	HL								; POP (3) HL IS ADDRESS OF DESIRED CONSOLE ENTRY
+	POP	DE								; POP (2) DE IS VALUE OF ORIGINAL TOP ENTRY
+	LD	(HL),E								; SAVE DE OVER ORIGINAL ENTRY
 	INC	HL
-	LD	(HL),E
+	LD	(HL),D
 	LD	B,PC_INITTBLLEN
-	POP	DE
+	POP	DE								; POP (1) DE IS ADDRESS OF TOP OF TABLE
 	CALL	CALLLIST		; PROCESS THE PRE-INIT CALL TABLE
 ;
 #IF 0
@ -1180,7 +1141,7 @@ PSCNX	.EQU	$ + 1
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
 	LD	I,A			; ... AND PLACE IT IN I REGISTER

-  #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+  #IFDEF CPU_Z180
 	; SETUP Z180 IVT
 	XOR	A			; SETUP LO BYTE OF IVT ADDRESS
 	OUT0	(Z180_IL),A		; ... AND PLACE IN Z180 IL REGISTER
@ -1218,7 +1179,7 @@ PSCNX	.EQU	$ + 1
 ;
 	; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT
 	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
-	LD	(HB_IVT01 + 1),HL	; IVT INDEX 1
+	LD	(IVT(INT_CTC0B)),HL	; IVT ENTRY FOR CTC0B
 ;
 	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
 	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
@ -1273,7 +1234,7 @@ PSCNX	.EQU	$ + 1
 ;
 	; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT
 	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
-	LD	(HB_IVT03 + 1),HL	; IVT INDEX 3
+	LD	(IVT(INT_CTC0D)),HL	; IVT ENTRY FOR CTC0D
 ;
 	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
 	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
@ -1313,22 +1274,25 @@ PSCNX	.EQU	$ + 1
 	OUT	(CTCD),A		; SETUP CTCD
 	LD	A,72			; CTCD TIMER CONSTANT = 72
 	OUT	(CTCD),A		; SETUP CTCD TIMER CONSTANT
+  #ELSE
+	.ECHO	"*** ERROR: EZZ80 REQUIRES INTMODE 2!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
  #ENDIF
+  
 ;
 #ENDIF
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 ;
  #IF (INTMODE == 2)
 ;
 	; MASK ALL EXTERNAL INTERRUPTS FOR NOW
-	;XOR	A			; INT0-2 DISABLED
 	LD	A,$01			; INT0 ENABLED, INT1-2 DISABLED
 	OUT0	(Z180_ITC),A		; WRITE TO INT/TRAP CONTROL REGISTER
 ;
 	; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
 	LD	HL,HB_TIMINT
-	LD	(HB_IVT02 + 1),HL	; IVT INDEX 3
+	LD	(IVT(INT_TIM0)),HL	; Z180 TIMER 0

 	; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0
 	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
@ -1390,7 +1354,7 @@ HB_PCPU:
 	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
 	PRTS("MHz$")
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	PRTS(" IO=0x$")
 	LD	A,Z180_BASE
 	CALL	PRTHEXBYTE
@ -1399,7 +1363,7 @@ HB_PCPU:
 ; DISPLAY CPU CONFIG
 ;
 	CALL	NEWLINE
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	LD	A,Z180_MEMWAIT
 #ELSE
 	LD	A,0
@ -1407,7 +1371,7 @@ HB_PCPU:
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" MEM W/S, $"
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	LD	A,Z180_IOWAIT + 1
 #ELSE
 	LD	A,1
@ -2392,7 +2356,7 @@ TEMPCNT	.DB	250
 ;
 HB_TIMINT2:
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	; ACK/RESET Z180 TIMER INTERRUPT
 	IN0	A,(Z180_TCR)
 	IN0	A,(Z180_TMDR0L)
@ -2846,6 +2810,7 @@ SIZ_UF	.EQU	$ - ORG_UF
 #INCLUDE "time.asm"
 #INCLUDE "bcd.asm"
 #INCLUDE "decode.asm"
+#INCLUDE "encode.asm"
 ;
 #IF (WBWDEBUG == USEXIO)
 #INCLUDE "xio.asm"
@ -2876,7 +2841,7 @@ HB_CPUSPD:
 	RET	NZ
 ;
 HB_CPUSPD1:
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	; USE MEM W/S = 2 AND I/O W/S = 3 FOR TEST
 	IN0	A,(Z180_DCNTL)
 	PUSH	AF
@ -2893,7 +2858,7 @@ HB_CPUSPD1:
 	LD	(HB_CURSEC),A		; SAVE NEW VALUE
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	; RESTORE W/S SETTINGS FROM BEFORE TEST
 	POP	AF
 	OUT0	(Z180_DCNTL),A
@ -2928,7 +2893,7 @@ HB_WAITSEC:
 	LD	DE,0			; INIT LOOP COUNTER
 HB_WAITSEC1:
 ;
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_EZZ80))
+#IFDEF CPU_Z80
 	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY32
 	CALL	DLY16
@ -2939,7 +2904,7 @@ HB_WAITSEC1:
 	INC	HL			; 6 TSTATES
 #ENDIF
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+#IFDEF CPU_Z180
 	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY2
 	ADD	IX,BC			; 10 + 4 = 14 TSTATES
@ -3776,8 +3741,7 @@ STR_PLATFORM	.DB	PLATFORM_NAME, "$"
 STR_SWITCH	.DB	"*** Activating CRT Console ***$"
 STR_BADINT	.DB	"\r\n*** BAD INT ***\r\n$"
 ;
-#IF (DSKYENABLE)	;	'H','B','I','O',' ','2','9','1'
-;MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$80,$6D,$77,$B0	; "HBIO 291"
+#IF (DSKYENABLE)	;	'H','B','I','O',' ',' ',' ',' '
 MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$80,$80,$80,$80	; "HBIO    "
 #ENDIF
 ;
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@ -16,7 +16,7 @@
 ; 
 ; SIO PORT A (COM1:) and SIO PORT B (COM2:) ARE MAPPED TO DEVICE UC1: AND UL1: IN CP/M.
 ;
-SIO_BUFSZ	.EQU	32			; RECEIVE RING BUFFER SIZE
+SIO_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
 SIO_NONE	.EQU	0
 SIO_SIO		.EQU	1
@ -24,20 +24,19 @@ SIO_SIO		.EQU	1
 SIO_RTSON	.EQU	$EA
 SIO_RTSOFF	.EQU	$E8
 ;
-#IF (INTMODE == 2)
-;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
-SIO0_IVT	.EQU	HB_IVT0D
-SIO1_IVT	.EQU	HB_IVT0E
-SIO0_VEC	.EQU	IVT_SER2
-SIO1_VEC	.EQU	IVT_SER3
+#IF (INTMODE == 0)
+SIO_WR1VAL	.EQU	$00		; WR1 VALUE FOR NO INTS
 #ELSE
-SIO0_IVT	.EQU	HB_IVT07
-SIO1_IVT	.EQU	HB_IVT08
-SIO0_VEC	.EQU	IVT_SER0
-SIO1_VEC	.EQU	IVT_SER1
+SIO_WR1VAL	.EQU	$18		; WR1 VALUE FOR INT ON RECEIVED CHARS
 #ENDIF
 ;
+#IF (INTMODE == 2)
+;
+SIO0_IVT	.EQU	IVT(INT_SIO0)
+SIO1_IVT	.EQU	IVT(INT_SIO1)
+SIO0_VEC	.EQU	VEC(INT_SIO0)
+SIO1_VEC	.EQU	VEC(INT_SIO1)
+;
 #ENDIF
 ;
 #IF (SIO0MODE == SIOMODE_RC)
@ -100,10 +99,6 @@ SIO1B_DAT	.EQU	SIO1BASE + $02
 ;
 #ENDIF
 ;
-; CONDITIONALS THAT DETERMINE THE ENCODED VALUE OF THE BAUD RATE
-;
-#INCLUDE "siobaud.inc"	
-;
 SIO_PREINIT:
 ;
 ; SETUP THE DISPATCH TABLE ENTRIES
@ -155,11 +150,11 @@ SIO_PREINIT2:
 #IF (INTMODE == 2)
 	; SETUP IM2 VECTORS
 	LD	HL,SIO_INT0
-	LD	(SIO0_IVT + 1),HL	; IVT INDEX
+	LD	(SIO0_IVT),HL		; IVT INDEX
 ;
 #IF (SIOCNT >= 2)
 	LD	HL,SIO_INT1
-	LD	(SIO1_IVT + 1),HL	; IVT INDEX
+	LD	(SIO1_IVT),HL		; IVT INDEX
 #ENDIF
 ;
 #ENDIF
@ -184,6 +179,13 @@ SIO_INITUNIT:
 	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
 	LD	(IY),A			; UPDATE UNIT NUM
 	
+	; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED
+	; DUE TO THE CONSTRAINTS OF THE SIO.  HERE WE FORCE A GENERIC
+	; FAILSAFE CONFIG ONTO THE CHANNEL.  IF THE SUBSEQUENT "REAL"
+	; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT
+	; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG.
+	CALL	SIO_INITSAFE
+;	
 	; SET DEFAULT CONFIG
 	LD	DE,-1			; LEAVE CONFIG ALONE
 	; CALL INITDEVX TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
@ -294,7 +296,7 @@ SIO_INTRCV2:
 	INC	HL			; BUMP HEAD POINTER
 	POP	DE			; RECOVER ADR OF HEAD PTR
 	LD	A,L			; GET LOW BYTE OF HEAD PTR
-	ADD	A,-SIO_BUFSZ-4		; SUBTRACT SIZE OF BUFFER AND POINTER
+	SUB	SIO_BUFSZ+4		; SUBTRACT SIZE OF BUFFER AND POINTER
 	CP	E			; IF EQUAL TO START, HEAD PTR IS PAST BUF END
 	JR	NZ,SIO_INTRCV3		; IF NOT, BYPASS
 	LD	H,D			; SET HL TO
@ -378,7 +380,7 @@ SIO_IN1:
 	INC	HL			; BUMP TAIL PTR
 	POP	DE			; RECOVER ADR OF TAIL PTR
 	LD	A,L			; GET LOW BYTE OF TAIL PTR
-	ADD	A,-SIO_BUFSZ-2		; SUBTRACT SIZE OF BUFFER AND POINTER
+	SUB	SIO_BUFSZ+2		; SUBTRACT SIZE OF BUFFER AND POINTER
 	CP	E			; IF EQUAL TO START, TAIL PTR IS PAST BUF END
 	JR	NZ,SIO_IN2		; IF NOT, BYPASS
 	LD	H,D			; SET HL TO
@ -468,159 +470,207 @@ SIO_INITDEVX:
 ;
 ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
 ; PREINIT ABOVE.  PREINIT IS NOT ALLOWED TO ENABLE INTS!
+;
+#IF (SIODEBUG)
+	CALL	NEWLINE
+	PRTS("SIO$")
+	LD	A,(IY+2)
+	SRL	A
+	CALL	PRTDECB
+	LD	A,(IY+2)
+	AND	$01
+	ADD	A,'A'
+	CALL	COUT
+	CALL	PC_COLON
+#ENDIF
 ;
 	; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
 	LD	A,D			; TEST DE FOR
 	AND	E			; ... VALUE OF -1
 	INC	A			; ... SO Z SET IF -1
-	JR	NZ,SIO_INITDEV1	; IF DE == -1, REINIT CURRENT CONFIG
+	JR	NZ,SIO_INITDEV1		; IF DE == -1, REINIT CURRENT CONFIG
 ;
 	; LOAD EXISTING CONFIG TO REINIT
 	LD	E,(IY+5)		; LOW BYTE
 	LD	D,(IY+6)		; HIGH BYTE	
 ;
 SIO_INITDEV1:
-	PUSH	DE			; SAVE CONFIG
-
+;
+#IF (SIODEBUG)
+	PUSH	DE
+	POP	BC
+	PRTS(" CFG=$")
+	CALL	PRTHEXWORD
+#ENDIF
+;
+	LD	A,E			; GET CONFIG LSB
+	AND	$E0			; CHECK FOR DTR, XON, PARITY=MARK/SPACE
+	JR	NZ,SIO_INITFAIL		; IF ANY BIT SET, FAIL, NOT SUPPORTED
+;
 	LD	A,D			; GET CONFIG MSB
 	AND	$1F			; ISOLATE ENCODED BAUD RATE
-
+;
 #IF (SIODEBUG)
-	PUSH	AF
-	PRTS(" ENCODE[$")
+	PRTS(" ENC=$")
 	CALL	PRTHEXBYTE
-	PRTC(']')
-	POP	AF
-#ENDIF
-;
-; ONLY FOUR BAUD RATES ARE POSSIBLE WITH A FIXED CLOCK.
-; THESE ARE PREDETERMINED BY HARDWARE SETTINGS AND MATCHING
-; CONFIGURATION SETTINGS. WE PRECALCULATED THE FOUR 
-; POSSIBLE ENCODED VALUES.
-;
-	CP	SIOBAUD1		; We set the divider and the lower bit (d2) of the stop bits
-	LD	D,$04			; /1 N,8,1
-	JR	Z,BROK	
-	CP	SIOBAUD2	
-	LD	D,$44			; /16 N,8,1
-	JR	Z,BROK	
-	CP	SIOBAUD3	
-	LD	D,$84			; /32 N,8,1
-	JR	Z,BROK	
-	CP	SIOBAUD4	
-	LD	D,$C4			; /64 N,8,1
-	JR	Z,BROK			
-	
+#ENDIF
+;
+	PUSH	DE			; SAVE REQUESTED CONFIG
+	LD	L,(IY+9)		; LOAD CLK FREQ
+	LD	H,(IY+10)		; ... INTO DE:HL
+	LD	E,(IY+11)		; ... "
+	LD	D,(IY+12)		; ... "
+	LD	C,75			; BAUD RATE ENCODING CONSTANT
+	CALL	ENCODE			; C = TEST BAUD RATE (ENCODED) = BAUDTST
+	POP	DE			; GET REQ CONFIG BACK, D = BAUDREQ
+;
+	; BIT 4 (DIV 3) OF BAUDREQ AND BAUDTST MUST MATCH!
+	LD	A,C			; A = BAUDTST
+	XOR	D			; XOR WITH BAUDREQ
+	BIT	4,A			; DO BIT 4 VALS MATCH?
+	JR	NZ,SIO_INITFAIL		; IF NOT, BAIL OUT
+;	
+	LD	A,C			; BAUDTST TO A
+	AND	$0F			; ISOLATE DIV 2 BAUD BITS
+	LD	C,A			; C = BAUDTST
+;	
+	LD	A,D			; MSB W/ BAUD RATE TO A
+	AND	$0F			; ISOLATE DIV 2 BAUD BITS
+	LD	L,A			; L = BAUDREQ
+;	
+;	PUSH	AF			; *DEBUG*
+;	CALL	NEWLINE                 ; *DEBUG*
+;	LD	A,L                     ; *DEBUG*
+;	CALL	PRTHEXBYTE              ; *DEBUG*
+;	LD	A,C                     ; *DEBUG*
+;	CALL	PRTHEXBYTE              ; *DEBUG*
+;	CALL	NEWLINE                 ; *DEBUG*
+;	POP	AF                      ; *DEBUG*
+;	
+	LD	A,C			; A = BAUDTST
+	LD	B,$04			; SIO R4 VAL FOR DIV 1
+	CP	L			; BAUDTST = BAUDREQ?
+	JR	Z,SIO_INITBROK		; IF MATCH, WE ARE DONE
+;	
+	SUB	4			; DIVIDE BY 16 (NOW DIV 16 TOT)
+	JR	C,SIO_INITFAIL		; FAIL IF UNDERFLOW
+	LD	B,$44			; SIO R4 VAL FOR DIV 16
+	CP	L			; BAUDTST = BAUDREQ?
+	JR	Z,SIO_INITBROK		; IF MATCH, WE ARE DONE
+;	
+	SUB	1			; DIVIDE BY 2 (NOW DIV 32 TOT)
+	JR	C,SIO_INITFAIL		; FAIL IF UNDERFLOW
+	LD	B,$84			; SIO R4 VAL FOR DIV 32
+	CP	L			; BAUDTST = BAUDREQ?
+	JR	Z,SIO_INITBROK		; IF MATCH, WE ARE DONE
+;	
+	SUB	1			; DIVIDE BY 2 (NOW DIV 64 TOT)
+	JR	C,SIO_INITFAIL		; FAIL IF UNDERFLOW
+	LD	B,$C4			; SIO R4 VAL FOR DIV 64
+	CP	L			; BAUDTST = BAUDREQ?
+	JR	Z,SIO_INITBROK		; IF MATCH, WE ARE DONE
+;
+SIO_INITFAIL:
+;
 #IF (SIODEBUG)
-	PUSH	AF
-	PRTS(" BR FAIL[$")	
-	CALL PRTHEXBYTE
-	PRTC(']')
-	POP	AF
+	PRTS(" BAD CFG$")	
 #ENDIF
 ;
-EXITINIT:
-	POP	DE
+	OR	$FF
 	RET				; NZ status here indicating fail / invalid baud rate.
-	
-BROK:
-	LD	A,E
-	AND	$E0
-	JR	NZ,EXITINIT		; NZ status here indicates dtr, xon, parity mark or space so return
-
-	LD	A,E			;  set stop bit (d3) and add divider
+;	
+SIO_INITBROK:
+	LD	A,E			; set stop bit (d3) and add divider
 	AND	$04
 	RLA
-	OR	D			; carry gets reset here
-	LD	D,A
+	OR	B			; carry gets reset here
+	LD	L,A			; save in L
 	
 	LD	A,E			; get the parity bits
 	SRL	A			; move them to bottom two bits
 	SRL	A			; we know top bits are zero from previous test
 	SRL	A			; add stop bits
-	OR	D 			; carry = 0
+	OR	L 			; carry = 0
 ;	
 ; SET DIVIDER, STOP AND PARITY WR4
 ;	
-	LD	BC,SIO_INITVALS+3
-	LD	(BC),A
-	
-#IF (SIODEBUG)
-	PUSH	AF
-	PRTS(" WR4[$")
-	CALL	PRTHEXBYTE
-	PRTC(']')
-	POP	AF
-#ENDIF
-
+	LD	(SIO_WR4),A
+;
 	LD	A,E			; 112233445566d1d0 CC
 	RRA				; CC112233445566d1 d0
 	RRA				; d0CC112233445566 d1
 	RRA 				; d1d0CC1122334455 66
-	LD	D,A	
+	LD	L,A	
 	RRA				; 66d1d0CC11223344 55
 	AND	$60			; 0011110000000000 00
-	OR	$8a
+	OR	$8A
 ;	
 ; SET TRANSMIT DATA BITS WR5	
 ;
-	LD	BC,SIO_INITVALS+11
-	LD	(BC),A	
-
-#IF (SIODEBUG)
-	PUSH	AF
-	PRTS(" WR5[$")
-	CALL	PRTHEXBYTE
-	PRTC(']')
-	POP	AF
-#ENDIF	
+	LD	(SIO_WR5),A
 ;
 ; SET RECEIVE DATA BITS WR3 
 ;	
-	LD	A,D			; DATA BITS
+	LD	A,L			; DATA BITS
 	AND	$C0			; CLEAR OTHER BITS
 	OR	$21			; CTS/DCD AUTO, RX ENABLE
-	
-	LD	BC,SIO_INITVALS+9
-	LD	(BC),A	
-
-#IF (SIODEBUG)
-	PUSH	AF
-	PRTS(" WR3[$")
-	CALL	PRTHEXBYTE
-	PRTC(']')
-	POP	AF
-#ENDIF
+;	
+	LD	(SIO_WR3),A
+;
+; SAVE CONFIG PERMANENTLY NOW
+;
+	LD	(IY+5),E		; SAVE LOW WORD
+	LD	(IY+6),D		; SAVE HI WORD
+;
+	JR	SIO_INITGO		; GO TO SEND INIT
+;
+; ENTER HERE TO PERFORM A "SAFE" INITIALIZTION.  I.E., INIT THE
+; CHANNEL USING THE DEFAULT, GENERIC REGISTER VALUES.  THIS CAN BE
+; USED TO ENSURE INITIALIZATION IF THE FULL CONFIGURATION ABOVE
+; FAILS.
+;
+SIO_INITSAFE:
+	LD	HL,SIO_INITDEFS
+	LD	DE,SIO_INITVALS
+	LD	BC,SIO_INITLEN
+	LDIR
+;
+SIO_INITGO:
 ;
 ; SET INTERRUPT VECTOR OFFSET WR2
 ;
 #IF (INTMODE == 2)
 	LD	A,(IY+2)		; CHIP / CHANNEL
 	SRL	A			; SHIFT AWAY CHANNEL BIT
-	LD	E,SIO0_VEC		; ASSUME CHIP 0
-	JR	Z,SIO_IVT1		; IF SO, DO IT
-	LD	E,SIO1_VEC		; ASSUME CHIP 1
+	LD	L,SIO0_VEC		; ASSUME CHIP 0
+	JR	Z,SIO_INITIVT		; IF SO, DO IT
+	LD	L,SIO1_VEC		; ASSUME CHIP 1
 	DEC	A			; CHIP 1?
-	JR	Z,SIO_IVT1		; IF SO, TO IT
+	JR	Z,SIO_INITIVT		; IF SO, DO IT
 	CALL 	PANIC			; IMPOSSIBLE SITUATION
-SIO_IVT1:
-	LD	A,E			; VALUE TO A
-	LD	(SIO_INITVALS+7),A	; SAVE IT
-
+SIO_INITIVT:
+	LD	A,L			; VALUE TO A
+	LD	(SIO_WR2),A		; SAVE IT
+;
+#ENDIF
+;
 #IF (SIODEBUG)
-	PUSH	AF
-	PRTS(" WR2[$")
+	LD	HL,SIO_INITVALS
+	LD	B,SIO_INITLEN/2
+SIO_INITPRT:
+	PRTS(" WR$")
+	LD	A,(HL)
 	CALL	PRTHEXBYTE
-	PRTC(']')
-	POP	AF
-#ENDIF
-
+	INC	HL
+	LD	A,'='
+	CALL	COUT
+	LD	A,(HL)
+	CALL	PRTHEXBYTE
+	INC	HL
+	DJNZ	SIO_INITPRT
+	LD	DE,65
+	CALL	VDELAY			; WAIT FOR FINAL CHAR TO SEND
 #ENDIF
-
-	POP	DE			; RESTORE CONFIG
-
-	LD	(IY+5),E		; SAVE LOW WORD
-	LD	(IY+6),D		; SAVE HI WORD
 ;
 	; PROGRAM THE SIO CHIP CHANNEL
 	LD	C,(IY+3)		; COMMAND PORT
@ -655,20 +705,41 @@ SIO_IVT1:
 	XOR	A			; SIGNAL SUCCESS
 	RET				; RETURN
 ;
+; THE SIO IS A LITTLE PRICKLY ABOUT THE ORDER IN WHICH REGSITERS ARE
+; WRITTEN DURING CONFIGURATION.  THE TABLE BELOW IS USED TO SETUP
+; THE REGISTER VALUES AND THEN THE ENTIRE TABLE CAN BE SPIT OUT.
 ;
 SIO_INITVALS:
-	.DB	$00, $18		; WR0: CHANNEL RESET
-	.DB	$04, $00		; WR4: CLK BAUD PARITY STOP BIT
-#IF (INTMODE == 0)
-	.DB	$01, $00		; WR1: NO INTERRUPTS
-#ELSE
-	.DB	$01, $18		; WR1: INTERRUPT ON ALL RECEIVE CHARACTERS
-#ENDIF
-	.DB	$02, IVT_SER0		; WR2: IM2 INTERRUPT VECTOR OFFSET
+	.DB	$00, $18		; WR0: CHANNEL RESET CMD
+SIO_WR4	.EQU	$+1
+	.DB	$04, $C4		; WR4: CLK BAUD PARITY STOP BIT
+SIO_WR1	.EQU	$+1
+	.DB	$01, SIO_WR1VAL		; WR1: INTERRUPT STYLE
+SIO_WR2	.EQU	$+1
+	.DB	$02, $00		; WR2: IM2 VEC OFFSET, SET DYNAMICALLY
+SIO_WR3	.EQU	$+1
 	.DB	$03, $E1		; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE
+SIO_WR5	.EQU	$+1
 	.DB	$05, SIO_RTSON		; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
+;
 SIO_INITLEN	.EQU	$ - SIO_INITVALS
 ;
+; THE FOLLOWING TABLE IS A GENERIC, STATIC SET OF CONFIG VALUES THAT CAN
+; BE USED TO INITIALIZE THE WORKING TABLE ABOVE.
+;
+SIO_INITDEFS:
+	.DB	$00, $18		; WR0: CHANNEL RESET CMD
+	.DB	$04, $C4		; WR4: CLK BAUD PARITY STOP BIT
+	.DB	$01, SIO_WR1VAL		; WR1: INTERRUPT STYLE
+	.DB	$02, $00		; WR2: IM2 VEC OFFSET
+	.DB	$03, $E1		; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE
+	.DB	$05, SIO_RTSON		; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
+;
+#IF (($ - SIO_INITDEFS) != SIO_INITLEN)
+	.ECHO	"*** ERROR: SIO_INITDEFS TABLE IS NOT THE SAME SIZE AS SIO_INITVALS TABLE!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
 ;
 ;
 SIO_QUERY:
@ -752,6 +823,8 @@ SIO_RD:
 	RET
 ;
 ; SIO DETECTION ROUTINE
+; THERE IS ONLY ONE VARIATION OF SIO CHIP, SO HERE WE JUST CHECK THE
+; CHIP PRESENCE BITMAP TO SET THE CHIP TYPE OF EITHER NONE OR SIO.
 ;
 SIO_DETECT:
 	LD	B,(IY+2)		; GET  CHIP/CHANNEL
@ -807,8 +880,8 @@ SIO_PRTCFG:
 ;
 ;
 SIO_TYPE_MAP:
-		.DW	SIO_STR_NONE
-		.DW	SIO_STR_SIO
+	.DW	SIO_STR_NONE
+	.DW	SIO_STR_SIO

 SIO_STR_NONE	.DB	"<NOT PRESENT>$"
 SIO_STR_SIO	.DB	"SIO$"
@ -874,8 +947,10 @@ SIO0A_CFG:
 	.DB	$00			; CHIP 0 / CHANNEL A (LOW BIT IS CHANNEL)
 	.DB	SIO0A_CMD		; CMD/STATUS PORT
 	.DB	SIO0A_DAT		; DATA PORT
-	.DW	DEFSIO0ACFG		; LINE CONFIGURATION
+	.DW	SIO0ACFG		; LINE CONFIGURATION
 	.DW	SIO0A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+	.DW	(SIO0ACLK / SIO0ADIV) & $FFFF	; CLOCK FREQ AS
+	.DW	(SIO0ACLK / SIO0ADIV) >> 16	; ... DWORD VALUE
 ;
 SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
 ;
@ -886,8 +961,10 @@ SIO0B_CFG:
 	.DB	$01			; CHIP 0 / CHANNEL B (LOW BIT IS CHANNEL)
 	.DB	SIO0B_CMD		; CMD/STATUS PORT
 	.DB	SIO0B_DAT		; DATA PORT
-	.DW	DEFSIO0BCFG		; LINE CONFIGURATION
+	.DW	SIO0BCFG		; LINE CONFIGURATION
 	.DW	SIO0B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+	.DW	(SIO0BCLK / SIO0BDIV) & $FFFF	; CLOCK FREQ AS
+	.DW	(SIO0BCLK / SIO0BDIV) >> 16	; ... DWORD VALUE
 ;
 #IF (SIOCNT >= 2)
 ;
@ -898,8 +975,10 @@ SIO1A_CFG:
 	.DB	$02			; CHIP 1 / CHANNEL A (LOW BIT IS CHANNEL)
 	.DB	SIO1A_CMD		; CMD/STATUS PORT
 	.DB	SIO1A_DAT		; DATA PORT
-	.DW	DEFSIO1ACFG		; LINE CONFIGURATION
+	.DW	SIO1ACFG		; LINE CONFIGURATION
 	.DW	SIO1A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+	.DW	(SIO1ACLK / SIO1ADIV) & $FFFF	; CLOCK FREQ AS
+	.DW	(SIO1ACLK / SIO1ADIV) >> 16	; ... DWORD VALUE
 ;
 	; SIO1 CHANNEL B
 SIO1B_CFG:
@ -908,8 +987,10 @@ SIO1B_CFG:
 	.DB	$03			; CHIP 1 / CHANNEL B (LOW BIT IS CHANNEL)
 	.DB	SIO1B_CMD		; CMD/STATUS PORT
 	.DB	SIO1B_DAT		; DATA PORT
-	.DW	DEFSIO1BCFG		; LINE CONFIGURATION
+	.DW	SIO1BCFG		; LINE CONFIGURATION
 	.DW	SIO1B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+	.DW	(SIO1BCLK / SIO1BDIV) & $FFFF	; CLOCK FREQ AS
+	.DW	(SIO1BCLK / SIO1BDIV) >> 16	; ... DWORD VALUE
 ;
 #ENDIF
 ;
--- a/Source/HBIOS/siobaud.inc
+++ b/Source/HBIOS/siobaud.inc
@ -1,393 +0,0 @@
-;
-; SIOBAUD1, SIOBAUD2, SIOBAUD3, SIOBAUD4 ARE SET TO THE
-; ENCODED VALUE OF EACH POSSIBLE BAUD RATE WITH A FIXED CLOCK.
-;
-
-#IF (DEFSIOCLK/DEFSIODIV/1 ==     75) 
-SIOBAUD1 .EQU  0
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==    150) 
-SIOBAUD1 .EQU  1 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==    300) 
-SIOBAUD1  .EQU  2 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==    600) 
-SIOBAUD1  .EQU  3 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   1200) 
-SIOBAUD1  .EQU  4 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   2400) 
-SIOBAUD1  .EQU  5 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   4800) 
-SIOBAUD1  .EQU  6 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   9600) 
-SIOBAUD1  .EQU  7 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==  19200) 
-SIOBAUD1  .EQU  8 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==  38400) 
-SIOBAUD1  .EQU  9 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==  76800) 
-SIOBAUD1  .EQU 10 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 153600) 
-SIOBAUD1  .EQU 11 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 307200) 
-SIOBAUD1  .EQU 12 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 614400) 
-SIOBAUD1  .EQU 13 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==1228800) 
-SIOBAUD1  .EQU 14 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==2457600) 
-SIOBAUD1  .EQU 15 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==    225) 
-SIOBAUD1  .EQU 16 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==    450) 
-SIOBAUD1  .EQU 17 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==    900) 
-SIOBAUD1  .EQU 18 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   1800) 
-SIOBAUD1  .EQU 19 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   3600) 
-SIOBAUD1  .EQU 20 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==   7200) 
-SIOBAUD1  .EQU 21 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==  14400) 
-SIOBAUD1  .EQU 22 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==  28800) 
-SIOBAUD1  .EQU 23 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==  57600) 
-SIOBAUD1  .EQU 24 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 115200) 
-SIOBAUD1  .EQU 25 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 230400) 
-SIOBAUD1  .EQU 26 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 460800)
-SIOBAUD1  .EQU 27
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 == 921600) 
-SIOBAUD1  .EQU 28 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==1843200) 
-SIOBAUD1  .EQU 29 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==3686400) 
-SIOBAUD1  .EQU 30 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/1 ==7372800) 
-SIOBAUD1  .EQU 31 
-#ENDIF
-
-
-#IF (DEFSIOCLK/DEFSIODIV/16 ==     75) 
-SIOBAUD2  .EQU  0 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==    150) 
-SIOBAUD2  .EQU  1 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==    300) 
-SIOBAUD2  .EQU  2 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==    600) 
-SIOBAUD2  .EQU  3 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   1200) 
-SIOBAUD2  .EQU  4 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   2400) 
-SIOBAUD2  .EQU  5 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   4800) 
-SIOBAUD2  .EQU  6 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   9600) 
-SIOBAUD2  .EQU  7 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==  19200) 
-SIOBAUD2  .EQU  8 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==  38400) 
-SIOBAUD2  .EQU  9 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==  76800) 
-SIOBAUD2  .EQU 10 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 153600) 
-SIOBAUD2  .EQU 11 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 307200) 
-SIOBAUD2  .EQU 12 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 614400) 
-SIOBAUD2  .EQU 13 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==1228800) 
-SIOBAUD2  .EQU 14 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==2457600) 
-SIOBAUD2  .EQU 15 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==    225) 
-SIOBAUD2  .EQU 16 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==    450) 
-SIOBAUD2  .EQU 17 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==    900) 
-SIOBAUD2  .EQU 18 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   1800) 
-SIOBAUD2  .EQU 19 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   3600) 
-SIOBAUD2  .EQU 20 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==   7200) 
-SIOBAUD2  .EQU 21 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==  14400) 
-SIOBAUD2  .EQU 22 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==  28800) 
-SIOBAUD2  .EQU 23 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==  57600) 
-SIOBAUD2  .EQU 24 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 115200) 
-SIOBAUD2  .EQU 25 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 230400) 
-SIOBAUD2  .EQU 26 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 460800) 
-SIOBAUD2  .EQU 27 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 == 921600) 
-SIOBAUD2  .EQU 28 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==1843200) 
-SIOBAUD2  .EQU 29 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==3686400) 
-SIOBAUD2  .EQU 30 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/16 ==7372800) 
-SIOBAUD2  .EQU 31 
-#ENDIF
-
-#IF (DEFSIOCLK/DEFSIODIV/32==     75) 
-SIOBAUD3  .EQU  0 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==    150) 
-SIOBAUD3  .EQU  1 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==    300) 
-SIOBAUD3  .EQU  2 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==    600) 
-SIOBAUD3  .EQU  3 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   1200) 
-SIOBAUD3  .EQU  4 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   2400) 
-SIOBAUD3  .EQU  5 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   4800) 
-SIOBAUD3  .EQU  6 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   9600) 
-SIOBAUD3  .EQU  7 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==  19200) 
-SIOBAUD3  .EQU  8 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==  38400) 
-SIOBAUD3  .EQU  9 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==  76800) 
-SIOBAUD3  .EQU 10 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 153600) 
-SIOBAUD3  .EQU 11 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 307200) 
-SIOBAUD3  .EQU 12 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 614400) 
-SIOBAUD3  .EQU 13 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==1228800) 
-SIOBAUD3  .EQU 14 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==2457600) 
-SIOBAUD3  .EQU 15 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==    225) 
-SIOBAUD3  .EQU 16 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==    450) 
-SIOBAUD3  .EQU 17 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==    900) 
-SIOBAUD3  .EQU 18 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   1800) 
-SIOBAUD3  .EQU 19 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   3600) 
-SIOBAUD3  .EQU 20 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==   7200) 
-SIOBAUD3  .EQU 21 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==  14400) 
-SIOBAUD3  .EQU 22 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==  28800) 
-SIOBAUD3  .EQU 23 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==  57600) 
-SIOBAUD3  .EQU 24 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 115200) 
-SIOBAUD3  .EQU 25 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 230400) 
-SIOBAUD3  .EQU 26 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 460800) 
-SIOBAUD3  .EQU 27 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32== 921600) 
-SIOBAUD3  .EQU 28 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==1843200) 
-SIOBAUD3  .EQU 29 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==3686400) 
-SIOBAUD3  .EQU 30 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/32==7372800) 
-SIOBAUD3  .EQU 31 
-#ENDIF
-
-#IF (DEFSIOCLK/DEFSIODIV/64==     75) 
-SIOBAUD4  .EQU  0 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==    150) 
-SIOBAUD4  .EQU  1 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==    300) 
-SIOBAUD4  .EQU  2 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==    600) 
-SIOBAUD4  .EQU  3 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==   1200) 
-SIOBAUD4  .EQU  4 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==   2400) 
-SIOBAUD4  .EQU  5 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==   4800) 
-SIOBAUD4  .EQU  6 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  9600) 
-SIOBAUD4  .EQU  7 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  19200) 
-SIOBAUD4  .EQU  8 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  38400) 
-SIOBAUD4  .EQU  9 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  76800) 
-SIOBAUD4  .EQU 10 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 153600) 
-SIOBAUD4  .EQU 11 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 307200) 
-SIOBAUD4  .EQU 12 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 614400) 
-SIOBAUD4  .EQU 13 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==1228800) 
-SIOBAUD4  .EQU 14 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==2457600) 
-SIOBAUD4  .EQU 15 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==    225) 
-SIOBAUD4  .EQU 16 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==    450) 
-SIOBAUD4  .EQU 17 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==    900) 
-SIOBAUD4  .EQU 18 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==   1800) 
-SIOBAUD4  .EQU 19 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==   3600) 
-SIOBAUD4  .EQU 20 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==   7200) 
-SIOBAUD4  .EQU 21 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  14400) 
-SIOBAUD4  .EQU 22 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  28800) 
-SIOBAUD4  .EQU 23 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==  57600) 
-SIOBAUD4  .EQU 24 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 115200) 
-SIOBAUD4  .EQU 25 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 230400) 
-SIOBAUD4  .EQU 26 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 460800) 
-SIOBAUD4  .EQU 27 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64== 921600) 
-SIOBAUD4  .EQU 28 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==1843200) 
-SIOBAUD4  .EQU 29 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==3686400) 
-SIOBAUD4  .EQU 30 
-#ENDIF
-#IF (DEFSIOCLK/DEFSIODIV/64==7372800) 
-SIOBAUD4  .EQU 31 
-#ENDIF
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@ -91,6 +91,11 @@ DSRTCMODE_NONE	.EQU	0		; NO DSRTC
 DSRTCMODE_STD	.EQU	1		; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
 DSRTCMODE_MFPIC	.EQU	2		; MF/PIC VARIANT
 ;
+; ACIA MODE SELECTIONS
+;
+ACIAMODE_NONE	.EQU	0
+ACIAMODE_RC	.EQU	1		; RC2014 ACIA MODULE (SPENCER OWEN)
+;
 ; SIO MODE SELECTIONS
 ;
 SIOMODE_NONE	.EQU	0
@ -192,7 +197,6 @@ SER_BAUD7200	.EQU	$15 << 8
 SER_BAUD14400	.EQU	$16 << 8							
 SER_BAUD28800	.EQU	$17 << 8							
 SER_BAUD57600	.EQU	$18 << 8						
-
 SER_BAUD115200	.EQU	$19 << 8
 SER_BAUD230400	.EQU	$1A << 8
 SER_BAUD460800	.EQU	$1B << 8
@ -251,25 +255,6 @@ V80X24B		.EQU	4
 KBD_US		.EQU	0	; US ENGLISH
 KBD_DE		.EQU	1	; GERMAN
 ;
-; INTERRUPT VECTOR TABLE ENTRY OFFSETS (Z180 COMPATIBLE)
-;
-IVT_INT1	.EQU	0
-IVT_INT2	.EQU	2
-IVT_TIM0	.EQU	4
-IVT_TIM1	.EQU	6
-IVT_DMA0	.EQU	8
-IVT_DMA1	.EQU	10
-IVT_CSIO	.EQU	12
-IVT_SER0	.EQU	14
-IVT_SER1	.EQU	16
-IVT_PIO0	.EQU	18
-IVT_PIO1	.EQU	20
-IVT_PIO2	.EQU	22
-IVT_PIO3	.EQU	24
-IVT_SER2	.EQU	26
-IVT_SER3	.EQU	28
-;
-;
 ; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
 ; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
 ; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE, 
@ -448,6 +433,52 @@ FTH_END		.EQU	FTH_LOC + FTH_SIZ
 MON_DSKY	.EQU	MON_LOC + (0 * 3)	; MONITOR ENTRY (DSKY)
 MON_SERIAL	.EQU	MON_LOC + (1 * 3)	; MONITOR ENTRY (SERIAL PORT)
 ;
+; INTERRUPT MODE 2 SLOT ASSIGNMENTS
+;
+#IF (INTMODE == 2)
+
+  #IFDEF CPU_Z180
+
+; Z180-BASED SYSTEMS
+
+INT_INT1	.EQU	0	; Z180 INT 1
+INT_INT2	.EQU	1	; Z180 INT 2
+INT_TIM0	.EQU	2	; Z180 TIMER 0
+INT_TIM1	.EQU	3	; Z180 TIMER 1
+INT_DMA0	.EQU	4	; Z180 DMA 0
+INT_DMA1	.EQU	5	; Z180 DMA 1
+INT_CSIO	.EQU	6	; Z180 CSIO
+INT_SER0	.EQU	7	; Z180 SERIAL 0
+INT_SER1	.EQU	8	; Z180 SERIAL 0
+INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
+INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
+INT_PIO1B	.EQU	12      ; ZILOG PIO 1, CHANNEL B
+INT_SIO0	.EQU	13	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	14	; ZILOG SIO 1, CHANNEL A & B
+
+  #ELSE
+  
+; Z80-BASED SYSTEMS
+
+INT_CTC0A	.EQU	0	; ZILOG CTC #0, CHANNEL A
+INT_CTC0B	.EQU	1	; ZILOG CTC #0, CHANNEL B
+INT_CTC0C	.EQU	2	; ZILOG CTC #0, CHANNEL C
+INT_CTC0D	.EQU	3	; ZILOG CTC #0, CHANNEL D
+INT_SIO0	.EQU	7	; ZILOG SIO 0, CHANNEL A & B
+INT_SIO1	.EQU	8       ; ZILOG SIO 1, CHANNEL A & B
+INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
+INT_PIO0B	.EQU	10      ; ZILOG PIO 0, CHANNEL B
+INT_PIO1A	.EQU	11      ; ZILOG PIO 1, CHANNEL A
+INT_PIO1B	.EQU	12      ; ZILOG PIO 1, CHANNEL B
+
+  #ENDIF
+  
+#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
+#DEFINE VEC(INTX) INTX*2
+
+#ENDIF
+;
 ; HELPER MACROS
 ;
 #DEFINE	PRTC(C)	CALL PRTCH \ .DB C			; PRINT CHARACTER C TO CONSOLE - PRTC('X')
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@ -569,7 +569,8 @@ UART_DEV		.DB	0		; DEVICE NUM USED DURING INIT
 ; UART PORT TABLE
 ;
 UART_CFG:
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
+;#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
+#IF (UARTSBC)
 	; SBC/ZETA ONBOARD SERIAL PORT
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@ -578,7 +579,8 @@ UART_CFG:
 	.DW	DEFSERCFG			; LINE CONFIGURATION
 	.FILL	2,$FF				; FILLER
 #ENDIF
-#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+;#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+#IF (UARTCAS)
 	; CASSETTE INTERFACE SERIAL PORT
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@ -587,7 +589,8 @@ UART_CFG:
 	.DW	SER_300_8N1			; LINE CONFIGURATION
 	.FILL	2,$FF				; FILLER
 #ENDIF
-#IF (PLATFORM == PLT_SBC)
+;#IF (PLATFORM == PLT_SBC)
+#IF (UARTMFP)
 	; MF/PIC SERIAL PORT
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@ -596,7 +599,8 @@ UART_CFG:
 	.DW	DEFSERCFG			; LINE CONFIGURATION
 	.FILL	2,$FF				; FILLER
 #ENDIF
-#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+;#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+#IF (UART4)
 	; 4UART SERIAL PORT A
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@ -604,8 +608,6 @@ UART_CFG:
 	.DB	$C0 + UART_LSR			; LINE STATUS PORT (LSR)
 	.DW	DEFSERCFG			; LINE CONFIGURATION
 	.FILL	2,$FF				; FILLER
-#ENDIF
-#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
 	; 4UART SERIAL PORT B
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@ -613,8 +615,6 @@ UART_CFG:
 	.DB	$C8 + UART_LSR			; LINE STATUS PORT (LSR)
 	.DW	DEFSERCFG			; LINE CONFIGURATION
 	.FILL	2,$FF				; FILLER
-#ENDIF
-#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
 	; 4UART SERIAL PORT C
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
@ -622,8 +622,6 @@ UART_CFG:
 	.DB	$D0 + UART_LSR			; LINE STATUS PORT (LSR)
 	.DW	DEFSERCFG			; LINE CONFIGURATION
 	.FILL	2,$FF				; FILLER
-#ENDIF
-#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
 	; 4UART SERIAL PORT D
 	.DB	0				; DEVICE NUMBER (UPDATED DURING INIT)
 	.DB	0				; UART TYPE
--- a/Source/HBIOS/ver.inc
+++ b/Source/HBIOS/ver.inc
@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.1"
+#DEFINE BIOSVER	"2.9.2-pre.2"