From 15d607d686d183c85b87c8be10a183784cd6b8c2 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 7 Feb 2020 11:47:16 -0800 Subject: [PATCH] Further PPIDE updates --- Doc/ChangeLog.txt | 2 + ReadMe.txt | 2 +- Source/BL/ver.inc | 2 +- Source/CBIOS/ver.inc | 2 +- Source/CPM3/ver.inc | 2 +- Source/HBIOS/Config/MK4_std.asm | 1 - Source/HBIOS/Config/SBC_std.asm | 1 - Source/HBIOS/cfg_dyno.asm | 9 +- Source/HBIOS/cfg_ezz80.asm | 6 +- Source/HBIOS/cfg_master.asm | 13 +- Source/HBIOS/cfg_mk4.asm | 13 +- Source/HBIOS/cfg_n8.asm | 13 +- Source/HBIOS/cfg_rcz180.asm | 14 +- Source/HBIOS/cfg_rcz80.asm | 13 +- Source/HBIOS/cfg_sbc.asm | 13 +- Source/HBIOS/cfg_scz180.asm | 13 +- Source/HBIOS/cfg_zeta.asm | 6 +- Source/HBIOS/cfg_zeta2.asm | 6 +- Source/HBIOS/ppide.asm | 747 ++++++++++++++++---------------- Source/HBIOS/std.asm | 1 - Source/HBIOS/ver.inc | 2 +- 21 files changed, 463 insertions(+), 418 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 873e0e36..26919279 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -40,6 +40,8 @@ Version 2.9.2 - PMS: Added font compression option - PMS: Added a "safe mode" startup w/ minimal device support - WBW: Switch RC/SC Z180 platforms to 115,200 default baud rate +- PMS: Enhanced PPIDE driver to handle multiple PPI interfaces +- PMS: Added a ROM based game Version 2.9.1 ------------- diff --git a/ReadMe.txt b/ReadMe.txt index 49a04500..f9f522d0 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -7,7 +7,7 @@ *********************************************************************** Wayne Warthen (wwarthen@gmail.com) -Version 2.9.2-pre.27, 2020-01-26 +Version 2.9.2-pre.28, 2020-02-07 https://www.retrobrewcomputers.org/ RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for diff --git a/Source/BL/ver.inc b/Source/BL/ver.inc index 530202ad..ed995cd7 100644 --- a/Source/BL/ver.inc +++ b/Source/BL/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.27" +#DEFINE BIOSVER "2.9.2-pre.28" diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc index 530202ad..ed995cd7 100644 --- a/Source/CBIOS/ver.inc +++ b/Source/CBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.27" +#DEFINE BIOSVER "2.9.2-pre.28" diff --git a/Source/CPM3/ver.inc b/Source/CPM3/ver.inc index 868c7005..0b96de4f 100644 --- a/Source/CPM3/ver.inc +++ b/Source/CPM3/ver.inc @@ -3,5 +3,5 @@ rmn equ 9 rup equ 2 rtp equ 0 biosver macro - db "2.9.2-pre.27" + db "2.9.2-pre.28" endm diff --git a/Source/HBIOS/Config/MK4_std.asm b/Source/HBIOS/Config/MK4_std.asm index f0e45a2d..b144c790 100644 --- a/Source/HBIOS/Config/MK4_std.asm +++ b/Source/HBIOS/Config/MK4_std.asm @@ -41,7 +41,6 @@ IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDEMODE .SET IDEMODE_MK4 ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE] ; PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .SET PPIDEMODE_MFP ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC] ; SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC] diff --git a/Source/HBIOS/Config/SBC_std.asm b/Source/HBIOS/Config/SBC_std.asm index 8097a3d6..31e094cf 100644 --- a/Source/HBIOS/Config/SBC_std.asm +++ b/Source/HBIOS/Config/SBC_std.asm @@ -37,7 +37,6 @@ IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDEMODE .SET IDEMODE_DIO ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE] ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .SET PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC] ; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC] diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index 83d7e0c5..e6808004 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -109,11 +109,12 @@ IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE] IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; -PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_DYNO ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] +PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $4C ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 35fedb50..d38b3587 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -125,9 +125,11 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 8a004eb8..a63aa593 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -169,10 +169,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_NONE ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $44 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index dd2e31a5..448d6361 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -124,10 +124,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $44 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index ac917b95..0a1b2aa6 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -127,10 +127,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_N8 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $80 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index e3a1d7bb..9e1ba907 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -130,11 +130,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES -; +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index e8f91bc4..1a79f75a 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -134,10 +134,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index b7027b23..67c1b36a 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -127,10 +127,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $44 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 0b90bc61..79f88b5e 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -125,10 +125,17 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) -PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index 4997be12..d34cfdbb 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -101,9 +101,11 @@ RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index 65c3e8d5..44c6bdcd 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -106,9 +106,11 @@ RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) ; PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm index 92eb3a66..98dfd096 100644 --- a/Source/HBIOS/ppide.asm +++ b/Source/HBIOS/ppide.asm @@ -4,30 +4,16 @@ ;============================================================================= ; ; TODO: -; - IMPLEMENT PPIDE_INITDEVICE ; - IMPLEMENT INTELLIGENT RESET, CHECK IF DEVICE IS ACTUALLY BROKEN BEFORE RESET ; - FIX SCALER CONSTANT ; -; -#IF (PPIDEMODE == PPIDEMODE_SBC) -PPIDE_IO_BASE .EQU $60 -#ENDIF -; -#IF ((PPIDEMODE == PPIDEMODE_DIO3) | (PPIDEMODE == PPIDEMODE_RC)) -PPIDE_IO_BASE .EQU $20 -#ENDIF -; -#IF (PPIDEMODE == PPIDEMODE_MFP) -PPIDE_IO_BASE .EQU $44 -#ENDIF -; -#IF (PPIDEMODE == PPIDEMODE_N8) -PPIDE_IO_BASE .EQU $80 -#ENDIF -; -#IF (PPIDEMODE == PPIDEMODE_DYNO) -PPIDE_IO_BASE .EQU $4C -#ENDIF +; NOTES: +; - WELL KNOWN PPIDE PORT ADDRESSES: +; $60 - SBC/ZETA ONBOARD PPI +; $20 - ECB DISKIO3, RC FAMILY +; $44 - ECB MULTI-FUNCTION PIC +; $80 - N8 ONBOARD PPI +; $4C - DYNO ONBOARD PPI ; ; THE CONTROL PORT OF THE 8255 IS PROGRAMMED AS NEEDED TO READ OR WRITE ; DATA ON THE IDE BUS. PORT C OF THE 8255 IS ALWAYS IN OUTPUT MODE BECAUSE @@ -162,18 +148,7 @@ PPIDE_REG_DRVADR .EQU PPIDE_CTL_CS3FX | $07 ; DRIVE ADDRESS REGISTER (R) #DEFINE DCALL \; #ENDIF ; -; UNIT MAPPING IS AS FOLLOWS: -; PPIDE0: PRIMARY MASTER -; PPIDE1: PRIMARY SLAVE -; PPIDE2: SECONDARY MASTER -; PPIDE3: SECONDARY SLAVE -; -PPIDE0IO .EQU PPIDE_IO_BASE -PPIDE1IO .EQU 20H -PPIDE2IO .EQU 44H -PPIDE3IO .EQU 00H -; -PPIDE_DEVCNT .EQU PPICNT*2 +PPIDE_DEVCNT .EQU PPIDECNT * 2 ; ASSUME ONLY PRIMARY INTERFACE ; ; COMMAND BYTES ; @@ -194,7 +169,7 @@ PPIDE_TYPEUNK .EQU 0 PPIDE_TYPEATA .EQU 1 PPIDE_TYPEATAPI .EQU 2 ; -; PPIDE DEVICE STATUS +; PPIDE DEVICE STATUS CODES ; PPIDE_STOK .EQU 0 PPIDE_STINVUNIT .EQU -1 @@ -207,75 +182,131 @@ PPIDE_STBSYTO .EQU -7 ; ; DRIVE SELECTION BYTES (FOR USE IN DRIVE/HEAD REGISTER) ; -PPIDE_DRVSEL: -PPIDE_DRVMASTER .DB %11100000 ; LBA, MASTER DEVICE -PPIDE_DRVSLAVE .DB %11110000 ; LBA, SLAVE DEVICE +;PPIDE_DRVSEL: +PPIDE_DRVMASTER .EQU %11100000 ; LBA, MASTER DEVICE +PPIDE_DRVSLAVE .EQU %11110000 ; LBA, SLAVE DEVICE ; ; PPIDE DEVICE CONFIGURATION ; -PPIDE_CFGSIZ .EQU 15 ; SIZE OF CFG TBL ENTRIES +PPIDE_CFGSIZ .EQU 18 ; SIZE OF CFG TBL ENTRIES ; ; PER DEVICE DATA OFFSETS ; PPIDE_DEV .EQU 0 ; OFFSET OF DEVICE NUMBER (BYTE) PPIDE_STAT .EQU 1 ; LAST STATUS (BYTE) PPIDE_TYPE .EQU 2 ; DEVICE TYPE (BYTE) -PPIDE_FLAGS .EQU 3 ; FLAG BITS BIT 0=CF, 1=LBA (BYTE) -PPIDE_MEDCAP .EQU 4 ; MEDIA CAPACITY (DWORD) -PPIDE_LBA .EQU 8 ; OFFSET OF LBA (DWORD) -PPIDE_DATALO .EQU 12 ; BASE PORT AND IDE DATA BUS LSB (8255 PORT A) (BYTE) -PPIDE_CTL .EQU 13 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)(BYTE) -PPIDE_PPI .EQU 14 ; 8255 CONTROL PORT(BYTE) +PPIDE_ACC .EQU 3 ; ACCESS FLAG BITS BIT 0=MASTER, 1=8BIT (BYTE) +PPIDE_MED .EQU 4 ; MEDIA FLAG BITS BIT 0=CF, 1=LBA (BYTE) +PPIDE_MEDCAP .EQU 5 ; MEDIA CAPACITY (DWORD) +PPIDE_LBA .EQU 9 ; OFFSET OF LBA (DWORD) +PPIDE_DATALO .EQU 13 ; BASE PORT AND IDE DATA BUS LSB (8255 PORT A) (BYTE) +PPIDE_CTL .EQU 14 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)(BYTE) +PPIDE_PPI .EQU 15 ; 8255 CONTROL PORT(BYTE) +PPIDE_PARTNER .EQU 16 ; PARTNER DEVICE (MASTER <-> SLAVE) +; +PPIDE_ACC_MAS .EQU %00000001 ; UNIT IS MASTER (ELSE SLAVE) +PPIDE_ACC_8BIT .EQU %00000010 ; UNIT WANTS 8 BIT I/O (ELSE 16 BIT) +; +PPIDE_MED_CF .EQU %00000001 ; MEDIA IS CF CARD +PPIDE_MED_LBA .EQU %00000010 ; MEDIA HAS LBA CAPABILITY ; PPIDE_CFGTBL: - ; DEVICE 0, PRIMARY MASTER - .DB 0 ; DRIVER DEVICE NUMBER +; +#IF (PPIDECNT >= 1) +; +PPIDE_DEV0M: ; DEVICE 0, MASTER + .DB 0 ; DRIVER RELATIVE DEVICE NUMBER (ASSIGNED DURING INIT) .DB 0 ; DEVICE STATUS .DB 0 ; DEVICE TYPE - .DB 0 ; FLAGS BYTE + .DB PPIDE_ACC_MAS | (PPIDE0A8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS + .DB 0 ; MEDIA FLAGS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA - .DB PPIDE0IO ; DATALO - .DB PPIDE0IO+2 ; CTL - .DB PPIDE0IO+3 ; PPI - ; DEVICE 1, PRIMARY SLAVE - .DB 1 ; DRIVER DEVICE NUMBER + .DB PPIDE0BASE ; DATALO + .DB PPIDE0BASE+2 ; CTL + .DB PPIDE0BASE+3 ; PPI + .DW PPIDE_DEV0S ; PARTNER +; +PPIDE_DEV0S: ; DEVICE 0, SLAVE + .DB 0 ; DRIVER RELATIVE DEVICE NUMBER (ASSIGNED DURING INIT) .DB 0 ; DEVICE STATUS .DB 0 ; DEVICE TYPE - .DB 0 ; FLAGS BYTE + .DB (PPIDE0B8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS + .DB 0 ; MEDIA FLAGS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA - .DB PPIDE0IO ; DATALO - .DB PPIDE0IO+2 ; CTL - .DB PPIDE0IO+3 ; PPI -#IF (PPICNT> 1) - ; DEVICE 2, PRIMARY MASTER - .DB 2 ; DRIVER DEVICE NUMBER + .DB PPIDE0BASE ; DATALO + .DB PPIDE0BASE+2 ; CTL + .DB PPIDE0BASE+3 ; PPI + .DW PPIDE_DEV0M ; PARTNER +; +#ENDIF +; +#IF (PPIDECNT >= 2) +; +PPIDE_DEV1M: ; DEVICE 1, MASTER + .DB 0 ; DRIVER RELATIVE DEVICE NUMBER (ASSIGNED DURING INIT) .DB 0 ; DEVICE STATUS .DB 0 ; DEVICE TYPE - .DB 0 ; FLAGS BYTE + .DB PPIDE_ACC_MAS | (PPIDE1A8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS + .DB 0 ; MEDIA FLAGS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA - .DB PPIDE1IO ; DATALO - .DB PPIDE1IO+2 ; CTL - .DB PPIDE1IO+3 ; PPI - ; DEVICE 3, PRIMARY SLAVE - .DB 3 ; DRIVER DEVICE NUMBER + .DB PPIDE1BASE ; DATALO + .DB PPIDE1BASE+2 ; CTL + .DB PPIDE1BASE+3 ; PPI + .DW PPIDE_DEV1S ; PARTNER +; +PPIDE_DEV1S: ; DEVICE 1, SLAVE + .DB 0 ; DRIVER RELATIVE DEVICE NUMBER (ASSIGNED DURING INIT) .DB 0 ; DEVICE STATUS .DB 0 ; DEVICE TYPE - .DB 0 ; FLAGS BYTE + .DB (PPIDE1B8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS + .DB 0 ; MEDIA FLAGS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA - .DB PPIDE1IO ; DATALO - .DB PPIDE1IO+2 ; CTL - .DB PPIDE1IO+3 ; PPI + .DB PPIDE1BASE ; DATALO + .DB PPIDE1BASE+2 ; CTL + .DB PPIDE1BASE+3 ; PPI + .DW PPIDE_DEV1M ; PARTNER +; +#ENDIF +; +#IF (PPIDECNT >= 3) +; +PPIDE_DEV2M: ; DEVICE 2, MASTER + .DB 0 ; DRIVER RELATIVE DEVICE NUMBER (ASSIGNED DURING INIT) + .DB 0 ; DEVICE STATUS + .DB 0 ; DEVICE TYPE + .DB PPIDE_ACC_MAS | (PPIDE2A8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS + .DB 0 ; MEDIA FLAGS + .DW 0,0 ; DEVICE CAPACITY + .DW 0,0 ; CURRENT LBA + .DB PPIDE2BASE ; DATALO + .DB PPIDE2BASE+2 ; CTL + .DB PPIDE2BASE+3 ; PPI + .DW PPIDE_DEV2S ; PARTNER +; +PPIDE_DEV2S: ; DEVICE 2, SLAVE + .DB 0 ; DRIVER RELATIVE DEVICE NUMBER (ASSIGNED DURING INIT) + .DB 0 ; DEVICE STATUS + .DB 0 ; DEVICE TYPE + .DB (PPIDE2B8BIT & PPIDE_ACC_8BIT) ; UNIT ACCESS FLAGS + .DB 0 ; MEDIA FLAGS + .DW 0,0 ; DEVICE CAPACITY + .DW 0,0 ; CURRENT LBA + .DB PPIDE2BASE ; DATALO + .DB PPIDE2BASE+2 ; CTL + .DB PPIDE2BASE+3 ; PPI + .DW PPIDE_DEV2M ; PARTNER +; #ENDIF ; #IF ($ - PPIDE_CFGTBL) != (PPIDE_DEVCNT * PPIDE_CFGSIZ) .ECHO "*** INVALID PPIDE CONFIG TABLE ***\n" #ENDIF ; - .DB $FF ; END MARKER + .DB $FF ; END OF TABLE MARKER ; ; THE IDE_WAITXXX FUNCTIONS ARE BUILT TO TIMEOUT AS NEEDED SO DRIVER WILL ; NOT HANG IF DEVICE IS UNRESPONSIVE. DIFFERENT TIMEOUTS ARE USED DEPENDING @@ -294,9 +325,6 @@ PPIDE_TOFAST .EQU 10 ; FAST TIMEOUT IS 0.5 SECS ;============================================================================= ; PPIDE_INIT: - CALL NEWLINE ; FORMATTING - PRTS("PPIDE:$") ; LABEL FOR IO ADDRESS -; ; COMPUTE CPU SPEED COMPENSATED TIMEOUT SCALER ; AT 1MHZ, THE SCALER IS 218 (50000US / 229TS = 218) ; SCALER IS THEREFORE 218 * CPU SPEED IN MHZ @@ -305,55 +333,61 @@ PPIDE_INIT: CALL MULT8X16 ; HL := DE * A LD (PPIDE_TOSCALER),HL ; SAVE IT ; -#IF (PPIDE8BIT) - PRTS(" 8BIT$") -#ENDIF - LD IY,PPIDE_CFGTBL - CALL PPIDE_DETECT ; CHECK FOR HARDWARE - JR Z,PPIDE_INIT00 ; CONTINUE IF PRESENT + XOR A ; ZERO ACCUM + LD (PPIDE_DEVNUM),A ; INIT DEV UNIT NUM FOR DYNAMIC ASSIGNMENT + LD IY,PPIDE_CFGTBL ; POINT TO START OF CONFIG TABLE ; - ; HARDWARE NOT PRESENT - PRTS(" NOT PRESENT$") - OR $FF ; SIGNAL FAILURE - RET +PPIDE_INIT1: + LD A,(IY) ; LOAD FIRST BYTE TO CHECK FOR END + CP $FF ; CHECK FOR END OF TABLE VALUE + JR NZ,PPIDE_INIT2 ; IF NOT END OF TABLE, CONTINUE + XOR A ; SIGNAL SUCCESS + RET ; AND RETURN +; +PPIDE_INIT2: + BIT 0,(IY+PPIDE_ACC) ; MASTER? + JR Z,PPIDE_INIT4 ; IF NOT MASTER, SKIP AHEAD ; -PPIDE_INIT00: - PRTS(" DEVICES=$") - LD A,PPIDE_DEVCNT - CALL PRTDECB + CALL NEWLINE ; FORMATTING + PRTS("PPIDE:$") ; LABEL FOR IO ADDRESS ; -; SETUP THE DISPATCH TABLE ENTRIES + PRTS(" IO=0x$") ; LABEL FOR IO ADDRESS + LD A,(IY+PPIDE_DATALO) ; GET IO BASE ADDRES + CALL PRTHEXBYTE ; DISPLAY IT ; - LD B,PPIDE_DEVCNT ; LOOP CONTROL - LD IY,PPIDE_CFGTBL ; START OF CFG TABLE -PPIDE_INIT0: - PUSH BC ; SAVE LOOP CONTROL + CALL PPIDE_DETECT ; PROBE FOR INTERFACE + JR Z,PPIDE_INIT3 ; GOT IT, MOVE ON TO INIT UNITS + CALL PC_SPACE ; FORMATTING + LD DE,PPIDE_STR_NOPPI ; NO PPI MESSAGE + CALL WRITESTR ; DISPLAY IT + JR PPIDE_INIT4 ; SKIP CFG ENTRY +; +PPIDE_INIT3: + CALL PPIDE_RESET ; RESET THE BUS + CALL PPIDE_INIT5 ; DETECT/INIT MASTER + PUSH IY ; SAVE CFG PTR + CALL PPIDE_GOPARTNER ; SWITCH IY TO PARTNER CFG + CALL PPIDE_INIT5 ; DETECT/INIT SLAVE + POP IY ; RESTORE CFG PTR +; +PPIDE_INIT4: + LD DE,PPIDE_CFGSIZ ; SIZE OF CFG TABLE ENTRY + ADD IY,DE ; BUMP POINTER + JR PPIDE_INIT1 ; AND LOOP +; +PPIDE_INIT5: + ; UPDATE DRIVER RELATIVE UNIT NUMBER IN CONFIG TABLE + LD A,(PPIDE_DEVNUM) ; GET NEXT UNIT NUM TO ASSIGN + LD (IY+PPIDE_DEV),A ; UPDATE IT + INC A ; BUMP TO NEXT UNIT NUM TO ASSIGN + LD (PPIDE_DEVNUM),A ; SAVE IT +; + ; ADD UNIT TO GLOBAL DISK UNIT TABLE LD BC,PPIDE_FNTBL ; BC := FUNC TABLE ADR PUSH IY ; CFG ENTRY POINTER POP DE ; COPY TO DE CALL DIO_ADDENT ; ADD ENTRY TO GLOBAL DISK DEV TABLE - LD BC,PPIDE_CFGSIZ ; SIZE OF CFG ENTRY - ADD IY,BC ; BUMP IY TO NEXT ENTRY - POP BC ; RESTORE BC - DJNZ PPIDE_INIT0 ; LOOP AS NEEDED -; - ; INITIALIZE THE PPIDE INTERFACE NOW - CALL PPIDE_RESET ; DO HARDWARE SETUP/INIT - RET NZ ; ABORT IF RESET FAILS -; - ; DEVICE DISPLAY LOOP - LD B,PPIDE_DEVCNT ; LOOP ONCE PER DEVICE - LD IY,PPIDE_CFGTBL ; START OF CFG TABLE -PPIDE_INIT1: - PUSH BC ; SAVE LOOP CONTROL - CALL PPIDE_INIT2 ; DISPLAY UNIT INFO - LD BC,PPIDE_CFGSIZ ; SIZE OF CFG ENTRY - ADD IY,BC ; BUMP IY TO NEXT ENTRY - POP BC ; RESTORE LOOP CONTROL - DJNZ PPIDE_INIT1 ; LOOP UNTIL DONE - RET ; DONE ; -PPIDE_INIT2: ; CHECK FOR BAD STATUS LD A,(IY+PPIDE_STAT) ; GET STATUS OR A ; SET FLAGS @@ -361,18 +395,13 @@ PPIDE_INIT2: ; CALL PPIDE_PRTPREFIX ; PRINT DEVICE PREFIX ; -; - PRTS(" IO=0x$") ; LABEL FOR IO ADDRESS - LD A,(IY+PPIDE_DATALO) - CALL PRTHEXBYTE -; -#IF (PPIDE8BIT) - PRTS(" 8BIT$") -#ENDIF + LD DE,PPIDE_STR_8BIT + BIT 1,(IY+PPIDE_ACC) ; 8 BIT ACCESS? + CALL NZ,WRITESTR ; ; PRINT LBA/NOLBA CALL PC_SPACE ; FORMATTING - BIT 1,(IY+PPIDE_FLAGS) ; TEST LBA FLAG + BIT 1,(IY+PPIDE_MED) ; TEST LBA FLAG LD DE,PPIDE_STR_NO ; POINT TO "NO" STRING CALL Z,WRITESTR ; PRINT "NO" BEFORE "LBA" IF LBA NOT SUPPORTED PRTS("LBA$") ; PRINT "LBA" REGARDLESS @@ -391,11 +420,10 @@ PPIDE_INIT2: CALL PRTDEC ; PRINT LOW WORD IN DECIMAL (HIGH WORD DISCARDED) PRTS("MB$") ; PRINT SUFFIX ; - XOR A ; SIGNAL SUCCESS - RET ; RETURN WITH A=0, AND Z SET + RET ; ;---------------------------------------------------------------------- -; PROBE FOR PPIDE HARDWARE +; PROBE FOR PPI HARDWARE ;---------------------------------------------------------------------- ; ; ON RETURN, ZF SET INDICATES HARDWARE FOUND @@ -408,20 +436,14 @@ PPIDE_DETECT: ; THEN THE BUS HOLD CIRCUITRY WILL READ BACK THE ZERO. SINCE ; WE ARE IN WRITE MODE, AN IDE CONTROLLER WILL NOT BE ABLE TO ; INTERFERE WITH THE VALUE BEING READ. - LD C,(IY+PPIDE_PPI) - LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE - OUT (C),A ; OUTPUT TO CONTROL WORD ; - LD C,(IY+PPIDE_DATALO) ; PPI PORT A + LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT ; -#IF USEZ80OPT -;; OUT (C),0 - .DB $ED,$71 -#ELSE + LD C,(IY+PPIDE_DATALO) ; PPI PORT A, DATALO XOR A ; VALUE ZERO OUT (C),A ; PUSH VALUE TO PORT -#ENDIF -; IN A,(C) ; GET PORT VALUE DCALL PC_SPACE DCALL PRTHEXBYTE @@ -485,7 +507,7 @@ PPIDE_IO: #ENDIF PUSH BC ; SAVE COUNTERS CALL PPIDE_SELUNIT ; HARDWARE SELECTION OF TARGET UNIT - CALL PPIDE_CHKDEVICE ; CHECK DEVICE AND CLEAR STATUS + CALL PPIDE_CHKERR ; CHECK FOR ERR STATUS AND RESET IF SO POP BC ; RESTORE COUNTERS JR NZ,PPIDE_IO3 ; BAIL OUT ON ERROR PPIDE_IO1: @@ -526,7 +548,7 @@ PPIDE_STATUS: PPIDE_DEVICE: LD D,DIODEV_PPIDE ; D := DEVICE TYPE LD E,(IY+PPIDE_DEV) ; E := PHYSICAL DEVICE NUMBER - BIT 0,(IY+PPIDE_FLAGS) ; TEST CF BIT IN FLAGS + BIT 0,(IY+PPIDE_MED) ; TEST CF BIT IN FLAGS LD C,%00000000 ; ASSUME NON-REMOVABLE HARD DISK JR Z,PPIDE_DEVICE1 ; IF Z, WE ARE DONE LD C,%01001000 ; OTHERWISE REMOVABLE COMPACT FLASH @@ -759,7 +781,7 @@ PPIDE_RUNCMD: JP NZ,PPIDE_CMDERR RET ; -; READ IDE DATA INTO BUFFER POINTED TO BY HL +; ; PPIDE_GETBUF: #IF (PPIDETRACE >= 3) @@ -771,71 +793,65 @@ PPIDE_GETBUF: RET NZ ; BAIL OUT IF TIMEOUT ; ; SETUP PPI TO READ - LD C,(IY+PPIDE_PPI) ; LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ - OUT (C),A ; DO IT + ;OUT (PPIDE_IO_PPI),A ; DO IT + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT ; ; SELECT READ/WRITE IDE REGISTER - DEC C ; LD C,(IY+PPIDE_CTL) LD A,PPIDE_REG_DATA ; DATA REGISTER + ;OUT (PPIDE_IO_CTL),A ; DO IT + LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS OUT (C),A ; DO IT - LD E,A ; E := READ UNASSERTED XOR PPIDE_CTL_DIOR ; SWAP THE READ LINE BIT LD D,A ; D := READ ASSERTED ; - LD B,0 ; LOOP SETUP - 256 ITERATIONS - - ; SETUP C WITH IO PORT - DEC C ; C = IY+PPIDE_DATAHI -#IF (PPIDE8BIT) ; - DEC C ; C = IY+PPIDE_DATALO -#ENDIF -; - CALL PPIDE_GETBUF1 ; FIRST PASS (FIRST 256 BYTES) - CALL PPIDE_GETBUF1 ; SECOND PASS (LAST 256 BYTES) -; - ;; CLEAN UP - ;XOR A ; ZERO A - ;OUT (PPIDE_IO_CTL),A ; RELEASE ALL BUS SIGNALS -; + ; LOOP SETUP + XOR A ; IMPORTANT, NEEDED FOR LOOP END COMPARISON + LD B,0 ; 256 ITERATIONS + LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS +; + BIT 1,(IY+PPIDE_ACC) ; 8 BIT? + JR Z,PPIDE_GETBUF1 ; IF NOT, DO 16 BIT + CALL PPIDE_GETBUF8 ; FIRST PASS (FIRST 256 BYTES) + CALL PPIDE_GETBUF8 ; SECOND PASS (LAST 256 BYTES) + JR PPIDE_GETBUF2 ; CONTINUE +PPIDE_GETBUF1: + CALL PPIDE_GETBUF16 ; FIRST PASS (FIRST 256 BYTES) + CALL PPIDE_GETBUF16 ; SECOND PASS (LAST 256 BYTES) +PPIDE_GETBUF2: CALL PPIDE_WAITRDY ; PROBLEMS IF THIS IS REMOVED! RET NZ CALL PPIDE_GETRES JP NZ,PPIDE_IOERR RET ; -PPIDE_GETBUF1: ; START OF READ LOOP -; -#IF (PPIDE8BIT) - INC C - INC C ; LD C,(IY+PPIDE_CTL) +PPIDE_GETBUF8: ; 8 BIT WIDE READ LOOP + ; ENTER W/ C = PPIDE_IO_CTL OUT (C),D ; ASSERT READ - DEC C - DEC C - INI ; GET AND SAVE NEXT BYTE - PUSH AF - INC C - INC C ; LD C,(IY+PPIDE_CTL) + DEC C ; CTL -> MSB + DEC C ; MSB -> LSB + INI ; READ FROM LSB + INC C ; LSB -> MSB + INC C ; MSB -> CTL OUT (C),E ; DEASSERT READ - DEC C - DEC C - POP AF -#ELSE - INC C ; LD C,(IY+PPIDE_CTL) + CP B ; B == A == 0? + JR NZ,PPIDE_GETBUF8 ; LOOP UNTIL DONE + RET +; +PPIDE_GETBUF16: ; 16 BIT WIDE READ LOOP + ; ENTER W/ C = PPIDE_IO_CTL OUT (C),D ; ASSERT READ - DEC C - DEC C - INI ; GET AND SAVE NEXT BYTE + DEC C ; CTL -> MSB + DEC C ; MSB -> LSB + INI ; READ FROM LSB INC C ; LSB -> MSB - INI ; GET AND SAVE NEXT BYTE - PUSH AF - INC C ; LD C,(IY+PPIDE_CTL) + INI ; READ MSB FOR 16 BIT + INC C ; MSB -> CTL OUT (C),E ; DEASSERT READ - DEC C - POP AF -#ENDIF - JR NZ,PPIDE_GETBUF1 ; LOOP UNTIL DONE + CP B ; B == A == 0? + JR NZ,PPIDE_GETBUF16 ; LOOP UNTIL DONE RET ; ; @@ -844,71 +860,69 @@ PPIDE_PUTBUF: #IF (PPIDETRACE >= 3) PRTS(" PUTBUF$") #ENDIF - +; ; WAIT FOR BUFFER CALL PPIDE_WAITDRQ ; WAIT FOR BUFFER READY RET NZ ; BAIL OUT IF TIMEOUT ; ; SETUP PPI TO WRITE - - LD C,(IY+PPIDE_PPI) LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE - OUT (C),A ; DO IT + ;OUT (PPIDE_IO_PPI),A ; DO IT + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT ; ; SELECT READ/WRITE IDE REGISTER - DEC C ; LD C,(IY+PPIDE_CTL) LD A,PPIDE_REG_DATA ; DATA REGISTER - OUT (C),A ; - + ;OUT (PPIDE_IO_CTL),A ; DO IT + LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + OUT (C),A ; DO IT LD E,A ; E := WRITE UNASSERTED XOR PPIDE_CTL_DIOW ; SWAP THE READ LINE BIT LD D,A ; D := WRITE ASSERTED ; - ; LOOP SETUP ; 256 ITERATIONS - LD B,0 ; SETUP C WITH IO PORT (LSB) - - DEC C ; LD C,(IY+PPIDE_DATAHI) -#IF (PPIDE8BIT) - DEC C ; LD C,(IY+PPIDE_DATALO) -#ENDIF -; - CALL PPIDE_PUTBUF1 ; FIRST PASS (FIRST 256 BYTES) - CALL PPIDE_PUTBUF1 ; SECOND PASS (LAST 256 BYTES) -; - ;; CLEAN UP - ;XOR A ; ZERO A - ;OUT (PPIDE_IO_CTL),A ; RELEASE ALL BUS SIGNALS -; + ; LOOP SETUP + XOR A ; IMPORTANT, NEEDED FOR LOOP END COMPARISON + LD B,0 ; 256 ITERATIONS + LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS +; + BIT 1,(IY+PPIDE_ACC) ; 8 BIT? + JR Z,PPIDE_PUTBUF1 ; IF NOT, DO 16 BIT + CALL PPIDE_PUTBUF8 ; FIRST PASS (FIRST 256 BYTES) + CALL PPIDE_PUTBUF8 ; SECOND PASS (LAST 256 BYTES) + JR PPIDE_PUTBUF2 ; CONTINUE +PPIDE_PUTBUF1: + CALL PPIDE_PUTBUF16 ; FIRST PASS (FIRST 256 BYTES) + CALL PPIDE_PUTBUF16 ; SECOND PASS (LAST 256 BYTES) +PPIDE_PUTBUF2: CALL PPIDE_WAITRDY ; PROBLEMS IF THIS IS REMOVED! RET NZ CALL PPIDE_GETRES JP NZ,PPIDE_IOERR RET ; -PPIDE_PUTBUF1: ; START OF READ LOOP -#IF (PPIDE8BIT) - OUTI ; PUT NEXT BYTE ON THE BUS - PUSH AF - INC C ; LD C,(IY+PPIDE_CTL) - INC C +PPIDE_PUTBUF8: ; 8 BIT WIDE WRITE LOOP + DEC C ; CTL -> MSB + DEC C ; MSB -> LSB + OUTI ; WRITE NEXT BYTE (LSB) + INC C ; LSB -> MSB + INC C ; MSB -> CTL OUT (C),D ; ASSERT WRITE OUT (C),E ; DEASSERT WRITE - DEC C - DEC C - POP AF -#ELSE - DEC C - OUTI ; PUT NEXT BYTE ON THE BUS (LSB) - INC C - OUTI ; PUT NEXT BYTE ON THE BUS (MSB) - PUSH AF - INC C ; LD C,(IY+PPIDE_CTL) + CP B ; B == A == 0? + JR NZ,PPIDE_PUTBUF8 ; LOOP UNTIL DONE + RET +; +PPIDE_PUTBUF16: ; 16 BIT WIDE WRITE LOOP + DEC C ; CTL -> MSB + DEC C ; MSB -> LSB + OUTI ; WRITE NEXT BYTE (LSB) + INC C ; LSB -> MSB + OUTI ; WRITE NEXT BYTE (MSB) + INC C ; MSB -> CTL OUT (C),D ; ASSERT WRITE OUT (C),E ; DEASSERT WRITE - DEC C - POP AF -#ENDIF - JR NZ,PPIDE_PUTBUF1 ; LOOP UNTIL DONE + CP B ; B == A == 0? + JR NZ,PPIDE_PUTBUF16 ; LOOP UNTIL DONE RET ; ; @@ -937,30 +951,27 @@ PPIDE_GETRES: ; SOFT RESET OF ALL DEVICES ON BUS ; PPIDE_RESET: +#IF (PPIDETRACE >= 3) + CALL PPIDE_PRTPREFIX + PRTS(" RESET$") +#ENDIF ; - PUSH BC - ; SETUP PPI TO READ - LD C,(IY+PPIDE_PPI) ;; LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ - OUT (C),A ; DO IT - + ;OUT (PPIDE_IO_PPI),A ; DO IT + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT +; ; PULSE IDE RESET LINE - LD C,(IY+PPIDE_CTL) LD A,PPIDE_CTL_RESET - OUT (C),A -; + ;OUT (PPIDE_IO_CTL),A + LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + OUT (C),A LD DE,20 CALL VDELAY -; -#IF USEZ80OPT -;; OUT (C),0 - .DB $ED,$71 -#ELSE - XOR A ; VALUE ZERO - OUT (C),A ; PUSH VALUE TO PORT -#ENDIF -; + XOR A + ;OUT (PPIDE_IO_CTL),A + OUT (C),A LD DE,20 CALL VDELAY ; @@ -979,30 +990,14 @@ PPIDE_RESET: LD DE,150000/16 ; ~???MS CALL VDELAY ; - ;; CLEAR OUT ALL DATA (FOR ALL UNITS) - ;LD HL,PPIDE_UDATA - ;LD BC,PPIDE_UDLEN - ;XOR A - ;CALL FILL -; - PUSH IY ; SAVE CURRENT DEVICE CFG PTR -; - ; PROBE / INITIALIZE ALL UNITS - LD B,PPIDE_DEVCNT ; NUMBER OF UNITS TO TRY - LD IY,PPIDE_CFGTBL ; START OF CFG TABLE -PPIDE_RESET1: - PUSH BC ; SAVE LOOP CONTROL - CALL PPIDE_INITUNIT ; PROBE/INIT UNIT - LD BC,PPIDE_CFGSIZ ; SIZE OF CFG ENTRY - ADD IY,BC ; BUMP IY TO NEXT ENTRY - POP BC ; RESTORE BC - DJNZ PPIDE_RESET1 ; LOOP AS NEEDED -; - POP IY ; RECOVER DEVICE CFG PTR - POP BC + CALL PPIDE_INITUNIT ; INIT CURRENT UNIT + PUSH IY ; SAVE CFG PTR + CALL PPIDE_GOPARTNER ; POINT TO PARTNER + CALL PPIDE_INITUNIT ; INIT PARTNER UNIT + POP IY ; RECOVER ORIG CFG PTR ; - XOR A ; SIGNAL SUCCESS - RET ; AND DONE + RET + ; ; ; @@ -1014,8 +1009,11 @@ PPIDE_INITUNIT: LD (HL),PPIDE_TONORM ; SET NORMAL TIMEOUT CALL PPIDE_PROBE ; DO PROBE - CALL Z,PPIDE_INITDEV ; IF FOUND, ATTEMPT TO INIT DEVICE + RET NZ ; JUST RETURN IF NOTHING THERE + CALL PPIDE_INITDEV ; IF FOUND, ATTEMPT TO INIT DEVICE + RET NZ ; IF FAILED, ALL DONE + RET ; ; TAKE ANY ACTIONS REQUIRED TO SELECT DESIRED PHYSICAL UNIT @@ -1025,18 +1023,15 @@ PPIDE_SELUNIT: CALL PPIDE_PRTPREFIX PRTS(" SELUNIT$") #ENDIF - PUSH HL ; SAVE HL, IT IS DESTROYED BELOW - PUSH IY - POP BC - LD A,(IY+PPIDE_DEV) ; GET DEVICE - AND $01 ; LS BIT DETERMINES MASTER/SLAVE - LD HL,PPIDE_DRVSEL - CALL ADDHLA - LD A,(HL) ; LOAD DRIVE/HEAD VALUE - POP HL ; RECOVER HL - LD (PPIDE_DRVHD),A ; SAVE IT -; - XOR A + BIT 0,(IY+PPIDE_ACC) ; MASTER? + JR Z,PPIDE_SELUNIT1 ; HANDLE SLAVE + LD A,PPIDE_DRVMASTER ; MASTER + JR PPIDE_SELUNIT2 +PPIDE_SELUNIT1: + LD A,PPIDE_DRVSLAVE ; SLAVE +PPIDE_SELUNIT2: + LD (PPIDE_DRVHD),A ; SAVE IT + XOR A ; SUCCESS RET ; ; @@ -1064,16 +1059,11 @@ PPIDE_PROBE: ; RETURN SOMETHING OTHER THAN ZERO. IF AN IDE CONTROLLER IS ; THERE, THEN THE VALUE WRITTEN TO PPI PORT A IS IGNORED ; BECAUSE THE WRITE SIGNAL IS NEVER PULSED. -; - LD C,(IY+PPIDE_DATALO) -#IF USEZ80OPT -;; OUT (C),0 - .DB $ED,$71 -#ELSE - XOR A ; VALUE ZERO - OUT (C),A ; PUSH VALUE TO PORT -#ENDIF -; + XOR A + ;OUT (PPIDE_IO_DATALO),A + LD C,(IY+PPIDE_DATALO) ; PPI PORT A, DATALO + OUT (C),A +; IN A,(PPIDE_REG_STAT) ; GET STATUS CALL PPIDE_IN .DB PPIDE_REG_STAT DCALL PC_SPACE @@ -1145,42 +1135,21 @@ PPIDE_INITDEV: OR A ; SET FLAGS JP Z,PPIDE_NOMEDIA ; EXIT SETTING NO MEDIA STATUS ; - ; CLEAR OUT UNIT SPECIFIC DATA, BUT PRESERVE THE EXISTING - ; VALUE OF THE UNIT TYPE WHICH WAS ESTABLISHED BY THE DEVICE - ; PROBES WHEN THE PPIDE BUS WAS RESET - ;PUSH AF ; SAVE UNIT TYPE VALUE FROM ABOVE - ;LD A,(IY+PPIDE_DEV) ; GET CURRENT DEVICE NUMBER - ;PUSH AF ; ... AND SAVE IT - ;;PUSH HL ; SAVE UNIT TYPE FIELD POINTER - ;;PPIDE_DPTR(0) ; SET HL TO START OF UNIT DATA - ;;LD BC,PPIDE_UDLEN - ;;XOR A - ;;CALL FILL - ;;POP HL ; RECOVER UNIT TYPE FIELD POINTER - ;;POP AF ; RECOVER UNIT TYPE VALUE - ;PUSH IY ; SET HL TO - ;POP HL ; ... START OF DEVICE INSTANCE DATA - ;LD BC,PPIDE_CFGSIZ ; SIZE OF CONFGI DATA TO CLEAR - ;XOR A ; FILL WITH ZERO - ;CALL FILL ; DO IT - ;POP AF ; RECOVER DEVICE NUMBER VALUE - ;LD (IY+PPIDE_DEV),A ; ... AND PUT IT BACK - ;POP AF ; RECOVER DEVICE TYPE VALUE - ;LD (IY+PPIDE_TYPE),A ; ... AND PUT IT BACK -; -#IF (PPIDE8BIT) + BIT 1,(IY+PPIDE_ACC) ; 8 BIT ACCESS? + JR Z,PPIDE_INITDEV0 ; NO, DO 16 BIT INIT LD A,PPIDE_FEAT_ENABLE8BIT ; FEATURE VALUE = ENABLE 8-BIT PIO -#ELSE - LD A,PPIDE_FEAT_DISABLE8BIT ; FEATURE VALUE = DISABLE 8-BIT PIO -#ENDIF CALL PPIDE_SETFEAT ; SET FEATURE - -#IF (PPIDE8BIT) + RET NZ ; BAIL OUT ON ERROR + JR PPIDE_INITDEV00 ; CONTINUE +; +PPIDE_INITDEV0: ; "REAL" IDE DRIVES MAY NOT ACCEPT THE DISABLE8BIT FEATURE COMMAND, ; SO IT IS ONLY AN ERROR IF WE ARE ATTEMPTING TO ENABLE8BIT. - ; CREDIT TO ED BRINDLEY FOR THIS CORRECTION. - RET NZ ; BAIL OUT ON ERROR -#ENDIF + ; CREDIT TO ED BRINDLEY FOR THIS CORRECTION. SO ERROR RETURN IGNORED HERE. + LD A,PPIDE_FEAT_DISABLE8BIT ; FEATURE VALUE = ENABLE 8-BIT PIO + CALL PPIDE_SETFEAT ; SET FEATURE, IGNORE ERRORS +; +PPIDE_INITDEV00: ; CALL PPIDE_IDENTIFY ; EXECUTE PPIDENTIFY COMMAND RET NZ ; BAIL OUT ON ERROR @@ -1188,9 +1157,8 @@ PPIDE_INITDEV: LD DE,HB_WRKBUF ; POINT TO BUFFER DCALL DUMP_BUFFER ; DUMP IT IF DEBUGGING ; - XOR A - LD (IY+PPIDE_FLAGS),0 ; CLEAR FLAGS - + LD (IY+PPIDE_MED),0 ; CLEAR MEDIA FLAGS +; ; DETERMINE IF CF DEVICE LD HL,HB_WRKBUF ; FIRST WORD OF IDENTIFY DATA HAS CF FLAG LD A,$8A ; FIRST BYTE OF MARKER IS $8A @@ -1200,14 +1168,14 @@ PPIDE_INITDEV: LD A,$84 ; SECOND BYTE OF MARKER IS $84 CP (HL) ; COMPARE JR NZ,PPIDE_INITDEV1 ; IF NOT MATCH, NOT CF - SET 0,(IY+PPIDE_FLAGS) ; SET FLAGS BIT FOR CF MEDIA + SET 0,(IY+PPIDE_MED) ; SET FLAGS BIT FOR CF MEDIA ; PPIDE_INITDEV1: ; DETERMINE IF LBA CAPABLE LD A,(HB_WRKBUF+98+1) ; GET BYTE WITH LBA BIT FROM BUFFER BIT 1,A ; CHECK THE LBA BIT JR Z,PPIDE_INITDEV2 ; NOT SET, BYPASS - SET 1,(IY+PPIDE_FLAGS) ; SET FLAGS BIT FOR LBA + SET 1,(IY+PPIDE_MED) ; SET FLAGS BIT FOR LBA ; PPIDE_INITDEV2: ; GET DEVICE CAPACITY AND SAVE IT @@ -1227,15 +1195,24 @@ PPIDE_INITDEV2: ; RET ; RETURN, A=0, Z SET ; +; SWITCH IY POINTER FROM CURRENT UNIT CFG TO PARTNER UNIT CFG +; +PPIDE_GOPARTNER: + PUSH HL ; SAVE HL + LD L,(IY+PPIDE_PARTNER) ; GET PARTNER ENTRY + LD H,(IY+PPIDE_PARTNER+1) ; ... + PUSH HL ; MOVE HL + POP IY ; ... TO IY + POP HL ; RESTORE INCOMING HL + RET ; AND DONE ; +; CHECK CURRENT DEVICE FOR ERROR STATUS AND ATTEMPT TO RECOVER +; VIA RESET IF DEVICE IS IN ERROR. ; -PPIDE_CHKDEVICE: +PPIDE_CHKERR: LD A,(IY+PPIDE_STAT) ; GET STATUS OR A ; SET FLAGS - RET Z ; RETURN IF ALL IS WELL -; - ; ATTEMPT TO REINITIALIZE HERE??? - JP PPIDE_ERR + CALL NZ,PPIDE_RESET ; IF ERROR STATUS, RESET BUS RET ; ; @@ -1291,7 +1268,7 @@ PPIDE_WAITBSY1: LD DE,(PPIDE_TOSCALER) ; CPU SPEED SCALER TO INNER LOOP VAR PPIDE_WAITBSY2: ;IN A,(PPIDE_REG_STAT) ; READ STATUS - CALL PPIDE_IN ; 17TS + 204TS + CALL PPIDE_IN ; 17TS + 170TS .DB PPIDE_REG_STAT ; 0TS LD C,A ; SAVE IT ; 4TS AND %10000000 ; TO FILL (OR READY TO FILL) ; 7TS @@ -1301,60 +1278,69 @@ PPIDE_WAITBSY2: OR E ; 4TS JR NZ,PPIDE_WAITBSY2 ; 12TS DJNZ PPIDE_WAITBSY1 ; ----- - JP PPIDE_BSYTO ; EXIT WITH BSYTO ERR ; 246TS + JP PPIDE_BSYTO ; EXIT WITH BSYTO ERR ; 229TS ; ; READ A VALUE FROM THE DEVICE POINTED TO BY IY AND RETURN IT IN A ; -PPIDE_IN: ; IY POINT TO CURRENT CFG TABLE - EX (SP),HL ; GET PARM POINTER ; 19TS +PPIDE_IN: + EX (SP),HL ; GET PARM POINTER ; 19TS PUSH BC ; SAVE INCOMING BC ; 11TS - LD C,(IY+PPIDE_PPI) ; ; 19TS LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ; 7TS - OUT (C),A ; DO IT ; 12TS + ;OUT (PPIDE_IO_PPI),A ; DO IT ; 11TS + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT ; LD B,(HL) ; GET CTL PORT VALUE ; 7TS - DEC C ; LD C,(IY+PPIDE_CTL) ; 4TS + ;LD C,PPIDE_IO_CTL ; SETUP PORT TO WRITE ; 7TS + ;LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + DEC C ; SET IDE ADDRESS OUT (C),B ; SET ADDRESS LINES ; 12TS - SET 6,B ; TURN ON WRITE BIT ; 8TS - OUT (C),B ; ASSERT WRITE LINE ; 12TS + SET 6,B ; TURN ON READ BIT ; 8TS + OUT (C),B ; ASSERT READ LINE ; 12TS ; - DEC C ; 4TS - DEC C ; LD C,(IY+PPIDE_DATALO) ; 4TS - IN A,(C) ; GET DATA VALUE FROM DEVICE ; 12TS + ;IN A,(PPIDE_IO_DATALO) ; GET DATA VALUE FROM DEVICE ; 11TS + DEC C + DEC C + IN A,(C) ; GET DATA VALUE FROM DEVICE + INC C + INC C ; - RES 6,B ; CLEAR WRITE BIT ; 8TS - INC C ; 4TS - INC C ; LD C,(IY+PPIDE_CTL) ; 4TS - OUT (C),B ; DEASSERT WRITE LINE ; 12TS + RES 6,B ; CLEAR READ BIT ; 8TS + OUT (C),B ; DEASSERT READ LINE ; 12TS POP BC ; RECOVER INCOMING BC ; 10TS INC HL ; POINT PAST PARM ; 6TS EX (SP),HL ; RESTORE STACK ; 19TS RET ; 10TS -; ; ----- -; ; 204TS -; ; ----- -; OUTPUT A TO 3 2 0 2 ; -PPIDE_OUT: ; IY POINT TO CURRENT CFG TABLE +; OUTPUT VALUE IN A TO THE DEVICE POINTED TO BY IY +; +PPIDE_OUT: + ; *** TODO *** FIX ORDER OF SET/CLEAR WRITE LINE EX (SP),HL ; GET PARM POINTER PUSH BC ; SAVE INCOMING BC - LD C,(IY+PPIDE_PPI) - LD B,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE - OUT (C),B ; DO IT - + PUSH AF ; PRESERVE INCOMING VALUE + LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE + ;OUT (PPIDE_IO_PPI),A ; DO IT + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT + POP AF ; RECOVER VALUE TO WRITE +; LD B,(HL) ; GET IDE ADDRESS VALUE - DEC C ; LD C,(IY+PPIDE_CTL) + ;LD C,PPIDE_IO_CTL ; SETUP PORT TO WRITE + ;LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + DEC C ; SET IDE ADDRESS OUT (C),B ; SET ADDRESS LINES SET 5,B ; TURN ON WRITE BIT OUT (C),B ; ASSERT WRITE LINE ; - DEC C - DEC C ; LD C,(IY+PPIDE_DATALO) + DEC C + DEC C + ;OUT (PPIDE_IO_DATALO),A ; SEND DATA VALUE TO DEVICE OUT (C),A ; SEND DATA VALUE TO DEVICE + INC C + INC C ; RES 5,B ; CLEAR WRITE BIT - INC C - INC C ; LD C,(IY+PPIDE_CTL) OUT (C),B ; DEASSERT WRITE LINE POP BC ; RECOVER INCOMING BC INC HL ; POINT PAST PARM @@ -1460,38 +1446,39 @@ PPIDE_PRTSTAT3: ; PRINT ALL REGISTERS DIRECTLY FROM DEVICE ; DEVICE MUST BE SELECTED PRIOR TO CALL ; -; -; PRINT ALL REGISTERS DIRECTLY FROM DEVICE -; DEVICE MUST BE SELECTED PRIOR TO CALL -; PPIDE_REGDUMP: PUSH AF PUSH BC - PUSH DE + push DE CALL PC_SPACE CALL PC_LBKT - LD C,(IY+PPIDE_PPI) ; LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ - OUT (C),A ; DO IT + ;OUT (PPIDE_IO_PPI),A ; DO IT + LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + OUT (C),A ; WRITE IT + LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS LD E,PPIDE_REG_CMD - LD D,7 + LD B,7 PPIDE_REGDUMP1: LD A,E ; REGISTER ADDRESS - LD C,(IY+PPIDE_CTL) - OUT (C),A ; SET IT + ;OUT (PPIDE_IO_CTL),A ; SET IT + OUT (C),A ; REGISTER ADDRESS XOR PPIDE_CTL_DIOR ; SET BIT TO ASSERT READ LINE + ;OUT (PPIDE_IO_CTL),A ; ASSERT READ OUT (C),A ; ASSERT READ -; - LD C,(IY+PPIDE_DATALO) + ;IN A,(PPIDE_IO_DATALO) ; GET VALUE + DEC C ; CTL -> MSB + DEC C ; MSB -> LSB IN A,(C) ; GET VALUE + INC C ; LSB -> MSB + INC C ; MSB -> CTL CALL PRTHEXBYTE ; DISPLAY IT -; - LD A,E ; - LD C,(IY+PPIDE_CTL) ; RELOAD ADDRESS W/ READ UNASSERTED - OUT (C),E -; + ;LD A,C ; RELOAD ADDRESS W/ READ UNASSERTED + ;OUT (PPIDE_IO_CTL),A ; AND SET IT + OUT (C),E ; RELOAD ADDRESS W/ READ UNASSERTED + ;DEC C ; NEXT LOWER REGISTER DEC E ; NEXT LOWER REGISTER - DEC D ; DEC LOOP COUNTER + DEC B ; DEC LOOP COUNTER CALL NZ,PC_SPACE ; FORMATTING JR NZ,PPIDE_REGDUMP1 ; LOOP AS NEEDED CALL PC_RBKT ; FORMATTING @@ -1552,6 +1539,8 @@ PPIDE_STR_STBSYTO .TEXT "BUSY TIMEOUT$" PPIDE_STR_STUNK .TEXT "UNKNOWN ERROR$" ; PPIDE_STR_NO .TEXT "NO$" +PPIDE_STR_NOPPI .TEXT "PPI NOT PRESENT$" +PPIDE_STR_8BIT .TEXT " 8-BIT$" ; ;============================================================================= ; DATA STORAGE @@ -1565,3 +1554,5 @@ PPIDE_IOFNADR .DW 0 ; PENDING IO FUNCTION ADDRESS PPIDE_DRVHD .DB 0 ; CURRENT DRIVE/HEAD MASK ; PPIDE_DSKBUF .DW 0 ; ACTIVE DISK BUFFER +; +PPIDE_DEVNUM .DB 0 ; TEMP DEVICE NUM USED DURING INIT diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 7172ef96..1d7c96e6 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -28,7 +28,6 @@ TRUE .EQU ~FALSE USENONE .EQU 0 ; NO DEBUG USEXIO .EQU 1 ; BASIC SERIAL DRIVER USEMIO .EQU 2 ; MEMORY BUFFER DRIVER -USEZ80OPT .EQU FALSE ; USE UNOFFICIAL OP CODES WBWDEBUG .EQU USENONE ; ; PRIMARY HARDWARE PLATFORMS diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc index 530202ad..ed995cd7 100644 --- a/Source/HBIOS/ver.inc +++ b/Source/HBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.27" +#DEFINE BIOSVER "2.9.2-pre.28"