ez80: new firmware feature to configure on-chip flash w/s

Source/HBIOS/cfg_rcez80.asm

@@ -45,20 +45,26 @@ MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
-EZ80_MEM_CYCLES	.EQU	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CYCLES
-EZ80_MEM_MIN_NS	.EQU	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_ASSIGN = EZ80WSMD_CALC
-EZ80_MEM_WS	.EQU	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_WAIT
-EZ80_MEM_MIN_WS	.EQU	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CALC
+EZ80_MEM_CYCLES	.EQU	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_MEM_MIN_NS	.EQU	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_MEM_WS	.EQU	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_MEM_MIN_WS	.EQU	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
-EZ80_IO_CYCLES	.EQU	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CYCLES
-EZ80_IO_WS	.EQU	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_WAIT
-EZ80_IO_MIN_NS	.EQU	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_ASSIGN = EZ80WSMD_CALC
-EZ80_IO_MIN_WS	.EQU	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CALC
+EZ80_IO_CYCLES	.EQU	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_IO_WS	.EQU	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_IO_MIN_NS	.EQU	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_IO_MIN_WS	.EQU	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 
 ; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD
-EZ80_ASSIGN	.EQU	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
+EZ80_WSMD_TYP	.EQU	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
+;
+; BUS TIMING FOR ON CHIP ROM
+;
+EZ80_FLSH_WS	.EQU	1		; WAIT STATES FOR ON CHIP FLASH (0-7)
+EZ80_FLSH_MIN_NS .EQU	60	; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_FWSMD_TYP	.EQU	EZ80WSMD_CALC	; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)
 ;
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR

Source/HBIOS/ez80cpudrv.asm

@@ -46,7 +46,24 @@ EZ80_PREINIT:
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
-#IF (EZ80_ASSIGN == EZ80WSMD_CYCLES)
+#IF (EZ80_FWSMD_TYP == EZ80WSMD_WAIT)
+	LD	L, EZ80_FLSH_WS
+	EZ80_UTIL_FLSHWS_SET()
+	LD	A, L
+	LD	(EZ80_PLT_FLSHWS), A
+#ENDIF
+
+#IF (EZ80_FWSMD_TYP == EZ80WSMD_CALC)
+	LD	HL, EZ80_FLSH_MIN_NS
+	LD	E, 0
+	EZ80_CPY_EHL_TO_UHL
+	EZ80_UTIL_FLSHFQ_SET()
+	LD	A, L
+	LD	(EZ80_PLT_FLSHWS), A
+#ENDIF
+
+
+#IF (EZ80_WSMD_TYP == EZ80WSMD_CYCLES)
 	LD	L, EZ80_MEM_CYCLES
 	OR	$80
 	EZ80_UTIL_MEMTM_SET()
@@ -62,7 +79,7 @@ EZ80_PREINIT:
 	RET
 #ENDIF
 
-#IF (EZ80_ASSIGN == EZ80WSMD_CALC)
+#IF (EZ80_WSMD_TYP == EZ80WSMD_CALC)
 	LD	HL, EZ80_MEM_MIN_NS
 	LD	E, 0
 	EZ80_CPY_EHL_TO_UHL
@@ -80,7 +97,7 @@ EZ80_PREINIT:
 	LD	A, L
 	LD	(EZ80_PLT_IOWS), A
 #ENDIF
-#IF (EZ80_ASSIGN == EZ80WSMD_WAIT)
+#IF (EZ80_WSMD_TYP == EZ80WSMD_WAIT)
 	LD	L, EZ80_MEM_WS
 	EZ80_UTIL_MEMTM_SET()
 	LD	A, L
@@ -113,7 +130,6 @@ EZ80_RPT_MCYC:
 	CALL	PRTSTRD
 	.TEXT	" MEM B/C, $"
 
-
 EZ80_RPT_IOTIMING:
 	LD	A, (EZ80_PLT_IOWS)
 	BIT	7, A
@@ -121,14 +137,20 @@ EZ80_RPT_IOTIMING:
 
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" I/O W/S$"
-	RET
+	.TEXT	" I/O W/S, $"
+	JR	EZ80_RPT_FSH_TIMINGS
 
 EZ80_RPT_ICYC:
 	AND	$7F
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" I/O B/C$"
+	.TEXT	" I/O B/C, $"
+
+EZ80_RPT_FSH_TIMINGS:
+	LD	A, (EZ80_PLT_FLSHWS)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" FSH W/S$"
 	RET
 
 EZ80_RPT_FIRMWARE:
@@ -184,6 +206,8 @@ EZ80_PLT_MEMWS:
 	.DB	EZ80_MEM_WS
 EZ80_PLT_IOWS:
 	.DB	EZ80_IO_WS
+EZ80_PLT_FLSHWS:
+	.DB	EZ80_FLSH_WS
 
 EZ80_PLT_VERSION:
 	.DB	0, 0, 0, 0

Source/HBIOS/ez80instr.inc

@@ -23,6 +23,9 @@
   #DEFINE EZ80_UTIL_IOTM_GET 		XOR A \ LD B, 11 \ EZ80_FN
   #DEFINE EZ80_UTIL_MEMTMFQ_SET		XOR A \ LD B, 12 \ EZ80_FN
   #DEFINE EZ80_UTIL_IOTMFQ_SET		XOR A \ LD B, 13 \ EZ80_FN
+  #DEFINE EZ80_UTIL_FLSHWS_SET		XOR A \ LD B, 14 \ EZ80_FN
+  #DEFINE EZ80_UTIL_FLSHWS_GET		XOR A \ LD B, 15 \ EZ80_FN
+  #DEFINE EZ80_UTIL_FLSHFQ_SET		XOR A \ LD B, 16 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 		LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 		LD A, 1	\ LD B, 1 \ EZ80_FN

Source/HBIOS/sn76489.asm

@@ -43,7 +43,7 @@ SN76489_PORT16_RIGHT	.EQU	(IO_SEGMENT*256) + SN76489_PORT_RIGHT
 
 #IF (CPUFAM == CPU_EZ80)
 ; The eZ80 configuration must have sufficient bus cycles configured for this driver
-; to work.  See the entries: (EZ80_ASSIGN and EZ80_IO_CYCLES, EZ80_IO_WS, EZ80_IO_MIN_NS)
+; to work.  See the entries: (EZ80_WSMD_TYP and EZ80_IO_CYCLES, EZ80_IO_WS, EZ80_IO_MIN_NS)
 ;
 ; For CPU @ ~18Mhz, the eZ80 must have at least 4 Bus Cycles for I/O operations
 ; For CPU @ ~24Mhz, the eZ80 must have at least 5 Bus Cycles for I/O operations