forked from MirrorRepos/RomWBW
Browse Source
- The naming of ZZRCC was incorrectly ZZRC. Corrected. - Max Scane has provided a small bug fix for CLRDIR. - Minor build updates for new HTalk utility.patch v3.4.0-dev.5
Wayne Warthen
2 years ago
58 changed files with 285 additions and 197 deletions
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@ -1,4 +0,0 @@ |
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@echo off |
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setlocal |
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|
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pushd ZZRC && call Build || exit /b & popd |
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@ -0,0 +1,4 @@ |
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@echo off |
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setlocal |
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|
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pushd ZZRCC && call Build || exit /b & popd |
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@ -0,0 +1,41 @@ |
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ZRC has no real ROM. It has a single 2048K RAM chip. There |
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are two startup modes supported by RomWBW. |
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|
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The normal startup mode treats the first 512KB like ROM and the |
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remaining 1536KB as RAM. The first 512KB (pseudo-ROM) must be preloaded |
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by the ZRC CF Loader. This mode simulates a normal ROM-based RomWBW |
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startup. |
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|
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Bank Contents Description |
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---- -------- ----------- |
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0x0 BOOT Boot Bank (HBIOS image) + |
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0x1 IMG0 ROM Loader, Monitor, ROM OSes | |
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0x2 IMG1 ROM Applications | Pseudo-ROM |
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0x3 IMG2 Reserved | |
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0x4-0xF ROMD ROM Disk Banks + |
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0x10 BIOS HBIOS Bank (operating) |
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0x11-0x3B RAMD RAM Disk Banks |
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0x3C BUF OS Buffers (CP/M3) |
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0x3D AUX Aux Bank (CP/M 3, BPBIOS, etc.) |
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0x3E USR User Bank (CP/M TPA, etc.) |
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0x3F COM Common Bank, Upper 32KB |
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|
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The ROMless startup mode treats the entire 2048KB as RAM. However, in |
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this mode, only the first 512KB of RAM is utilized. This is because |
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the RAM Disk is seeded by the CF Loader which is currently constrained |
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to loading 512KB. The entire 512KB of RAM (less the top 32KB) must be |
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preloaded by the ZRC CF Loader. There will be no ROM disk available |
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under RomWBW. There will be a RAM Disk and it's initial contents will |
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be seeded by the image loaded by the CF Loader. |
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|
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Bank Contents Description |
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-------- -------- ----------- |
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0x0 BIOS HBIOS Bank (operating) |
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0x1 IMG0 ROM Loader, Monitor, ROM OSes |
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0x2 IMG1 ROM Applications |
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0x3 IMG2 Reserved |
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0x4-0xB RAMD RAM Disk Banks |
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0xC BUF OS Buffers (CP/M3) |
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0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.) |
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0xE USR User Bank (CP/M TPA, etc.) |
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0xF COM Common Bank, Upper 32KB |
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@ -1,32 +0,0 @@ |
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ZZRCC has no real ROM. It has a single 512K RAM chip. The first |
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256K of the RAM chip is loaded from the CF card. This 256K is |
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treated like ROM by RomWBW. The remainder of the RAM (256K) is |
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treated like RAM by RomWBW. |
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|
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Because of the memory constraints, notice that there is no RAM Disk, |
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only a ROM disk. If you perform a ROM boot to an OS, the A: drive |
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will be the ROM disk and will not be writable. Booting a ROM OS |
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on this system is not typical since the system has a CF card by |
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definition. |
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|
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Bank ROM RAM RAM |
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---- --- --- --- |
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0 HBIOS (IMG) |
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1 ROMLDR+MON+CP/M2+ZSYS |
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2 FTH+BAS+TBAS+PLAY+USR |
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3 RESERVED |
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4 ROMDISK |
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5 ROMDISK |
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6 ROMDISK |
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7 ROMDISK |
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|
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8 BUF (CPM3) BUF (CPM3) |
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9 BUF (CPM3) BUF (CPM3) |
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A BUF (CPM3) BUF (CPM3) |
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B BUF (CPM3) BUF (CPM3) |
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C AUX (CPM3) TPA (CPM3) |
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D HBIOS (EXEC) HBIOS (EXEC) |
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E TPA-LO OS (CPM3) |
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F COMMON (TPA-HI) COMMON (TPA-HI) |
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|
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--WBW 6:40 PM 2/16/2022 |
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@ -1,41 +0,0 @@ |
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:: @echo off |
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setlocal |
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|
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set ROMFILE=..\..\Binary\RCZ280_zzrc.rom |
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set ROMSIZE=262144 |
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set TOOLS=../../Tools |
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set PATH=%TOOLS%\srecord;%PATH% |
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if exist ..\..\Binary\RCZ280_zzrc.rom call :build_zzrc |
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if exist ..\..\Binary\RCZ280_zzrc_ram.rom call :build_zzrc_ram |
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goto :eof |
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:build_zzrc |
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|
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrc.rom -binary -offset 0x24000 -o temp.dat -binary |
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move temp.dat ..\..\Binary\hd1k_zzrc_prefix.dat |
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|
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copy /b ..\..\Binary\hd1k_zzrc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrc_combo.img || exit /b |
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goto :eof |
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:build_zzrc_ram |
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|
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary |
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move temp.dat ..\..\Binary\hd1k_zzrc_ram_prefix.dat |
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|
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copy /b ..\..\Binary\hd1k_zzrc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrc_ram_combo.img || exit /b |
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goto :eof |
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@ -1,48 +0,0 @@ |
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HD1KZZRCPREFIX = hd1k_zzrc_prefix.dat |
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HD1KZZRCCOMBOIMG = hd1k_zzrc_combo.img |
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HD1KZZRCRAMPREFIX = hd1k_zzrc_ram_prefix.dat |
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HD1KZZRCRAMCOMBOIMG = hd1k_zzrc_ram_combo.img |
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ZZRCROM = ../../Binary/RCZ280_zzrc.rom |
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ZZRCRAMROM = ../../Binary/RCZ280_zzrc_ram.rom |
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HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
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../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img |
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OBJECTS := |
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ifneq ($(wildcard $(ZZRCROM)),) |
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OBJECTS += $(HD1KZZRCPREFIX) $(HD1KZZRCCOMBOIMG) |
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endif |
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ifneq ($(wildcard $(ZZRCRAMROM)),) |
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OBJECTS += $(HD1KZZRCRAMPREFIX) $(HD1KZZRCRAMCOMBOIMG) |
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endif |
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DEST=../../Binary |
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|
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TOOLS = ../../Tools |
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|
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include $(TOOLS)/Makefile.inc |
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DIFFPATH = $(DIFFTO)/Binary |
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|
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$(HD1KZZRCPREFIX): |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCROM) -binary -offset 0x24000 -o temp.dat -binary |
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mv temp.dat $@ |
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|
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$(HD1KZZRCRAMPREFIX): |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary |
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mv temp.dat $@ |
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|
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$(HD1KZZRCCOMBOIMG): $(HD1KZZRCPREFIX) $(HD1KIMGS) |
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cat $^ > $@ |
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|
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$(HD1KZZRCRAMCOMBOIMG): $(HD1KZZRCRAMPREFIX) $(HD1KIMGS) |
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cat $^ > $@ |
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@ -1,31 +0,0 @@ |
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Start Length Sector Count Description |
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------- ------- ------- ------- ----------------------------------------- |
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0x00000 0x00100 0x000 0x001 CF Boot Loader (first 256 bytes) |
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0x00100 0x00100 0x000 0x001 RomWBW Partition Table (last 256 bytes) |
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0x00200 0x1EE00 0x001 0x0F7 Filler |
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0x1F000 0x01000 0x0F8 0x008 ZZRCC Monitor / RomWBW Loader |
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0x20000 0x04000 0x100 0x020 Filler |
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0x24000 0x40000 0x120 0x200 RomWBW (256KB ROM image) |
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0x64000 0x9C000 0x320 0x4E0 Filler |
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0x100000 0x800 Slices |
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|
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Notes |
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----- |
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|
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- At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000 |
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- CPLD ROM (CF bootstrap mode) loads CF Boot Loader (256B) to 0xB000 and runs it |
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- CF Boot Loader loads ZZRCC Monitor to 0xB000 and runs it starting at address 0xB400 |
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- Monitor (Boot RomWBW) loads RomWBW ROM image to first 8 banks of RAM, then runs it starting at address 0x000 |
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|
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Possible alternative layout: |
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|
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Start Length Sector Count Description |
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------- ------- ------- ------- ----------------------------------------- |
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0x00000 0x00100 0 1 CF Boot Loader (first 256 bytes) |
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0x00100 0x00100 0 1 RomWBW Partition Table (last 256 bytes) |
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0x00200 0x01000 0x001 0x008 ZZRCC Monitor / RomWBW Loader |
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0x01200 0x7EE00 0x009 0x3F7 Filler |
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0x80000 0x40000 0x400 0x200 RomWBW (256KB ROM image) |
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0xC0000 0x40000 0x600 0x200 Filler |
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0x100000 0x800 Slices (0x1E partition start) |
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|
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@ -0,0 +1,39 @@ |
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ZZRCC has no real ROM. It has a single 512K RAM chip. There |
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are two startup modes supported by RomWBW. |
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|
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The normal startup mode treats the first 256KB like ROM and the second |
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256KB as RAM. The first 256KB (pseudo-ROM) must be preloaded by the |
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ZZRCC CF Loader. This mode simulates a normal ROM-based RomWBW |
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startup. |
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|
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Bank Contents Description |
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---- -------- ----------- |
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0x0 BOOT Boot Bank (HBIOS image) + |
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0x1 IMG0 ROM Loader, Monitor, ROM OSes | |
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0x2 IMG1 ROM Applications | Pseudo-ROM |
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0x3 IMG2 Reserved | |
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0x4-0x7 ROMD ROM Disk Banks + |
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0x8 BIOS HBIOS Bank (operating) |
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0x9-0xB RAMD RAM Disk Banks |
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0xC BUF OS Buffers (CP/M3) |
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0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.) |
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0xE USR User Bank (CP/M TPA, etc.) |
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0xF COM Common Bank, Upper 32KB |
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|
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The ROMless startup mode treats the entire 512KB as RAM. The entire |
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512KB of RAM (less the top 32KB) must be preloaded by the ZZRCC CF |
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Loader. There will be no ROM disk available under RomWBW. There |
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will be a RAM Disk and it's initial contents will be seeded by the |
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image loaded by the CF Loader. |
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|
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Bank Contents Description |
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-------- -------- ----------- |
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0x0 BIOS HBIOS Bank (operating) |
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0x1 IMG0 ROM Loader, Monitor, ROM OSes |
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0x2 IMG1 ROM Applications |
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0x3 IMG2 Reserved |
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0x4-0xB RAMD RAM Disk Banks |
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0xC BUF OS Buffers (CP/M3) |
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0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.) |
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0xE USR User Bank (CP/M TPA, etc.) |
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0xF COM Common Bank, Upper 32KB |
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@ -0,0 +1,41 @@ |
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:: @echo off |
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setlocal |
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set ROMFILE=..\..\Binary\RCZ280_zzrcc.rom |
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set ROMSIZE=262144 |
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set TOOLS=../../Tools |
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set PATH=%TOOLS%\srecord;%PATH% |
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if exist ..\..\Binary\RCZ280_zzrcc.rom call :build_zzrcc |
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if exist ..\..\Binary\RCZ280_zzrcc_ram.rom call :build_zzrcc_ram |
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goto :eof |
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:build_zzrcc |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary |
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move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat |
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|
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copy /b ..\..\Binary\hd1k_zzrcc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrcc_combo.img || exit /b |
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goto :eof |
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|
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:build_zzrcc_ram |
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|
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary |
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move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat |
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|
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copy /b ..\..\Binary\hd1k_zzrcc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrcc_ram_combo.img || exit /b |
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|
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goto :eof |
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@ -0,0 +1,48 @@ |
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HD1KZZRCCPREFIX = hd1k_zzrcc_prefix.dat |
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HD1KZZRCCCOMBOIMG = hd1k_zzrcc_combo.img |
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HD1KZZRCCRAMPREFIX = hd1k_zzrcc_ram_prefix.dat |
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HD1KZZRCCRAMCOMBOIMG = hd1k_zzrcc_ram_combo.img |
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ZZRCCROM = ../../Binary/RCZ280_zzrcc.rom |
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ZZRCCRAMROM = ../../Binary/RCZ280_zzrcc_ram.rom |
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HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
|
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../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img |
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|
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OBJECTS := |
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|
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ifneq ($(wildcard $(ZZRCCROM)),) |
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OBJECTS += $(HD1KZZRCCPREFIX) $(HD1KZZRCCCOMBOIMG) |
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endif |
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|
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ifneq ($(wildcard $(ZZRCCRAMROM)),) |
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OBJECTS += $(HD1KZZRCCRAMPREFIX) $(HD1KZZRCCRAMCOMBOIMG) |
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endif |
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|
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DEST=../../Binary |
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|
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TOOLS = ../../Tools |
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|
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include $(TOOLS)/Makefile.inc |
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|
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DIFFPATH = $(DIFFTO)/Binary |
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|
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$(HD1KZZRCCPREFIX): |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCROM) -binary -offset 0x24000 -o temp.dat -binary |
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mv temp.dat $@ |
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|
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$(HD1KZZRCCRAMPREFIX): |
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srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary |
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srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCRAMROM) -binary -offset 0x24000 -o temp.dat -binary |
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mv temp.dat $@ |
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|
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$(HD1KZZRCCCOMBOIMG): $(HD1KZZRCCPREFIX) $(HD1KIMGS) |
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cat $^ > $@ |
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|
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$(HD1KZZRCCRAMCOMBOIMG): $(HD1KZZRCCRAMPREFIX) $(HD1KIMGS) |
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cat $^ > $@ |
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@ -0,0 +1,25 @@ |
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ZZRCC Disk Prefix Layout |
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======================== |
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|
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---- Bytes ---- --- Sectors --- |
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Start Length Start Length Description |
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------- ------- ------- ------- --------------------------- |
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0x00000 0x00100 0 0.5 CF Boot Loader |
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0x00100 0x00100 0.5 0.5 RomWBW Partition Table |
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0x00200 0x1EE00 1 247 Unused |
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0x1F000 0x01000 248 8 ZZRCC Monitor v0.5 |
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0x20000 0x04000 256 32 Unused |
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0x24000 0x80000 288 1024 RomWBW |
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0xA4000 0x5C000 1312 736 Unused |
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0x100000 2048 Start of slices (partition 0x1E) |
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|
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Notes |
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----- |
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|
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- At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000 |
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- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it |
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- CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it |
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- ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM |
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- ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000 |
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|
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-WBW 2:36 PM 10/8/2023 |
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