@ -63,64 +63,51 @@
;
; CONSTANTS
;
; RTC SBC SBC-004 N8 N8-CSIO SC126
; ----- ------- ------- ------- ------- -------
; D7 WR RTC_OUT RTC_OUT RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
; D6 WR RTC_CLK RTC_CLK RTC_CLK RTC_CLK RTC_CLK
; D5 WR /RTC_WE /RTC_WE /RTC_WE /RTC_WE /RTC_WE
; D4 WR RTC_CE RTC_CE RTC_CE RTC_CE RTC_CE
; D3 WR NC SPK NC NC /SPI_CS1
; D2 WR NC CLKHI SPI_CS SPI_CS /SPI_CS2
; D1 WR -- -- SPI_CLK NC FS
; D0 WR -- -- SPI_DI NC I2C_SCL
; RTC SBC SBC-004 MFPIC N8 N8-CSIO SC126
; ----- ------- ------- ------- ------- ------- -------
; D7 WR RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
; D6 WR RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK
; D5 WR /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE
; D4 WR RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE
; D3 WR NC SPK /RTC_CE NC NC /SPI_CS2
; D2 WR NC CLKHI RTC_CLK SPI_CS SPI_CS /SPI_CS1
; D1 WR -- -- RTC_WE SPI_CLK NC FS
; D0 WR -- -- RTC_OUT SPI_DI NC I2C_SCL
;
; D7 RD -- -- -- -- I2C_SDA
; D6 RD CFG CFG SPI_DO CFG --
; D5 RD -- -- -- -- --
; D4 RD -- -- -- -- --
; D3 RD -- -- -- -- --
; D2 RD -- -- -- -- --
; D1 RD -- -- -- -- --
; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN
; D7 RD -- -- -- -- -- I2C_SDA
; D6 RD CFG CFG -- SPI_DO CFG --
; D5 RD -- -- -- -- -- --
; D4 RD -- -- -- -- -- --
; D3 RD -- -- -- -- -- --
; D2 RD -- -- -- -- -- --
; D1 RD -- -- -- -- -- --
; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN
;
# IF ( DS RTCMODE = = DS RTCMODE_STD )
;
DSRTC_BASE .EQU RTC ; RTC PORT ON ALL SBC SERIES Z80 PLATFORMS
;
DSRTC_DATA .EQU % 10000000 ; BIT 7 CONTROLS RTC DATA (I/O) LINE
DSRTC_CLK .EQU % 01000000 ; BIT 6 CONTROLS RTC CLOCK LINE, 1 = HIGH
DSRTC_RD .EQU % 00100000 ; BIT 5 CONTROLS DATA DIRECTION, 1 = READ
DSRTC_CE .EQU % 00010000 ; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED)
;
DSRTC_RESET .EQU % 00000000 ; ALL LOW
;
# ENDIF
;
# IF ( DS RTCMODE = = DS RTCMODE_SC126 )
;
DSRTC_BASE .EQU RTC ; RTC PORT
;
DSRTC_DATA .EQU % 10000000 ; BIT 7 CONTROLS RTC DATA (I/O) LINE
DSRTC_CLK .EQU % 01000000 ; BIT 6 CONTROLS RTC CLOCK LINE, 1 = HIGH
DSRTC_RD .EQU % 00100000 ; BIT 5 CONTROLS DATA DIRECTION, 1 = READ
DSRTC_CE .EQU % 00010000 ; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED )
DSRTC_DATA .EQU % 10000000 ; BIT 7 IS RTC DATA OUT
DSRTC_CLK .EQU % 01000000 ; BIT 6 IS RTC CLOCK (CLK)
DSRTC_RD .EQU % 00100000 ; BIT 5 IS DATA DIRECTION (/WE)
DSRTC_CE .EQU % 00010000 ; BIT 4 IS CHIP ENABLE (CE)
;
DSRTC_RESET .EQU % 00001101 ; /SPI_CS1, /SPI_CS2, & I2C_SCL HIGH
DSRTC_MASK .EQU % 11110000 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
DSRTC_IDLE .EQU % 00100000 ; QUIESCENT STATE
;
# ENDIF
;
# IF ( DS RTCMODE = = DS RTCMODE_MFPIC )
;
DSRTC_BASE .EQU $ 43 ; RTC PORT ON MF/PIC
;
DSRTC_DATA .EQU % 00000001 ; BIT 0 CONTROLS RTC DATA (I/O) LINE
DSRTC_CLK .EQU % 00000100 ; BIT 2 CONTROLS RTC CLOCK LINE, 1 = HIGH
DSRTC_WR .EQU % 00000010 ; BIT 1 CONTROLS DATA DIRECTION, 1 = WRITE
DSRTC_CE .EQU % 00001000 ; BIT 3 CONTROLS RTC CE LINE, 0 = ENABLED
DSRTC_DATA .EQU % 00000001 ; BIT 0 IS RTC DATA OUT
DSRTC_CLK .EQU % 00000100 ; BIT 2 IS RTC CLOCK (CLK)
DSRTC_WR .EQU % 00000010 ; BIT 1 IS DATA DIRECTION (WE)
DSRTC_CE .EQU % 00001000 ; BIT 3 CHIP ENABLE (/CE)
;
DSRTC_RESET .EQU % 00001000 ; ALL LOW, BUT CE = 1
DSRTC_MASK .EQU % 00001111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
DSRTC_IDLE .EQU % 00101000 ; QUIESCENT STATE
;
# ENDIF
;
@ -138,9 +125,13 @@ DSRTC_INIT:
# IF ( DS RTCMODE = = DS RTCMODE_MFPIC )
PRTS ( "MFPIC$" )
# ENDIF
# IF ( DS RTCMODE = = DS RTCMODE_SC126 )
PRTS ( "SC126$" )
# ENDIF
;
; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
; TO THEIR QUIESENT STATE
LD A ,( RTCVAL )
AND DS RTC_MASK
OR DS RTC_IDLE
LD ( RTCVAL ), A
;
; CHECK FOR CLOCK HALTED
CALL DS RTC_TSTCLK
@ -162,21 +153,21 @@ DSRTC_INIT1:
CALL PRTDT
# IF DS RTCCHG ; FORCE_RTC_CHARGE_ENABLE
LD C , $ 8 E ; ACCESS WRITE PROT REG
LD E , $ 8 E ; ACCESS WRITE PROT REG
CALL DS RTC_CMD ;
LD A , $ 00 ; WRITE PROTECT OFF
LD E , $ 00 ; WRITE PROTECT OFF
CALL DS RTC_PUT ;
CALL DS RTC_END ; FINISH CMD
LD C , $ 90 ; ACCESS CHARGE REGISTER
LD E , $ 90 ; ACCESS CHARGE REGISTER
CALL DS RTC_CMD ;
LD A , $ A5 ; STD CHARGE VALUES
LD E , $ A5 ; STD CHARGE VALUES
CALL DS RTC_PUT ;
CALL DS RTC_END ; FINISH REG WRITE
LD C , $ 8 E ; ACCESS WRITE PROT REG
LD E , $ 8 E ; ACCESS WRITE PROT REG
CALL DS RTC_CMD ;
LD A , $ 80 ; WRITE PROTECT ON
LD E , $ 80 ; WRITE PROTECT ON
CALL DS RTC_PUT ;
CALL DS RTC_END ; FINISH CMD
# ENDIF
@ -341,12 +332,13 @@ DSRTC_TIM2CLK:
; TEST CLOCK FOR CHARGE DATA
;
DSRTC_TSTCHG:
LD C , $ 91 ; CHARGE RESISTOR & DIODE VALUES
LD E , $ 91 ; CHARGE RESISTOR & DIODE VALUES
CALL DS RTC_CMD ; SEND THE COMMAND
CALL DS RTC_GET ; READ THE REGISTER
CALL DS RTC_END ; FINISH IT
AND % 11110000 ; CHECK FOR
CP % 10100000 ; ENABLED FLAG
LD A , E ; VALUE TO A
AND % 11110000 ; CHECK FOR
CP % 10100000 ; ENABLED FLAG
RET
;
; TEST CLOCK FOR VALID DATA
@ -355,23 +347,24 @@ DSRTC_TSTCHG:
; 1 = HALTED
;
DSRTC_TSTCLK:
LD C , $ 81 ; SECONDS REGISTER HAS CLOCK HALT FLAG
LD E , $ 81 ; SECONDS REGISTER HAS CLOCK HALT FLAG
CALL DS RTC_CMD ; SEND THE COMMAND
CALL DS RTC_GET ; READ THE REGISTER
CALL DS RTC_END ; FINISH IT
LD A , E ; VALUE TO A
AND % 10000000 ; HIGH ORDER BIT IS CLOCK HALT
RET
;
; BURST READ CLOCK DATA INTO BUFFER AT HL
;
DSRTC_RDCLK:
LD C , $ BF ; COMMAND = $BF TO BURST READ CLOCK
LD E , $ BF ; COMMAND = $BF TO BURST READ CLOCK
CALL DS RTC_CMD ; SEND COMMAND TO RTC
LD B , DS RTC_BUFSIZ ; B IS LOOP COUNTER
DSRTC_RDCLK1:
PUSH BC ; PRESERVE BC
CALL DS RTC_GET ; GET NEXT BYTE
LD ( HL ), A ; SAVE IN BUFFER
LD ( HL ), E ; SAVE IN BUFFER
INC HL ; INC BUF POINTER
POP BC ; RESTORE BC
DJNZ DS RTC_RDCLK1 ; LOOP IF NOT DONE
@ -380,34 +373,35 @@ DSRTC_RDCLK1:
; BURST WRITE CLOCK DATA FROM BUFFER AT HL
;
DSRTC_WRCLK:
LD C , $ 8 E ; COMMAND = $8E TO WRITE CONTROL REGISTER
LD E , $ 8 E ; COMMAND = $8E TO WRITE CONTROL REGISTER
CALL DS RTC_CMD ; SEND COMMAND
XOR A ; $00 = UNPROTECT
LD E , $ 00 ; $00 = UNPROTECT
CALL DS RTC_PUT ; SEND VALUE TO CONTROL REGISTER
CALL DS RTC_END ; FINISH IT
;
LD C , $ BE ; COMMAND = $BE TO BURST WRITE CLOCK
LD E , $ BE ; COMMAND = $BE TO BURST WRITE CLOCK
CALL DS RTC_CMD ; SEND COMMAND TO RTC
LD B , DS RTC_BUFSIZ ; B IS LOOP COUNTER
DSRTC_WRCLK1:
PUSH BC ; PRESERVE BC
LD A ,( HL ) ; GET NEXT BYTE TO WRITE
LD E ,( HL ) ; GET NEXT BYTE TO WRITE
CALL DS RTC_PUT ; PUT NEXT BYTE
INC HL ; INC BUF POINTER
POP BC ; RESTORE BC
DJNZ DS RTC_WRCLK1 ; LOOP IF NOT DONE
LD A , $ 80 ; ADD CONTROL REG BYTE, $80 = PROTECT ON
LD E , $ 80 ; ADD CONTROL REG BYTE, $80 = PROTECT ON
CALL DS RTC_PUT ; WRITE REQUIRED 8TH BYTE
JP DS RTC_END ; FINISH IT
;
# IF (( DS RTCMODE = = DS RTCMODE_STD ) | ( DS RTCMODE = = DS RTCMODE_SC126 ))
;
; SEND COMMAND IN C TO RTC
; SEND COMMAND IN E TO RTC
; ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
; THE COMMAND IS SENT VIA A PUT. CE AND CLK ARE LEFT HIGH ! THIS
; THE COMMAND IS SENT VIA A PUT. CE AND CLK ARE LEFT ASSERTED! THIS
; IS INTENTIONAL BECAUSE WHEN THE CLOCK IS LOWERED, THE FIRST BIT
; WILL BE PRESENTED TO READ (IN THE CASE OF A READ CMD).
;
; N.B. REGISTER A CONTAINS WORKING VALUE OF LATCH PORT AND MUST NOT
; BE MODIFIED BETWEEN CALLS TO DSRTC_CMD, DSRTC_PUT, AND DSRTC_GET.
;
; 0) ASSUME ALL LINES UNDEFINED AT ENTRY
; 1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA)
; 2) WAIT 1US
@ -416,19 +410,22 @@ DSRTC_WRCLK1:
; 5) PUT COMMAND
;
DSRTC_CMD:
LD A , DS RTC_RESET ; QUIESCENT STATE
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
LD A ,( RTCVAL ) ; INIT A WITH QUIESCENT STATE
OUT ( DS RTC_BASE ), A ; WRITE TO PORT
CALL DL Y2 ; DELAY 2 * 27 T-STATES
XOR DS RTC_CE ; NOW SET CE HIGH
# IF ( DS RTCMODE = = DS RTCMODE_MFPIC )
AND ~ DS RTC_CE ; ASSERT CE (LOW)
# ELSE
OR DS RTC_CE ; ASSERT CE (HIGH)
# ENDIF
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y2 ; DELAY 2 * 27 T-STATES
LD A , C ; LOAD COMMAND
CALL DS RTC_PUT ; WRITE IT
RET
;
; WRITE BYTE IN A TO THE RTC
; WRITE BYTE IN A TO THE RTC. CE IS IMPLICITY ASSERTED AT
; THE START. CE AND CLK ARE LEFT HIGH AT THE END IN CASE
; WRITE BYTE IN E TO THE RTC
; WRITE BYTE IN E TO THE RTC. CE IS IMPLICITY ASSERTED AT
; THE START. CE AND CLK ARE LEFT ASSERTED AT THE END IN CASE
; NEXT ACTION IS A READ.
;
; 0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
@ -442,135 +439,36 @@ DSRTC_CMD:
;
DSRTC_PUT:
LD B , 8 ; LOOP FOR 8 BITS
LD C , A ; SAVE THE WORKING VALUE
DSRTC_PUT1:
LD A , DS RTC_RESET | DS RTC_CE ; SET CLOCK LOW
OUT ( DS RTC_BASE ), A ; DO IT
CALL DL Y1 ; DELAY 27 T-STATES
LD A , C ; RECOVER WORKING VALUE
RRCA ; ROTATE NEXT BIT TO SEND INTO BIT 7
LD C , A ; SAVE WORKING VALUE
AND % 10000000 ; ISOLATE THE DATA BIT
OR DS RTC_RESET | DS RTC_CE ; KEEP CE HIGH
OUT ( DS RTC_BASE ), A ; ASSERT DATA BIT ON BUS
OR DS RTC_CLK ; SET CLOCK HI
OUT ( DS RTC_BASE ), A ; DO IT
CALL DL Y1 ; DELAY 27 T-STATES
DJNZ DS RTC_PUT1 ; LOOP IF NOT DONE
RET
;
; READ BYTE FROM RTC, RETURN VALUE IN A
; READ THE NEXT BYTE FROM THE RTC INTO A. CE IS IMPLICITLY
; ASSERTED AT THE START. CE AND CLK ARE LEFT HIGH AT
; THE END. CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD!
;
; 0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
; 1) SET RD HI AND CLOCK LOW
; 3) WAIT 250NS (CLOCK PUTS DATA BIT ON BUS)
; 4) READ DATA BIT
; 5) SET CLOCK HI
; 6) WAIT 250NS
; 7) LOOP FOR 8 DATA BITS
; 8) EXIT WITH CE,CLK,RD HI
;
DSRTC_GET:
LD C , 0 ; INITIALIZE WORKING VALUE TO 0
LD B , 8 ; LOOP FOR 8 BITS
DSRTC_GET1:
LD A , DS RTC_RESET | DS RTC_CE | DS RTC_RD ; SET CLK LO
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y2 ; DELAY 2 * 27 T-STATES
IN A ,( DS RTC_BASE ) ; READ THE RTC PORT
AND % 00000001 ; ISOLATE THE DATA BIT
OR C ; COMBINE WITH WORKING VALUE
RRCA ; ROTATE FOR NEXT BIT
LD C , A ; SAVE WORKING VALUE
LD A , DS RTC_RESET | DS RTC_CE | DS RTC_CLK | DS RTC_RD ; CLOCK BACK TO HI
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y1 ; DELAY 27 T-STATES
DJNZ DS RTC_GET1 ; LOOP IF NOT DONE (13)
LD A , C ; GET RESULT INTO A
RET
;
; COMPLETE A COMMAND SEQUENCE
; FINISHES UP A COMMAND SEQUENCE.
; DOES NOT DESTROY ANY REGISTERS.
;
; 1) SET ALL LINES LO
;
DSRTC_END:
PUSH AF ; SAVE AF
LD A , DS RTC_RESET ; QUIESCENT STATE
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
POP AF ; RESTORE AF
RET
;
# ENDIF
;
# IF ( DS RTCMODE = = DS RTCMODE_MFPIC )
;
;
; SEND COMMAND IN C TO RTC
; ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
; THE COMMAND IS SENT VIA A PUT. CE AND CLK ARE LEFT ACTIVE! THIS
; IS INTENTIONAL BECAUSE WHEN THE CLOCK IS LOWERED, THE FIRST BIT
; WILL BE PRESENTED TO READ (IN THE CASE OF A READ CMD).
;
; 0) ASSUME ALL LINES UNDEFINED AT ENTRY
; 1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA)
; 2) WAIT 1US
; 3) SET CE HI
; 4) WAIT 1US
; 5) PUT COMMAND
;
DSRTC_CMD:
;XOR A ; ALL LINES LOW TO RESET
LD A , DS RTC_RESET ; QUIESCENT STATE
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y2 ; DELAY 2 * 27 T-STATES
XOR DS RTC_CE ; NOW ASSERT CE
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y2 ; DELAY 2 * 27 T-STATES
LD A , C ; LOAD COMMAND
CALL DS RTC_PUT ; WRITE IT
RET
;
; WRITE BYTE IN A TO THE RTC
; WRITE BYTE IN A TO THE RTC. CE IS IMPLICITY ASSERTED AT
; THE START. CE AND CLK ARE LEFT ASSERTED AT THE END IN CASE
; NEXT ACTION IS A READ.
;
; 0) ASSUME ENTRY WITH CE ASSERTED, OTHERS UNDEFINED
; 1) CLOCK -> LOW
; 2) WAIT 250NS
; 3) SET DATA ACCORDING TO BIT VALUE
; 4) CLOCK -> HIGH
; 5) WAIT 250NS (CLOCK READS DATA BIT FROM BUS)
; 6) LOOP FOR 8 DATA BITS
; 7) EXIT WITH CE AND CLOCK ASSERTED
;
DSRTC_PUT:
LD B , 8 ; LOOP FOR 8 BITS
LD C , A ; SAVE THE WORKING VALUE
LD A , DS RTC_RESET | DS RTC_WR | DS RTC_CLK ; MODE=WRITE, CLOCK ON, CE ACTIVE (0)
OR DS RTC_WR ; SET WRITE MODE
# ELSE
AND ~ DS RTC_RD ; SET WRITE MODE
# ENDIF
DSRTC_PUT1:
XOR DS RTC_CLK ; FLIP CLOCK OFF
AND ~ DS RTC_CLK ; SET CLOCK LOW
OUT ( DS RTC_BASE ), A ; DO IT
CALL DL Y1 ; DELAY 27 T-STATES
# IF ( DS RTCMODE = = DS RTCMODE_MFPIC )
RRA ; PREP ACCUM TO GET DATA BIT IN CARRY
RR C ; ROTATE NEXT BIT TO SEND INTO CARRY
RR E ; ROTATE NEXT BIT TO SEND INTO CARRY
RLA ; ROTATE BITS BACK TO CORRECT POSTIIONS
# ELSE
RLA ; PREP ACCUM TO GET DATA BIT IN CARRY
RR E ; ROTATE NEXT BIT TO SEND INTO CARRY
RRA ; ROTATE BITS BACK TO CORRECT POSTIIONS
# ENDIF
OUT ( DS RTC_BASE ), A ; ASSERT DATA BIT ON BUS
XOR DS RTC_CLK ; FLIP CLOCK ON
OUT ( DS RTC_BASE ), A ; DO IT, DATA BIT SENT ON RISING EDGE
OR DS RTC_CLK ; SET CLOCK HI
OUT ( DS RTC_BASE ), A ; DO IT
CALL DL Y1 ; DELAY 27 T-STATES
DJNZ DS RTC_PUT1 ; LOOP IF NOT DONE
RET
;
; READ BYTE FROM RTC, RETURN VALUE IN A
; READ THE NEXT BYTE FROM THE RTC INTO A . CE IS IMPLICITLY
; ASSERTED AT THE START. CE AND CLK ARE LEFT HIGH AT
; THE END. CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD!
; READ BYTE FROM RTC, RETURN VALUE IN E
; READ THE NEXT BYTE FROM THE RTC INTO E. CE IS IMPLICITLY
; ASSERTED AT THE START. CE AND CLK ARE LEFT ASSERTED AT
; THE END. CLOCK *MUST* BE LEFT ASSERTED FROM DSRTC_CMD!
;
; 0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
; 1) SET RD HI AND CLOCK LOW
@ -582,38 +480,38 @@ DSRTC_PUT1:
; 8) EXIT WITH CE,CLK,RD HI
;
DSRTC_GET:
LD C , 0 ; INITIALIZE WORKING VALUE TO 0
LD E , 0 ; INITIALIZE WORKING VALUE TO 0
LD B , 8 ; LOOP FOR 8 BITS
LD A , DS RTC_RESET | DS RTC_CLK ; MODE=READ, CLOCK ON, CE ACTIVE (0)
# IF ( DS RTCMODE = = DS RTCMODE_MFPIC )
AND ~ DS RTC_WR ; SET READ MODE
# ELSE
OR DS RTC_RD ; SET READ MODE
# ENDIF
DSRTC_GET1:
XOR DS RTC_CLK ; FLIP CLOCK OFF
OUT ( DS RTC_BASE ), A ; DO IT
CALL DL Y2 ; DELAY 2 * 27 T-STATES
AND ~ DS RTC_CLK ; SET CLK LO
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y1 ; DELAY 2 * 27 T-STATES
PUSH AF ; SAVE PORT VALUE
IN A ,( DS RTC_BASE ) ; READ THE RTC PORT
RRA ; DATA BIT TO CARRY
RR C ; SHIFT INTO WORKING VALUE
LD A , DS RTC_RESET | DS RTC_CLK ; CLOCK ON
RR E ; SHIFT INTO WORKING VALUE
POP AF ; RESTORE PORT VALUE
OR DS RTC_CLK ; CLOCK BACK TO HI
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
CALL DL Y1 ; DELAY 27 T-STATES
DJNZ DS RTC_GET1 ; LOOP IF NOT DONE
LD A , C ; GET RESULT INTO A
DJNZ DS RTC_GET1 ; LOOP IF NOT DONE (13)
RET
;
; COMPLETE A COMMAND SEQUENCE
; FINISHES UP A COMMAND SEQUENCE.
; DOES NOT DESTROY ANY REGISTERS.
;
; 1) BACK TO QUIESCENT STATE
; 1) SET ALL LINES BACK TO QUIESCENT STATE
;
DSRTC_END:
PUSH AF ; SAVE AF
;XOR A ; ALL LINES OFF TO CLEAN UP
LD A , DS RTC_RESET ; QUIESCENT STATE
OUT ( DS RTC_BASE ), A ; WRITE TO RTC PORT
POP AF ; RESTORE AF
RET
;
# ENDIF
LD A ,( RTCVAL ) ; INIT A WITH QUIESCENT STATE
OUT ( DS RTC_BASE ), A ; WRITE TO PORT
RET ; RETURN
;
; WORKING VARIABLES
;
Wayne Warthen
7 years ago