diff --git a/Source/ZRC/Build.cmd b/Source/ZRC/Build.cmd
index 3cef14a5..181db8ab 100644
--- a/Source/ZRC/Build.cmd
+++ b/Source/ZRC/Build.cmd
@@ -14,8 +14,8 @@ goto :eof
 :build_zrc
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat
@@ -27,8 +27,8 @@ goto :eof
 :build_zrc_ram
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zrc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zrc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat
diff --git a/Source/ZRC/ZRC Disk Layout.txt b/Source/ZRC/ZRC Disk Layout.txt
index 441b1108..6159704c 100644
--- a/Source/ZRC/ZRC Disk Layout.txt	
+++ b/Source/ZRC/ZRC Disk Layout.txt	
@@ -4,8 +4,8 @@ ZRC Disk Prefix Layout
 ---- Bytes ----   --- Sectors ---
 Start   Length    Start   Length    Description
 ------- -------   ------- -------   ---------------------------
-0x00000 0x00100   0       0.5       CF Boot Loader
-0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
 0x00200 0x1EE00   1       247       Unused
 0x1F000 0x01000   248     8         ZRC Monitor v0.7
 0x20000 0x04000   256     32        Unused
@@ -17,9 +17,9 @@ Notes
 -----
 
 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
 - ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
 - ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
 
--- WBW 2:30 PM 10/8/2023
\ No newline at end of file
+-- WBW 3:30 PM 10/12/2023
\ No newline at end of file
diff --git a/Source/ZRC/zrc_cfldr.bin b/Source/ZRC/zrc_cfldr.bin
index 9a28f43b..dc481183 100644
Binary files a/Source/ZRC/zrc_cfldr.bin and b/Source/ZRC/zrc_cfldr.bin differ
diff --git a/Source/ZRC/zrc_ptbl.bin b/Source/ZRC/zrc_ptbl.bin
index 5e3a2a4d..5e9fc41d 100644
Binary files a/Source/ZRC/zrc_ptbl.bin and b/Source/ZRC/zrc_ptbl.bin differ
diff --git a/Source/ZZRCC/Build.cmd b/Source/ZZRCC/Build.cmd
index 9a934aa7..f520b11a 100644
--- a/Source/ZZRCC/Build.cmd
+++ b/Source/ZZRCC/Build.cmd
@@ -17,8 +17,8 @@ goto :eof
 :build_zzrcc
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat
@@ -30,8 +30,8 @@ goto :eof
 :build_zzrcc_ram
 
 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat
diff --git a/Source/ZZRCC/ZZRCC Disk Layout.txt b/Source/ZZRCC/ZZRCC Disk Layout.txt
index 8dd73653..6aac2a6f 100644
--- a/Source/ZZRCC/ZZRCC Disk Layout.txt	
+++ b/Source/ZZRCC/ZZRCC Disk Layout.txt	
@@ -4,8 +4,8 @@ ZZRCC Disk Prefix Layout
 ---- Bytes ----   --- Sectors ---
 Start   Length    Start   Length    Description
 ------- -------   ------- -------   ---------------------------
-0x00000 0x00100   0       0.5       CF Boot Loader
-0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00000 0x001BE   0       1         CF Boot Loader
+0x001B8 0x00048                     RomWBW Partition Table
 0x00200 0x1EE00   1       247       Unused
 0x1F000 0x01000   248     8         ZZRCC Monitor v0.5
 0x20000 0x04000   256     32        Unused
@@ -17,9 +17,9 @@ Notes
 -----
 
 - At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (512B) from start of CF (MBR) to 0xB000 and runs it
 - CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
 - ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
 - ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
 
--WBW 2:36 PM 10/8/2023
\ No newline at end of file
+-WBW 3:30 PM 10/12/2023
\ No newline at end of file
diff --git a/Source/ZZRCC/zzrcc_cfldr.bin b/Source/ZZRCC/zzrcc_cfldr.bin
index 04b6c228..9c8fce82 100644
Binary files a/Source/ZZRCC/zzrcc_cfldr.bin and b/Source/ZZRCC/zzrcc_cfldr.bin differ
diff --git a/Source/ZZRCC/zzrcc_ptbl.bin b/Source/ZZRCC/zzrcc_ptbl.bin
index 5e3a2a4d..5e9fc41d 100644
Binary files a/Source/ZZRCC/zzrcc_ptbl.bin and b/Source/ZZRCC/zzrcc_ptbl.bin differ
diff --git a/Source/ver.inc b/Source/ver.inc
index f43d5766..28980241 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	4
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.4.0-dev.7"
+#DEFINE BIOSVER	"3.4.0-dev.8"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
diff --git a/Source/ver.lib b/Source/ver.lib
index 52e14bb1..088eec18 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	4
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.4.0-dev.7"
+	db	"3.4.0-dev.8"
 	endm