diff --git a/Source/Apps/rtc.asm b/Source/Apps/rtc.asm
index c49157f5..7d456da7 100644
--- a/Source/Apps/rtc.asm
+++ b/Source/Apps/rtc.asm
@@ -33,6 +33,8 @@
 ;
 ;[2023/07/07] v1.9 Support DUODYNE
 ;
+;[2024/09/02] v1.10  Support Genesis STD Z180
+;
 ; Constants
 ;
 mask_data	.EQU	%10000000	; RTC data line
@@ -52,6 +54,7 @@ PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
 PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
 PORT_DUO	.EQU	$94		; RTC port for DUODYNE
+PORT_STDZ180 .EQU $84         ; RTC Port for STD Bus Z180 board
 
 
 BDOS		.EQU	5		; BDOS invocation vector
@@ -1143,7 +1146,13 @@ HINIT:
 	CP	17		; DUODYNE
 	JP	Z,RTC_INIT2
 ;
-	; Unknown platform
+	LD	C,PORT_STDZ180
+	LD	DE,PLT_STDZ180
+	CP	21		; STD Z180
+	JP	Z,RTC_INIT2
+;
+
+; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
 	LD	C,9		; BDOS string display function
 	CALL	BDOS		; Do it
@@ -1769,6 +1778,7 @@ PLT_RCZ280	.TEXT	", RCBus Z280 RTC Module Latch Port 0xC0\r\n$"
 PLT_MBC		.TEXT	", MBC RTC Latch Port 0x70\r\n$"
 PLT_RPH		.TEXT	", RHYOPHYRE RTC Latch Port 0x84\r\n$"
 PLT_DUO		.TEXT	", DUODYNE RTC Latch Port 0x70\r\n$"
+PLT_STDZ180 .TEXT ", STD Z180 RTC Module latch port 0x84\r\n$"
 
 ;
 ; Generic FOR-NEXT loop algorithm
diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1
index f6aa0a4e..e7ef3e63 100644
--- a/Source/HBIOS/Build.ps1
+++ b/Source/HBIOS/Build.ps1
@@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
 #
 
 $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180"
 $PlatformListZ280 = "RCZ280"
 
 #
diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh
index bb6dd4ad..cd9c06b2 100755
--- a/Source/HBIOS/Build.sh
+++ b/Source/HBIOS/Build.sh
@@ -51,6 +51,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
+      ROM_PLATFORM="GMZ180"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi
 
diff --git a/Source/HBIOS/Config/GMZ180_std.asm b/Source/HBIOS/Config/GMZ180_std.asm
new file mode 100644
index 00000000..9cf083b7
--- /dev/null
+++ b/Source/HBIOS/Config/GMZ180_std.asm
@@ -0,0 +1,72 @@
+;
+;==================================================================================================
+;   STD Z180 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_GMZ180.asm"
+;
+CPUOSC	.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT	.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+LEDENABLE	.SET	FALSE		; ENABLE STATUS LED (SINGLE LED)
+LEDMODE	.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE	.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE	.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE	.SET	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
diff --git a/Source/HBIOS/cfg_gmz180.asm b/Source/HBIOS/cfg_gmz180.asm
new file mode 100644
index 00000000..ee5ecc24
--- /dev/null
+++ b/Source/HBIOS/cfg_gmz180.asm
@@ -0,0 +1,358 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR GENESIS MODULES STD BUS BASED Z180 VARIANTS 
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM	.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND	.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON	.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC	.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE	.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE	.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE	.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR	.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS	.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA	.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+Z180_BASE	      .EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	      .EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	      .EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	      .EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RTCIO		.EQU	$84		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE	.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE	.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE	.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	      .EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	      .EQU	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT      .EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	      .EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	      .EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL	.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE	.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT	.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC	.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE	.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.EQU	TRUE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	      .EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	      .EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG	.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT	.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_GIDE	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.EQU	$20   		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE   	; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE	.EQU	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE	.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE	.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE	.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT	.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$18		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT	.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE	.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT	.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE	.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT	.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE	.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	      .EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	      .EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	      .EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	      .EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index 308bcb87..f1a42802 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -157,7 +157,7 @@ PLT_DUO		.EQU	17		; DUODYNE Z80 SYSTEM
 PLT_HEATH	.EQU	18		; HEATHKIT H8 Z80 SYSTEM
 PLT_EPITX	.EQU	19		; Z180 MINI-ITX
 PLT_MON		.EQU	20		; MONSPUTER
-PLT_STDZ180	.EQU	21		; GENESIS Z180 SYSTEM
+PLT_GMZ180	.EQU	21		; GENESIS Z180 SYSTEM
 PLT_NABU	.EQU	22		; NABU PERSONAL COMPUTER
 PLT_FZ80	.EQU	23		; S100 FPGA Z80
 ;
@@ -377,7 +377,6 @@ VDADEV_TMS	.EQU	$03		; N8 ONBOARD VDA SUBSYSTEM - TMS 9918
 VDADEV_VGA	.EQU	$04		; ECB VGA3 - HITACHI HD6445
 VDADEV_VRC	.EQU	$05		; VGARC
 VDADEV_EF	.EQU	$06		; EF9345
-VDADEV_FV	.EQU	$07		; S100 FPGA VGA
 ;
 ; SOUND DEVICE IDS
 ;
diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm
index 7abb8316..0730636d 100644
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@@ -18,6 +18,7 @@
 ;	MK4	$80	N/A	N/A
 ;	RC	$10	N/A	N/A
 ;	SMB	$E0	N/A	N/A
+;     GIDE        $20         $20         $28  - Genesis IDE controller - Note Read Hi Low - Write - Low High   
 ;
 ;	+-----------------------------------------------------------------------+
 ;	| CONTROL BLOCK REGISTERS						|
@@ -224,6 +225,9 @@ IDE_DEV0M:	; DEVICE 0, MASTER
   #IF (IDE0MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE0MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE0MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -259,6 +263,9 @@ IDE_DEV0S:	; DEVICE 0, SLAVE
   #IF (IDE0MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE0MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE0MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -297,6 +304,9 @@ IDE_DEV1M:	; DEVICE 1, MASTER
   #IF (IDE1MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE1MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE1MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -332,6 +342,9 @@ IDE_DEV1S:	; DEVICE 1, SLAVE
   #IF (IDE1MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE1MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE1MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -370,6 +383,9 @@ IDE_DEV2M:	; DEVICE 2, MASTER
   #IF (IDE2MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE2MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE2MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -405,6 +421,9 @@ IDE_DEV2S:	; DEVICE 2, SLAVE
   #IF (IDE2MODE == IDEMODE_DIDE)
 	DEVECHO	"DIDE"
   #ENDIF
+  #IF (IDE2MODE == IDEMODE_GIDE)
+	DEVECHO	"GIDE"
+  #ENDIF
   #IF (IDE2MODE == IDEMODE_MK4)
 	DEVECHO	"MK4"
   #ENDIF
@@ -491,6 +510,9 @@ IDE_INIT2:
 	LD	DE,IDE_STR_MODE_RC	; MODE LABEL
 	CP	IDEMODE_RC		; TEST FOR MODE
 	JR	Z,IDE_INIT2A		; IF SO, DISPLAY IT
+    LD	DE,IDE_STR_MODE_GIDE	; MODE LABEL
+	CP	IDEMODE_GIDE		; TEST FOR MODE
+	JR	Z,IDE_INIT2A		; IF SO, DISPLAY IT
 	JR	IDE_INIT4		; NO MODE?  BYPASS ENTRY
 IDE_INIT2A:
 	CALL	WRITESTR		; DISPLAY MODE
@@ -920,13 +942,13 @@ IDE_PKT_RDSEC:
 #ENDIF
 	; SETUP LBA
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,IDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,IDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -989,13 +1011,13 @@ IDE_PKT_WRSEC:
 #ENDIF
 	; SETUP LBA
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,IDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,IDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -1021,13 +1043,13 @@ IDE_PKT_WRSEC:
 ;
 IDE_SETADDR:
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,IDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 	; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER
 	; IDE_REG_LBA3 HAS ALREADY BEEN SET
 	; HSTLBA2-0 --> IDE_REG_LBA2-0
@@ -1253,10 +1275,17 @@ IDE_GET16:
 	RET
 ;
 IDE_GET16A:
-	LD	C,D			; PORT FOR LSB
+#IF (IDE0MODE == IDEMODE_GIDE)    ; GENESIS BOARD IS REVERSED
+	LD	C,E			; PORT FOR MSB
+	INI				; GET IT, SAVE IT, AND DEC B
+      LD	C,D			; PORT FOR LSB
+	INI				; GET IT, SAVE IT, AND DEC B
+#ELSE
+      LD	C,D			; PORT FOR LSB
 	INI				; GET IT, SAVE IT, AND DEC B
 	LD	C,E			; PORT FOR MSB
 	INI				; GET IT, SAVE IT, AND DEC B
+#ENDIF
 	DEC	A
 	JR	NZ,IDE_GET16A		; LOOP TILL COUNTER EXHAUSTED
 	RET
@@ -1318,11 +1347,18 @@ IDE_PUT16:
 	RET
 ;
 IDE_PUT16A:
+#IF (IDE0MODE == IDEMODE_GIDE)    ; GENESIS BOARD IS REVERSED
+	LD	C,E			; PORT FOR MSB
+	OUTI				; PUT IT AND DEC B
+	LD	C,D			; PORT FOR LSB
+	OUTI				; PUT IT AND DEC B
+#ELSE
 	LD	C,D			; PORT FOR LSB
 	OUTI				; PUT IT AND DEC B
 	LD	C,E			; PORT FOR MSB
 	OUTI				; PUT IT AND DEC B
 	DEC	A
+#ENDIF
 	JR	NZ,IDE_PUT16A		; LOOP TILL COUNTER EXHAUSTED
 	RET
 ;
@@ -1990,6 +2026,17 @@ IDE_OUT:
 	EX	(SP),HL			; GET PARM POINTER
 	PUSH	BC
 	PUSH	AF
+      
+#IF (IDE0MODE == IDEMODE_GIDE)    ; SET TOP BYTE TO 0 FOR GENESIS BOARD 
+
+	LD	A,(HL)
+	LD	C,(IY+IDE_DATAHI)
+	ADD	A,C
+	LD	C,A
+	LD    A,0
+	OUT	(C),A
+
+#ENDIF
 	LD	A,(HL)
 	INC	HL
 	LD	C,(IY+IDE_IOBASE)
@@ -2000,6 +2047,7 @@ IDE_OUT:
 	POP	BC
 	EX	(SP),HL			; RESTORE STACK
 	RET
+
 ;
 ;=============================================================================
 ; ERROR HANDLING AND DIAGNOSTICS
@@ -2189,6 +2237,7 @@ IDE_STR_MODE_DIO	.TEXT	"DIO$"
 IDE_STR_MODE_DIDE	.TEXT	"DIDE$"
 IDE_STR_MODE_MK4	.TEXT	"MK4$"
 IDE_STR_MODE_RC		.TEXT	"RC$"
+IDE_STR_MODE_GIDE  .TEXT "GIDE$"
 ;
 IDE_STR_TYPEATA		.TEXT	" ATA$"
 IDE_STR_TYPEATAPI	.TEXT	" ATAPI$"
diff --git a/Source/HBIOS/imm.asm b/Source/HBIOS/imm.asm
index 9ab0940b..237c6ed4 100644
--- a/Source/HBIOS/imm.asm
+++ b/Source/HBIOS/imm.asm
@@ -343,13 +343,13 @@ IMM_IO:
 ;
 	LD	(IMM_DSKBUF),HL		; SAVE DISK BUFFER ADDRESS
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,IMM_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 ;
 	; SETUP LBA
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
diff --git a/Source/HBIOS/md.asm b/Source/HBIOS/md.asm
index 5eba934a..b7d34401 100644
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@@ -64,6 +64,8 @@ MD_DEVCNT	.EQU	($ - MD_CFGTBL) / MD_CFGSIZ
 ;
 ;
 ;
+
+
 MD_INIT:
 #IF (MDFFENABLE)
 	CALL	MD_FINIT		; PROBE FLASH CAPABILITY
@@ -301,13 +303,13 @@ MD_RW:
 MD_RW1:
 	PUSH	BC			; SAVE COUNTERS
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,MD_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 ;
 	LD	HL,(MD_RWFNADR)		; GET PENDING IO FUNCTION ADDRESS
 #IF (MDFFENABLE)
diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm
index 28a3bb99..f7d7c6c7 100644
--- a/Source/HBIOS/ppide.asm
+++ b/Source/HBIOS/ppide.asm
@@ -830,13 +830,13 @@ PPIDE_PKT_RDSEC:
 #ENDIF
 	; SETUP LBA
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,PPIDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,PPIDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -899,13 +899,13 @@ PPIDE_PKT_WRSEC:
 #ENDIF
 	; SETUP LBA
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,PPIDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 ;
 	; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN
 	LD	HL,PPIDE_PKTCMD_RW10+3	; START OF LBA FIELD IN CDB (MSB)
@@ -931,13 +931,13 @@ PPIDE_PKT_WRSEC:
 ;
 PPIDE_SETADDR:
 ;
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	LD	A,PPIDE_LBA
 	CALL	LDHLIYA
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 	; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER
 	; IDE_REG_LBA3 HAS ALREADY BEEN SET
 	; HSTLBA2-0 --> IDE_REG_LBA2-0
diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm
index b00d969d..5e3f9d95 100644
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -125,8 +125,8 @@ SD_OPRREG	.EQU	RTCIO		; USES RTC LATCHES FOR OPERATION
 SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_OPRMSK	.EQU	%10000111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
 SD_INPREG	.EQU	RTCIO		; INPUT REGISTER IS RTC
-SD_CS0		.EQU	%00000100	; RTC:2 IS SELECT
-SD_CLK		.EQU	%00000010	; RTC:1 IS CLOCK
+SD_CS0	.EQU	%00000100	; RTC:2 IS SELECT
+SD_CLK	.EQU	%00000010	; RTC:1 IS CLOCK
 SD_DI		.EQU	%00000001	; RTC:0 IS DATA IN (CARD <- CPU)
 SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
@@ -235,14 +235,28 @@ SD_DEVMAX	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTCIO		; USES RTC LATCHES FOR OPERATION
 SD_OPRDEF	.EQU	%00001100	; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
 SD_OPRMSK	.EQU	%00001100	; MASK FOR BITS WE OWN IN RTC LATCH PORT
-SD_CS0		.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
-SD_CS1		.EQU	%00001000	; RTC:3 IS SELECT FOR SECONDARY SPI CARD
-SD_CNTR		.EQU	Z180_CNTR
-SD_TRDR		.EQU	Z180_TRDR
+SD_CS0	.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
+SD_CS1	.EQU	%00001000	; RTC:3 IS SELECT FOR SECONDARY SPI CARD
+SD_CNTR	.EQU	Z180_CNTR
+SD_TRDR	.EQU	Z180_TRDR
 SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
 SD_INVCS	.EQU	TRUE		; INVERT CS
 		DEVECHO	"SC"
+RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
+#ENDIF
 ;
+#IF (SDMODE == SDMODE_GM)	; GM
+SD_DEVMAX	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRREG	.EQU	RTCIO		; USES RTC LATCHES FOR OPERATION
+SD_OPRDEF	.EQU	%00000100	; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
+SD_OPRMSK	.EQU	%00000100	; MASK FOR BITS WE OWN IN RTC LATCH PORT
+SD_CS0	.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
+SD_CS1	.EQU	%00000000	; RTC:3 IS SELECT FOR SECONDARY SPI CARD
+SD_CNTR	.EQU	Z180_CNTR
+SD_TRDR	.EQU	Z180_TRDR
+SD_IOBASE	.EQU	SD_OPRREG	; IOBASE
+SD_INVCS	.EQU	TRUE		; INVERT CS
+		DEVECHO	"GM"
 RTCDEF		.SET	RTCDEF | SD_OPRDEF	; SET DEFAULT IN HBIOS MAINLINE
 #ENDIF
 ;
@@ -608,7 +622,7 @@ SD_INIT:
 	CALL	PRTHEXBYTE
 #ENDIF
 ;
-#IF (SDMODE == SDMODE_SC)
+#IF  ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 	PRTS(" MODE=SC$")
   #IF (SDCSIOFAST)
 	PRTS(" FAST$")
@@ -1132,7 +1146,7 @@ SD_INITCARD1:
 	POP	BC			; RESTORE LOOP CONTROL
 	DJNZ	SD_INITCARD1		; LOOP AS NEEDED
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM) | (SDMODE == SDMODE_EPITX))
 	; MAKE SURE CSIO IS DONE SENDING DATA
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 	CALL	DLY32			; WAIT A BIT MORE FOR FINAL BIT
@@ -1312,7 +1326,7 @@ SD_INITCARD5:
 
 ; HIGH SPEED CSIO OPERATION IS NOW SET AT THE START OF SD_IO
 ;
-;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 ;	; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION
 ;	; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED
 ;	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -1497,11 +1511,11 @@ SD_SETADDR:
 	PUSH	AF			; SAVE IT
 	LD	A,SD_LBA		; OFFSET OF LBA VALUE
 	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
-;;;#IF (DSKYENABLE)
-;;;  #IF (DSKYDSKACT)
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
 	CALL	HB_DSKACT		; SHOW ACTIVITY
-;;;  #ENDIF
-;;;#ENDIF
+  #ENDIF
+#ENDIF
 	CALL	LD32			; LOAD IT TO DE:HL, AF IS TRASHED
 	POP	AF			; GET CARD TYPE BACK
 	CP	SD_TYPESDHC		; IS IT V2 OR BETTER?
@@ -1874,7 +1888,7 @@ SD_DONE:
 	PUSH	AF
 	LD	A,$FF
 	CALL	SD_PUT
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; MAKE SURE CSIO IS DONE SENDING DATA
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 	CALL	DLY32			; WAIT A BIT MORE FOR FINAL BIT
@@ -1898,14 +1912,14 @@ SD_SETUP:
 	OUT	(SD_PPIX),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; CSIO SETUP FOR Z180 CSIO
 ;	LD	A,2			; DIV 80, 225KHZ @ 18MHZ CLK
 	LD	A,6			; DIV 1280, 14KHZ @ 18MHZ CLK
 	OUT0	(SD_CNTR),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 	LD	A,(HB_RTCVAL)
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
@@ -2004,11 +2018,11 @@ SD_CHKWP:
 ;
 SD_SELECT:
 ;	; FINISH SENDING BEFORE ASSERTING CS!
-;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 ;	CALL	SD_WAITTX
 ;#ENDIF
 ;
-#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80))
+#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM))
 	LD	A,(IY+SD_DEV)		; GET CURRENT DEVICE
 	OR	A			; SET FLAGS
 	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
@@ -2038,9 +2052,9 @@ SD_SELECT1:
 ;
 SD_SELECT2:
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 #IF (SD_INVCS)
-  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -2049,7 +2063,7 @@ SD_SELECT2:
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
 ;;
-;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
+;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
 ;	CALL	DLY32			; DELAY FOR FINAL BIT
 ;#ENDIF
 ;
@@ -2058,7 +2072,7 @@ SD_SELECT2:
 ; DESELECT CARD
 ;
 SD_DESELECT:
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; DON'T REMOVE CS UNTIL WE ARE DONE SENDING!
 	CALL	SD_WAITTX		; WAIT FOR TE TO CLEAR
 ;
@@ -2077,7 +2091,7 @@ SD_DESELECT:
 #ENDIF
 ;
 	LD	A,(SD_OPRVAL)
-#IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1))
+#IF (((SDMODE == SDMODE_SC) | (SDMODE_MT) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
 	AND	~(SD_CS0 | SD_CS1)
 #ELSE
 #IF (SDMODE == SDMODE_EPITX)
@@ -2088,7 +2102,7 @@ SD_DESELECT:
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
 #IF (SD_INVCS)
-  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
+  #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
 	XOR	SD_CS0
@@ -2098,7 +2112,7 @@ SD_DESELECT:
 	OUT	(SD_OPRREG),A
 	RET
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 ;
 ; CSIO WAIT FOR TRANSMIT READY (TX REGISTER EMPTY)
 ;
@@ -2140,7 +2154,7 @@ SD_PUT:
 	OUT	(SD_WRTR),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS, RESULT IN C
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	OUT0	(SD_TRDR),C		; PUT BYTE IN BUFFER
@@ -2227,7 +2241,7 @@ SD_GET:
 	IN	A,(SD_RDTR)
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	IN0	A,(SD_CNTR)		; GET CSIO STATUS
 	SET	5,A			; START RECEIVER
@@ -2331,7 +2345,7 @@ SD_GET1:
 ;
 SD_SPD_STD:
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; SET CSIO FOR DEFAULT OPERATION
 	PUSH	AF			; PRESERVE AF
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -2346,7 +2360,7 @@ SD_SPD_STD:
 ;
 SD_SPD_SLOW:
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; SET CSIO FOR DEFAULT OPERATION
 	PUSH	AF			; PRESERVE AF
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -2361,7 +2375,7 @@ SD_SPD_SLOW:
 ;
 SD_SPD_FAST:
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM))
 	; SET CSIO FOR HIGH SPEED OPERATION
 	PUSH	AF			; PRESERVE AF
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -2612,7 +2626,7 @@ SD_DSKBUF	.DW	0		; ADR OF ACTIVE DISK BUFFER
 ; MSB<-->LSB MIRROR BITS IN A, RESULT IN C
 ;
 MIRROR:
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) & SDCSIOFAST)
 					; FASTEST BUT USES MOST CODE SPACE
 	LD	BC,MIRTAB		; 256 BYTE MIRROR TABLE
 	ADD	A,C			; ADD OFFSET
@@ -2645,7 +2659,7 @@ MIRROR2:
 ;
 ; LOOKUP TABLE TO MIRROR BITS IN A BYTE
 ;
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) & SDCSIOFAST)
 
 MIRTAB	.DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H
 	.DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index dd1e7f21..5f68199c 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -22,7 +22,7 @@
 ; 18. HEATH	Les Bird's Heath Z80 Board
 ; 19. EPITX	Alan Cox' Mini-ITX System
 ; 20. MON	Jacques Pelletier's Monsputer
-; 21. STDZ180	Genesis Z180 System
+; 21. GMZ180      Doug Jacksons' Genesis Z180 System
 ; 22. NABU	NABU w/ Les Bird's RomWBW Option Board
 ; 23. FZ80	S100 Computers FPGA Z80
 ; 
@@ -194,6 +194,7 @@ IDEMODE_DIO	.EQU	1		; DISKIO V1
 IDEMODE_DIDE	.EQU	2		; DUAL IDE
 IDEMODE_MK4	.EQU	3		; MARK IV ONBOARD IDE (8 BIT ONLY)
 IDEMODE_RC	.EQU	4		; RCBUS CF MODULE (8 BIT ONLY)
+IDEMODE_GIDE      .EQU  5     ; GENESIS MODULES STD BUS IDE CONTROLLER
 ;
 ; PPIDE MODE SELECTIONS
 ;
@@ -223,6 +224,7 @@ SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
 SDMODE_Z80R	.EQU	12		; Z80 Retro
 SDMODE_EPITX	.EQU	13		; Mini ITX Z180
 SDMODE_FZ80	.EQU	14		; S100 FPGA Z80
+SDMODE_GM   .EQU  15          ; Genesis SD Driver
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;
@@ -321,7 +323,6 @@ DMAMODE_VDG	.EQU	7		; VELESOFT DATAGEAR
 KBDMODE_NONE	.EQU	0
 KBDMODE_PS2	.EQU	1		; PS/2 KEYBOARD CONTROLLER
 KBDMODE_VRC	.EQU	2		; VGARC KEYBOARD CONTROLLER
-KBDMODE_FV	.EQU	3		; FPGA VGA KEYBOARD CONTROLLER
 ;
 ; SERIAL DEVICE CONFIGURATION CONSTANTS
 ;
@@ -493,7 +494,6 @@ KBDENABLE	.EQU	FALSE		; PS/2 KEYBOARD DRIVER
 PPKENABLE	.EQU	FALSE		; PPK KEYBOARD DRIVER
 MKYENABLE	.EQU	FALSE		; MSX KEYBOARD DRIVER
 NABUKBENABLE	.EQU	FALSE		; NABU KEYBOARD DRIVER
-FKBDENABLE	.EQU	FALSE		; FPGA KEYBOARD DRIVER
 ;
 ; VIDEO MODES
 ;
diff --git a/Source/HDIAG/hdsk.asm b/Source/HDIAG/hdsk.asm
new file mode 100644
index 00000000..6dfc426f
--- /dev/null
+++ b/Source/HDIAG/hdsk.asm
@@ -0,0 +1,449 @@
+;
+;==================================================================================================
+;   HDSK DISK DRIVER
+;==================================================================================================
+;
+; IO PORT ADDRESSES
+;
+HDSK_IO		.EQU	$FD
+;
+HDSK_CMDNONE	.EQU	0
+HDSK_CMDRESET	.EQU	1
+HDSK_CMDREAD	.EQU	2
+HDSK_CMDWRITE	.EQU	3
+HDSK_CMDPARAM	.EQU	4
+;
+; HDSK DEVICE CONFIGURATION
+;
+HDSK_DEVCNT	.EQU	2		; NUMBER OF HDSK DEVICES SUPPORTED
+HDSK_CFGSIZ	.EQU	6		; SIZE OF CFG TBL ENTRIES
+;
+HDSK_DEV	.EQU	0		; OFFSET OF DEVICE NUMBER (BYTE)
+HDSK_STAT	.EQU	1		; OFFSET OF STATUS (BYTE)
+HDSK_LBA	.EQU	2		; OFFSET OF LBA (DWORD)
+;
+	DEVECHO	"HDSK: IO="
+	DEVECHO	HDSK_IO
+	DEVECHO	", DEVICE COUNT="
+	DEVECHO	HDSK_DEVCNT
+	DEVECHO	"\n"
+;
+HDSK_CFGTBL:
+	; DEVICE 0
+	.DB	0			; DRIVER DEVICE NUMBER
+	.DB	0			; DEVICE STATUS
+	.DW	0,0			; CURRENT LBA
+#IF (HDSK_DEVCNT >= 2)
+	; DEVICE 1
+	.DB	1			; DEVICE NUMBER
+	.DB	0			; DEVICE STATUS
+	.DW	0,0			; CURRENT LBA
+#ENDIF
+;
+#IF ($ - HDSK_CFGTBL) != (HDSK_DEVCNT * HDSK_CFGSIZ)
+	.ECHO	"*** INVALID HDSK CONFIG TABLE ***\n"
+#ENDIF
+;
+	.DB	$FF			; END MARKER
+;
+; STATUS
+;
+HDSK_STOK	.EQU	0		; OK
+HDSK_STNOTRDY	.EQU	-1		; NOT READY
+;
+;
+;
+HDSK_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("HDSK:$")
+	PRTS(" DEVICES=$")
+	LD	A,HDSK_DEVCNT
+	CALL	PRTDECB
+;
+; SETUP THE DISPATCH TABLE ENTRIES
+;
+	XOR	A			; ZERO ACCUM
+	LD	(HDSK_CURDEV),A		; INIT CURRENT DEVICE NUM
+	LD	IY,HDSK_CFGTBL		; START OF DEV CFG TABLE
+HDSK_INIT0:
+	CALL	HDSK_PROBE		; HARDWARE PROBE
+	JR	NZ,HDSK_INIT1		; SKIP DEVICE IF NOT PRESENT
+	LD	BC,HDSK_FNTBL		; BC := DRIVER FUNC TABLE ADDRESS
+	PUSH	IY			; CFG ENTRY POINTER
+	POP	DE			; ... TO DE
+	CALL	DIO_ADDENT		; ADD ENTRY TO GLOBAL DISK TABLE
+	CALL	HDSK_INITDEV		; PERFORM DEVICE INITIALIZATION
+HDSK_INIT1:
+	LD	BC,HDSK_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,BC			; BUMP IY TO NEXT ENTRY
+	LD	HL,HDSK_CURDEV		; POINT TO CURRENT DEVICE
+	INC	(HL)			; AND INCREMENT IT
+	LD	A,(IY)			; GET FIRST BYTE OF ENTRY
+	INC	A			; TEST FOR END OF TABLE ($FF)
+	JR	NZ,HDSK_INIT0		; IF NOT, LOOP
+;
+	XOR	A			; INIT SUCCEEDED
+	RET				; RETURN
+;
+; PROBE FOR DEVICE EXISTENCE
+;
+HDSK_PROBE:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
+;
+; INITIALIZE DEVICE
+;
+HDSK_INITDEV:
+	LD	(IY+HDSK_STAT),HDSK_STNOTRDY	; STATUS := NOT READY
+	XOR	A			; CLEAR ACCUM
+	LD	(IY+HDSK_LBA+0),A	; ZERO LBA
+	LD	(IY+HDSK_LBA+1),A	; ...
+	LD	(IY+HDSK_LBA+2),A	; ...
+	LD	(IY+HDSK_LBA+3),A	; ...
+	XOR	A			; SIGNAL SUCCESS (REDUNDANT)
+	RET				; AND DONE
+;
+; DRIVER FUNCTION TABLE
+;
+HDSK_FNTBL:
+	.DW	HDSK_STATUS
+	.DW	HDSK_RESET
+	.DW	HDSK_SEEK
+	.DW	HDSK_READ
+	.DW	HDSK_WRITE
+	.DW	HDSK_VERIFY
+	.DW	HDSK_FORMAT
+	.DW	HDSK_DEVICE
+	.DW	HDSK_MEDIA
+	.DW	HDSK_DEFMED
+	.DW	HDSK_CAP
+	.DW	HDSK_GEOM
+#IF (($ - HDSK_FNTBL) != (DIO_FNCNT * 2))
+	.ECHO	"*** INVALID HDSK FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+HDSK_VERIFY:
+HDSK_FORMAT:
+HDSK_DEFMED:
+	SYSCHKERR(ERR_NOTIMPL)			; INVALID SUB-FUNCTION
+	RET
+;
+;
+;
+HDSK_STATUS:
+	LD	A,(IY+HDSK_STAT)	; LOAD STATUS
+	OR	A			; SET FLAGS
+	RET
+;
+;
+;
+HDSK_RESET:
+	JP	HDSK_DSKRESET
+;
+; GET DISK CAPACITY
+;   RETURN DE:HL=BLOCK COUNT, BC=BLOCK SIZE
+;   ASSUME 1GB MEDIA SIZE, SO 1GB / 512B
+;   IS $200000 SECTORS
+;
+HDSK_CAP:
+	LD	DE,$20			; BLOCK COUNT MSW
+	LD	HL,0			; BLOCK COUNT LSW
+	LD	BC,512			; 512 BYTE SECTOR
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+HDSK_GEOM:
+	; FOR LBA, WE SIMULATE CHS ACCESS USING 16 HEADS AND 16 SECTORS
+	; RETURN HS:CC -> DE:HL, SET HIGH BIT OF D TO INDICATE LBA CAPABLE
+	CALL	HDSK_CAP		; GET TOTAL BLOCKS IN DE:HL, BLOCK SIZE TO BC
+	LD	L,H			; DIVIDE BY 256 FOR # TRACKS
+	LD	H,E			; ... HIGH BYTE DISCARDED, RESULT IN HL
+	LD	D,$80 | 16		; HEADS / CYL = 16, SET LBA BIT
+	LD	E,16			; SECTORS / TRACK = 16
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+HDSK_DEVICE:
+	LD	D,DIODEV_HDSK		; D := DEVICE TYPE
+	LD	E,(IY+HDSK_DEV)		; E := PHYSICAL DEVICE NUMBER
+	LD	C,%00110000		; C := ATTRIBUTES, NON-REMOVABLE HARD DISK
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,HDSK_IO		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+HDSK_MEDIA:
+	LD	E,MID_HD		; HARD DISK MEDIA
+	LD	D,0			; D:0=0 MEANS NO MEDIA CHANGE
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+;
+HDSK_SEEK:
+	BIT	7,D			; CHECK FOR LBA FLAG
+	CALL	Z,HB_CHS2LBA		; CLEAR MEANS CHS, CONVERT TO LBA
+	RES	7,D			; CLEAR FLAG REGARDLESS (DOES NO HARM IF ALREADY LBA)
+	LD	(IY+HDSK_LBA+0),L	; SAVE NEW LBA
+	LD	(IY+HDSK_LBA+1),H	; ...
+	LD	(IY+HDSK_LBA+2),E	; ...
+	LD	(IY+HDSK_LBA+3),D	; ...
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+;
+;
+HDSK_READ:
+	CALL	HB_DSKREAD		; HOOK HBIOS DISK READ SUPERVISOR
+	LD	A,HDSK_CMDREAD
+	JR	HDSK_RW
+;
+;
+;
+HDSK_WRITE:
+	CALL	HB_DSKWRITE		; HOOK HBIOS DISK WRITE SUPERVISOR
+	LD	A,HDSK_CMDWRITE
+	JR	HDSK_RW
+;
+;
+;
+HDSK_RW:
+	LD	(HDSK_CMD),A		; SET COMMAND BYTE
+	LD	(HDSK_DMA),HL		; SAVE INITIAL DMA
+	LD	A,E			; SECTOR COUNT TO A
+	OR	A			; SET FLAGS
+	RET	Z			; ZERO SECTOR I/O, RETURN W/ E=0 & A=0
+	LD	B,A			; INIT SECTOR DOWNCOUNTER
+	LD	C,0			; INIT SECTOR READ/WRITE COUNT
+	LD	A,(IY+HDSK_DEV)		; GET DEVICE NUMBER
+	LD	(HDSK_DRV),A		; ... AND SET FIELD IN HDSK PARM BLOCK
+
+	; RESET HDSK INTERFACE IF NEEDED
+	LD	A,(IY+HDSK_STAT)	; GET CURRENT STATUS
+	OR	A			; SET FLAGS
+	PUSH	BC			; SAVE COUNTERS
+	CALL	NZ,HDSK_DSKRESET	; RESET IF NOT READY
+	POP	BC			; RESTORE COUNTERS
+	JR	NZ,HDSK_RW6		; ABORT ON FAILURE
+
+HDSK_RW0:
+	PUSH	BC			; SAVE COUNTERS
+	XOR	A			; A = 0
+	LD	(HDSK_RC),A		; CLEAR RETURN CODE
+;
+#IF (DSKYENABLE)
+  #IF (DSKYDSKACT)
+	LD	A,HDSK_LBA
+	CALL	LDHLIYA
+	CALL	HB_DSKACT		; SHOW ACTIVITY
+  #ENDIF
+#ENDIF
+;
+	; CONVERT LBA HHHH:LLLL (4 BYTES)
+	; TO HDSK TRACK/SECTOR TTTT:SS (3 BYTES)
+	; SAVING TO HDSK PARM BLOCK
+	; (IY+HDSK_LBA+0) ==> (HDSK_SEC)
+	LD	A,(IY+HDSK_LBA+0)
+	LD	(HDSK_SEC),A
+	; (IY+HDSK_LBA+1) ==> (HDSK_TRK+0)
+	LD	A,(IY+HDSK_LBA+1)
+	LD	(HDSK_TRK+0),A
+	; (IY+HDSK_LBA+2) ==> (HDSK_TRK+1)
+	LD	A,(IY+HDSK_LBA+2)
+	LD	(HDSK_TRK+1),A
+
+	; EXECUTE COMMAND
+	LD	B,7			; SIZE OF PARAMETER BLOCK
+	LD	HL,HDSK_PARMBLK		; ADDRESS OF PARAMETER BLOCK
+	LD	C,$FD			; HDSK CMD PORT
+	OTIR				; SEND IT
+
+	; GET RESULT
+	IN	A,(C)			; GET RESULT CODE
+	LD	(HDSK_RC),A		; SAVE IT
+	OR	A			; SET FLAGS
+
+#IF (HDSKTRACE > 0)
+	PUSH	AF			; SAVE RETURN CODE
+#IF (HDSKTRACE == 1)
+	CALL	NZ,HDSK_PRT		; DIAGNOSE ERRORS ONLY
+#ENDIF
+#IF (HDSKTRACE >= 2)
+	CALL	HDSK_PRT		; DISPLAY ALL READ/WRITE RESULTS
+#ENDIF
+	POP	AF			; RESTORE RETURN CODE
+#ENDIF
+
+	JR	NZ,HDSK_RW5		; BAIL OUT ON ERROR
+
+	; INCREMENT LBA
+	LD	A,HDSK_LBA		; LBA OFFSET IN CFG ENTRY
+	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
+	CALL	INC32HL			; INCREMENT THE VALUE
+
+	; INCREMENT DMA
+	LD	HL,HDSK_DMA+1		; POINT TO MSB OF DMA
+	INC	(HL)			; BUMP DMA BY
+	INC	(HL)			; ... 512 BYTES
+
+	XOR	A			; A := 0 SIGNALS SUCCESS
+
+HDSK_RW5:
+	POP	BC			; RECOVER COUNTERS
+	JR	NZ,HDSK_RW6		; IF ERROR, GET OUT
+
+	INC	C			; RECORD SECTOR COMPLETED
+	DJNZ	HDSK_RW0		; LOOP AS NEEDED
+
+HDSK_RW6:
+	; RETURN WITH SECTORS READ IN E AND UPDATED DMA ADDRESS IN HL
+	LD	E,C			; SECTOR READ COUNT TO E
+	LD	HL,(HDSK_DMA)		; CURRENT DMA TO HL
+	OR	A			; SET FLAGS BASED ON RETURN CODE
+	RET	Z			; RETURN IF SUCCESS
+	LD	A,ERR_IO		; SIGNAL IO ERROR
+	OR	A			; SET FLAGS
+	RET				; AND DONE
+;
+;
+;
+HDSK_DSKRESET:
+;
+#IF (HDSKTRACE >= 2)
+	CALL	NEWLINE
+	LD	DE,HDSKSTR_PREFIX
+	CALL	WRITESTR
+	CALL	PC_SPACE
+	LD	DE,HDSKSTR_RESET
+	CALL	WRITESTR
+#ENDIF
+;
+	LD	B,32
+	LD	A,HDSK_CMDRESET
+HDSK_DSKRESET1:
+	OUT	($FD),A
+	DJNZ	HDSK_DSKRESET1
+
+	XOR	A			; STATUS = OK
+	LD	(IY+HDSK_STAT),A	; SAVE IT
+
+	RET
+;
+;
+;
+HDSK_PRT:
+	CALL	NEWLINE
+
+	LD	DE,HDSKSTR_PREFIX
+	CALL	WRITESTR
+
+	CALL	PC_SPACE
+	LD	DE,HDSKSTR_CMD
+	CALL	WRITESTR
+	LD	A,(HDSK_CMD)
+	CALL	PRTHEXBYTE
+
+	CALL	PC_SPACE
+	CALL	PC_LBKT
+	LD	A,(HDSK_CMD)
+	LD	DE,HDSKSTR_NONE
+	CP	HDSK_CMDNONE
+	JP	Z,HDSK_PRTCMD
+	LD	DE,HDSKSTR_RESET
+	CP	HDSK_CMDRESET
+	JP	Z,HDSK_PRTCMD
+	LD	DE,HDSKSTR_READ
+	CP	HDSK_CMDREAD
+	JP	Z,HDSK_PRTCMD
+	LD	DE,HDSKSTR_WRITE
+	CP	HDSK_CMDWRITE
+	JP	Z,HDSK_PRTCMD
+	LD	DE,HDSKSTR_PARAM
+	CP	HDSK_CMDPARAM
+	JP	Z,HDSK_PRTCMD
+	LD	DE,HDSKSTR_UNKCMD
+HDSK_PRTCMD:
+	CALL	WRITESTR
+	CALL	PC_RBKT
+
+	LD	A,(HDSK_CMD)
+	CP	HDSK_CMDREAD
+	JR	Z,HDSK_PRTRW
+	CP	HDSK_CMDWRITE
+	JR	Z,HDSK_PRTRW
+	RET
+
+HDSK_PRTRW:
+	CALL	PC_SPACE
+	LD	A,(HDSK_DRV)
+	CALL	PRTHEXBYTE
+	CALL	PC_SPACE
+	LD	BC,(HDSK_TRK)
+	CALL	PRTHEXWORD
+	CALL	PC_SPACE
+	LD	A,(HDSK_SEC)
+	CALL	PRTHEXBYTE
+	CALL	PC_SPACE
+	LD	BC,(HDSK_DMA)
+	CALL	PRTHEXWORD
+
+	CALL	PC_SPACE
+	LD	DE,HDSKSTR_ARROW
+	CALL	WRITESTR
+
+	CALL	PC_SPACE
+	LD	DE,HDSKSTR_RC
+	CALL	WRITESTR
+	LD	A,(HDSK_RC)
+	CALL	PRTHEXBYTE
+
+	CALL	PC_SPACE
+	CALL	PC_LBKT
+	LD	A,(HDSK_RC)
+	LD	DE,HDSKSTR_STOK
+	CP	HDSK_STOK
+	JP	Z,HDSK_PRTRC
+	LD	DE,HDSKSTR_STUNK
+
+HDSK_PRTRC:
+	CALL	WRITESTR
+	CALL	PC_RBKT
+
+	RET
+;
+;
+;
+HDSKSTR_PREFIX	.TEXT	"HDSK:$"
+HDSKSTR_CMD	.TEXT	"CMD=$"
+HDSKSTR_RC	.TEXT	"RC=$"
+HDSKSTR_ARROW	.TEXT	"-->$"
+HDSKSTR_NONE	.TEXT	"NONE$"
+HDSKSTR_RESET	.TEXT	"RESET$"
+HDSKSTR_READ	.TEXT	"READ$"
+HDSKSTR_WRITE	.TEXT	"WRITE$"
+HDSKSTR_PARAM	.TEXT	"PARAM$"
+HDSKSTR_UNKCMD	.TEXT	"UNKCMD$"
+HDSKSTR_STOK	.TEXT	"OK$"
+HDSKSTR_STUNK	.TEXT	"UNKNOWN ERROR$"
+;
+;==================================================================================================
+;   HDSK DISK DRIVER - DATA
+;==================================================================================================
+;
+HDSK_RC		.DB	0		; CURRENT RETURN CODE
+HDSK_CURDEV	.DB	0		; CURRENT DEVICE NUMBER
+;
+HDSK_PARMBLK:
+HDSK_CMD	.DB	0		; COMMAND (HDSK_READ, HDSK_WRITE, ...)
+HDSK_DRV	.DB	0		; 0..7, HDSK DRIVE NUMBER
+HDSK_SEC	.DB	0		; 0..255 SECTOR
+HDSK_TRK	.DW	0		; 0..2047 TRACK
+HDSK_DMA	.DW	0		; ADDRESS FOR SECTOR DATA EXCHANGE