From 48ab169c60997d28b0a8c73164a2a28e6a5185ee Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Wed, 3 Jul 2024 10:39:19 -0700 Subject: [PATCH] S100 FPGA Z80 SD Card Support WIP - Not yet working --- Doc/ChangeLog.txt | 1 + Source/HBIOS/Config/FZ80_std.asm | 4 + Source/HBIOS/cfg_duo.asm | 2 +- Source/HBIOS/cfg_dyno.asm | 2 +- Source/HBIOS/cfg_epitx.asm | 2 +- Source/HBIOS/cfg_fz80.asm | 4 +- Source/HBIOS/cfg_heath.asm | 2 +- Source/HBIOS/cfg_master.asm | 2 +- Source/HBIOS/cfg_mbc.asm | 2 +- Source/HBIOS/cfg_mk4.asm | 2 +- Source/HBIOS/cfg_mon.asm | 2 +- Source/HBIOS/cfg_n8.asm | 2 +- Source/HBIOS/cfg_nabu.asm | 2 +- Source/HBIOS/cfg_rcz180.asm | 2 +- Source/HBIOS/cfg_rcz280.asm | 2 +- Source/HBIOS/cfg_rcz80.asm | 2 +- Source/HBIOS/cfg_rph.asm | 2 +- Source/HBIOS/cfg_s100.asm | 2 +- Source/HBIOS/cfg_sbc.asm | 2 +- Source/HBIOS/cfg_scz180.asm | 2 +- Source/HBIOS/cfg_z80retro.asm | 2 +- Source/HBIOS/cfg_zeta.asm | 2 +- Source/HBIOS/cfg_zeta2.asm | 2 +- Source/HBIOS/sd.asm | 174 ++++++++++++++++++++++++------- Source/HBIOS/std.asm | 1 + Source/ver.inc | 2 +- Source/ver.lib | 2 +- 27 files changed, 167 insertions(+), 61 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index e139cdd5..a887c670 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -21,6 +21,7 @@ Version 3.5 - M?R: Update Timer app to display output in decimal - WBW: Preliminary support for S100 FPGA Z80 platform - WBW: Added simple serial (SSER) driver +- WBW: Added preliminary support for S100 FPGA Z80 SD Cards Version 3.4 ----------- diff --git a/Source/HBIOS/Config/FZ80_std.asm b/Source/HBIOS/Config/FZ80_std.asm index bc8c1fad..ee1f642c 100644 --- a/Source/HBIOS/Config/FZ80_std.asm +++ b/Source/HBIOS/Config/FZ80_std.asm @@ -28,3 +28,7 @@ ; CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +; +; SD CARD SUPPORT CURRENTLY BROKEN +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDTRACE .SET 3 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm index 6b99fc6b..ad670e3f 100644 --- a/Source/HBIOS/cfg_duo.asm +++ b/Source/HBIOS/cfg_duo.asm @@ -239,7 +239,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index 9199a435..0db376f0 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -254,7 +254,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_epitx.asm b/Source/HBIOS/cfg_epitx.asm index 4463d568..2190518c 100644 --- a/Source/HBIOS/cfg_epitx.asm +++ b/Source/HBIOS/cfg_epitx.asm @@ -256,7 +256,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|EPITX] +SDMODE .EQU SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $40 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 2 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_fz80.asm b/Source/HBIOS/cfg_fz80.asm index 6ff802f1..0a528da9 100644 --- a/Source/HBIOS/cfg_fz80.asm +++ b/Source/HBIOS/cfg_fz80.asm @@ -258,8 +258,8 @@ PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .EQU SDMODE_FZ80 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm index 368986ae..859943e8 100644 --- a/Source/HBIOS/cfg_heath.asm +++ b/Source/HBIOS/cfg_heath.asm @@ -259,7 +259,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 2c660aef..2f8d46e0 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -306,7 +306,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm index f8bbcebb..54428eb3 100644 --- a/Source/HBIOS/cfg_mbc.asm +++ b/Source/HBIOS/cfg_mbc.asm @@ -236,7 +236,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index a71b9e2e..d0d69027 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -245,7 +245,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_mon.asm b/Source/HBIOS/cfg_mon.asm index 8fd6616d..01f5c9d3 100644 --- a/Source/HBIOS/cfg_mon.asm +++ b/Source/HBIOS/cfg_mon.asm @@ -254,7 +254,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index 874b04d4..9e64f3e7 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -247,7 +247,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm index 6e53084d..5b8cd169 100644 --- a/Source/HBIOS/cfg_nabu.asm +++ b/Source/HBIOS/cfg_nabu.asm @@ -259,7 +259,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index f7c8a09a..e94f321f 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -260,7 +260,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm index fed30e1c..60f3a65c 100644 --- a/Source/HBIOS/cfg_rcz280.asm +++ b/Source/HBIOS/cfg_rcz280.asm @@ -264,7 +264,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index d61cfb90..196dba63 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -259,7 +259,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_rph.asm b/Source/HBIOS/cfg_rph.asm index 997764b1..98b29a0c 100644 --- a/Source/HBIOS/cfg_rph.asm +++ b/Source/HBIOS/cfg_rph.asm @@ -236,7 +236,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm index 699202bb..446d8271 100644 --- a/Source/HBIOS/cfg_s100.asm +++ b/Source/HBIOS/cfg_s100.asm @@ -254,7 +254,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index d70be45f..5efc5154 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -235,7 +235,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 61279038..426d17fc 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -254,7 +254,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm index 560bea43..1f67d4e9 100644 --- a/Source/HBIOS/cfg_z80retro.asm +++ b/Source/HBIOS/cfg_z80retro.asm @@ -210,7 +210,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index b713736b..5dd1293d 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -180,7 +180,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index 810a2927..bde847f9 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -191,7 +191,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index aa77ef6e..c15e4ca7 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -372,10 +372,10 @@ SD_CS0 .EQU %00000100 ; SELECT SD_DI .EQU %00000001 ; DATA IN (CARD <- CPU) MOSI SD_DO .EQU %00000001 ; DATA OUT (CARD -> CPU) MISO SD_CINIT .EQU FALSE ; INITIALIZE OUTPUT PORT -SD_INVCS .EQU FALSE ; INVERT CS +SD_INVCS .EQU TRUE ; INVERT CS DEVECHO "Z80R" #ENDIF - +; ; FOR NOW WE JUST HOOK UP ONE UNIT. THERE ARE EIGHT PORTS FOR DIFFERENT ; THINGS BUT THIS WILL GET US GOING #IF (SDMODE == SDMODE_EPITX) ; Z180 ITX - CSIO, 82C55 for CS @@ -389,6 +389,39 @@ SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS DEVECHO "EPITX" #ENDIF +; +; S100 FPGA Z80 SPI-BASED SD CARD +; +; BASE PORT: $6C +; BASE + 0: DATA IN/OUT +; BASE + 1: SPI CLOCK SPEED (0=LOW 4KHZ, 1=HIGH 10MHZ) +; BASE + 2: SELECT (W), STATUS (R) +; BASE + 3: START READ (IN OPCODE), START WRITE (OUT OPCODE), ANY VALUE +; +; STATUS BITS: +; 7: BUSY (1=BUSY) +; 0: PRIMARY DEVICE SELECT STATUS (1=SELECTED) +; 1: SECONDARY DEVICE SELECT STATUS (1=SELECTED) +; +; SELECT BITS (INVERTED!!!): +; 0: PRIMARY DEVICE, USE VALUE ~$01 +; 1: SECONDARY DEVICE, USE VALUE ~$02 +; +#IF (SDMODE == SDMODE_FZ80) ; S100 FPGA Z80 +SD_IOBASE .EQU $6C ; IOBASE +SD_DATA .EQU SD_IOBASE + 0 ; DATA IN/OUT PORT +SD_CLKSEL .EQU SD_IOBASE + 1 ; CLOCK SPEED SELECT PORT +SD_SELSTAT .EQU SD_IOBASE + 2 ; DEVICE SELECT PORT (W) / STATUS (R) +SD_ACTION .EQU SD_IOBASE + 3 ; INITIATE R/W ACTION VIA IN/OUT +; +SD_DEVMAX .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS) +SD_OPRREG .EQU SD_SELSTAT ; SELECT/STATUS PORT +SD_OPRDEF .EQU $FF ; QUIESCENT STATE +SD_CS0 .EQU %00000001 ; PRIMARY DEVICE SELECT BIT +SD_CS1 .EQU %00000010 ; SECONDARY DEVICE SELECT BIT +SD_INVCS .EQU TRUE ; INVERT CS + DEVECHO "FZ80" +#ENDIF ; DEVECHO ", IO=" DEVECHO SD_IOBASE @@ -640,6 +673,13 @@ SD_INIT: LD A,SD_TRDR CALL PRTHEXBYTE #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + PRTS(" MODE=FZ80$") + PRTS(" IO=0x$") + LD A,SD_IOBASE + CALL PRTHEXBYTE +#ENDIF ; CALL SD_PROBE ; CHECK FOR HARDWARE JR Z,SD_INIT00 ; CONTINUE IF PRESENT @@ -1083,6 +1123,11 @@ SD_INITCARD: #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) CALL SD_CSIO_DEF ; ENSURE CSIO AT DEFAULT SPEED #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + ;;; FORCE SLOW SPEED HERE? + ;;; CALL SD_SELECT? +#ENDIF ; ; WAKE UP THE CARD, KEEP DIN HI (ASSERTED) AND /CS HI (DEASSERTED) LD B,$10 ; MIN 74 CLOCKS REQUIRED, WE USE 128 ($10 * 8) @@ -1486,8 +1531,10 @@ SD_GOIDLE: ; SD_GOIDLE1: ; SEEMS TO HELP SOME CARDS? - ;CALL SD_SELECT ; ASSERT CS - ;CALL SD_DONE ; SEND 8 CLOCKS AND DEASSERT CS + ;;; DEBUG + CALL SD_SELECT ; ASSERT CS + CALL SD_DONE ; SEND 8 CLOCKS AND DEASSERT CS + ;;; DEBUG ; SMALL DELAY HERE HELPS SOME CARDS ;;LD DE,300 ; 16US * 300 = ~5MS @@ -1884,6 +1931,15 @@ SD_SETUP: LD (SD_OPRVAL),A OUT (SD_OPRREG),A #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + LD A,SD_OPRDEF ; DEFAULT SELECT VALUE + LD (SD_OPRVAL),A ; PUT IN SHADOW + OUT (SD_OPRREG),A ; WRITE TO PORT + XOR A ; LOW SPEED OPERATION + LD (SD_CLKSEL),A ; DO IT + CALL SD_DESELECT ; MAKE SURE CARD(S) ARE NOT SELECTED +#ENDIF ; XOR A RET @@ -1931,7 +1987,7 @@ SD_SELECT: ; CALL SD_WAITTX ;#ENDIF ; -#IF ((SDMODE == SDMODE_SC) | SDMODE == SDMODE_MT)) +#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80)) LD A,(IY+SD_DEV) ; GET CURRENT DEVICE OR A ; SET FLAGS LD A,(SD_OPRVAL) ; GET CURRENT OPRVAL BACK @@ -1949,21 +2005,21 @@ SD_SELECT1: OR SD_CS1 #ENDIF #ELSE -#IF (SDMODE == SDMODE_EPITX) + #IF (SDMODE == SDMODE_EPITX) LD A,(SD_OPRVAL) AND $F8 OR SD_CS0 ; WILL DO 1-7 LATER -#ELSE + #ELSE LD A,(SD_OPRVAL) ; GET CURRENT OPRVAL BACK OR SD_CS0 -#ENDIF + #ENDIF #ENDIF ; SD_SELECT2: ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS ;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC)) #IF (SD_INVCS) - #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1)) + #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1)) XOR SD_CS0 | SD_CS1 #ELSE XOR SD_CS0 @@ -1994,20 +2050,25 @@ SD_DESELECT: ; TRACES. CALL DLY32 ; DELAY FOR FINAL BIT #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + CALL SD_WAITBSY +#ENDIF ; LD A,(SD_OPRVAL) #IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1)) AND ~(SD_CS0 | SD_CS1) #ELSE -#if (SDMODE == SDMODE_EPITX) +#IF (SDMODE == SDMODE_EPITX) OR 7 ; CHAN 7 IS USED FOR DESELECTS #ELSE AND ~SD_CS0 #ENDIF #ENDIF ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS -#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R)) - #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1)) +;;;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R)) +#IF (SD_INVCS) + #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1)) XOR SD_CS0 | SD_CS1 #ELSE XOR SD_CS0 @@ -2037,24 +2098,40 @@ SD_WAITRX: ; #ENDIF ; +#IF (SDMODE == SDMODE_FZ80) +; +; WAIT WHILE FPGA SPI INTERFACE IS BUSY SENDING OR RECEIVING +; +SD_WAITBSY: + PUSH AF + CALL PC_PERIOD ; *DEBUG* + ;;;CALL DLY32 + IN A,(SD_SELSTAT) + BIT 7,A + JR NZ,SD_WAITBSY + ;;;CALL DLY32 + POP AF + RET +#ENDIF +; ; SEND ONE BYTE ; SD_PUT: ; #IF (SDMODE == SDMODE_MT) OUT (SD_WRTR),A -#ELSE +#ENDIF ; - #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) CALL MIRROR ; MSB<-->LSB MIRROR BITS, RESULT IN C CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING OUT0 (SD_TRDR),C ; PUT BYTE IN BUFFER IN0 A,(SD_CNTR) SET 4,A ; SET TRANSMIT ENABLE OUT0 (SD_CNTR),A - #ELSE - - #IF (SDMODE == SDMODE_Z80R) +#ENDIF +; +#IF (SDMODE == SDMODE_Z80R) ; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE ; WHILST THE OTHER PATHS DO ? LD C,A @@ -2090,8 +2167,9 @@ SD_PUT: RLA OUT (SD_IOREG),A OUT (SD_IOCLK),A - #ELSE - +#ENDIF +; +#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO)) #IF (SDMODE == SDMODE_UART) XOR $FF ; DI IS INVERTED ON UART #ENDIF @@ -2110,8 +2188,17 @@ SD_PUT1: DJNZ SD_PUT1 ; REPEAT FOR ALL 8 BITS LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE OUT (SD_OPRREG),A ; LEAVE WITH CLOCK LOW - #ENDIF - #ENDIF +#ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY + OUT (SD_DATA),A ; POST THE VALUE + OUT (SD_ACTION),A ; INITIATE THE WRITE + ;;;CALL SD_WAITBSY + + CALL PC_SPACE ; *DEBUG* + CALL PC_GT ; *DEBUG* + CALL PRTHEXBYTE ; *DEBUG* #ENDIF RET ; DONE ; @@ -2122,8 +2209,9 @@ SD_GET: ; #IF (SDMODE == SDMODE_MT) IN A,(SD_RDTR) -#ELSE - #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#ENDIF +; +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING IN0 A,(SD_CNTR) ; GET CSIO STATUS SET 5,A ; START RECEIVER @@ -2132,8 +2220,9 @@ SD_GET: IN0 A,(SD_TRDR) ; GET RECEIVED BYTE CALL MIRROR ; MSB<-->LSB MIRROR BITS LD A,C ; KEEP RESULT - #ELSE - #IF (SDMODE == SDMODE_Z80R) +#ENDIF +; +#IF (SDMODE == SDMODE_Z80R) ; MUST PRESERVE HL,DE PUSH DE LD A,1 @@ -2180,38 +2269,49 @@ SD_GET: RL E LD A,E POP DE - #ELSE +#ENDIF +; +#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO)) LD B,8 ; RECEIVE 8 BITS (LOOP 8 TIMES) LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE SD_GET1: XOR SD_CLK ; TOGGLE CLOCK OUT (SD_OPRREG),A ; UPDATE CLOCK IN A,(SD_INPREG) ; READ THE DATA WHILE CLOCK IS ACTIVE - #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO)) + #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO)) RLA ; ROTATE INP:7 INTO CF - #ENDIF - #IF (SDMODE == SDMODE_N8) + #ENDIF + #IF (SDMODE == SDMODE_N8) RLA ; ROTATE INP:6 INTO CF RLA ; " - #ENDIF - #IF (SDMODE == SDMODE_UART) + #ENDIF + #IF (SDMODE == SDMODE_UART) RLA ; ROTATE INP:5 INTO CF RLA ; " RLA ; " - #ENDIF - #IF (SDMODE == SDMODE_DSD) + #ENDIF + #IF (SDMODE == SDMODE_DSD) RRA ; ROTATE INP:0 INTO CF - #ENDIF + #ENDIF RL C ; ROTATE CF INTO C:0 LD A,(SD_OPRVAL) ; BACK TO INITIAL VALUES (TOGGLE CLOCK) OUT (SD_OPRREG),A ; DO IT DJNZ SD_GET1 ; REPEAT FOR ALL 8 BITS LD A,C ; GET BYTE RECEIVED INTO A - #IF (SDMODE == SDMODE_UART) + #IF (SDMODE == SDMODE_UART) XOR $FF ; DO IS INVERTED ON UART - #ENDIF - #ENDIF #ENDIF +#ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY + IN A,(SD_ACTION) ; INITIATE READ + CALL SD_WAITBSY ; WAIT FOR DONE + IN A,(SD_DATA) ; GET THE VALUE + ;;;CALL SD_WAITBSY + CALL PC_SPACE ; *DEBUG* + CALL PC_LT ; *DEBUG* + CALL PRTHEXBYTE ; *DEBUG* #ENDIF RET ; diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 50b6ad0c..c64da154 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -222,6 +222,7 @@ SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE) SDMODE_PIO .EQU 11 ; Z80 PIO bitbang SDMODE_Z80R .EQU 12 ; Z80 Retro SDMODE_EPITX .EQU 13 ; Mini ITX Z180 +SDMODE_FZ80 .EQU 14 ; S100 FPGA Z80 ; ; AY SOUND CHIP MODE SELECTIONS ; diff --git a/Source/ver.inc b/Source/ver.inc index 9510c20e..15761e84 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 5 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.5.0-dev.50" +#DEFINE BIOSVER "3.5.0-dev.51" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index ec7a738f..592b3bb4 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 5 rup equ 0 rtp equ 0 biosver macro - db "3.5.0-dev.50" + db "3.5.0-dev.51" endm