Support S100 Z80 FPGA Printer Port
This commit is contained in:
Wayne Warthen
@@ -65,23 +65,14 @@
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;
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#DEFINE BOOT_DEFAULT "Z" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
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;
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#include "cfg_RCZ80.asm"
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#include "Config/RCZ80_std.asm"
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;
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CPUOSC .SET 3686400 ; CPU OSC FREQ IN MHZ
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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;BOOTCON .SET 1 ; BOOT CONSOLE DEVICE
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;
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DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
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;
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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;
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
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SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
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SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
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@@ -95,8 +86,6 @@ SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
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TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
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TMSMODE .SET TMSMODE_COLECO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
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MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
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EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
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VDAEMU_SERKBD .SET 1 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
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;
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AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
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@@ -108,7 +97,3 @@ FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3
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;
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
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PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
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SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
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;
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PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
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@@ -44,28 +44,18 @@
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;
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
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;
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#include "cfg_RCZ80.asm"
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#include "Config/RCZ80_std.asm"
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;
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CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
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INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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;
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FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
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FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES
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;
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DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
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KIOENABLE .SET TRUE ; ENABLE ZILOG KIO SUPPORT
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;
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CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
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CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
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CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS
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;
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UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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;
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
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SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR
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@@ -73,26 +63,3 @@ SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
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SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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;
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TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
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TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
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TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
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MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
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VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
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EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
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VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
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;
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AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
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AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
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SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
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;
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FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
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FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
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;
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
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SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
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IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
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;
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PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
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@@ -1,47 +0,0 @@
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;
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;==================================================================================================
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; SBC SIMH EMULATOR CONFIGURATION
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;==================================================================================================
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;
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
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; YOUR FILE IN THE BUILD PROCESS.
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;
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
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; SETTINGS.
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;
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
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;
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
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; DIRECTORIES ABOVE THIS ONE).
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;
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
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;
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#include "cfg_SBC.asm"
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;
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INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
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;
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HTIMENABLE .SET TRUE ; ENABLE SIMH TIMER SUPPORT
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;
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SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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;
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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;
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SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .SET $6D ; SSER: STATUS PORT
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SSERDATA .SET $68 ; SSER: DATA PORT
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SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
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SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
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SSERORDY .SET %00100000 ; SSER: OUTPUT READY BIT MASK
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SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
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;
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HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
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67
Source/HBIOS/Config/SBC_simh_std.asm
Normal file
67
Source/HBIOS/Config/SBC_simh_std.asm
Normal file
@@ -0,0 +1,67 @@
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;
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;==================================================================================================
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; ROMWBW DEFAULT BUILD SETTINGS FOR N8VEM SBC W/SIMH SUPPORT
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;==================================================================================================
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;
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; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
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; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
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; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
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;
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; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
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;
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; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
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; |
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; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
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; |
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; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
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; |
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; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
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;
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; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
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; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
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; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
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; OVERRIDE THESE SETTINGS AS DESIRED.
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;
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; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
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; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
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; MODIFIED.
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;
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; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
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; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
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; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
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; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
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;
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; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
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; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
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; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
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;
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
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; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
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;
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; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
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; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
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; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
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;
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
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;
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#include "cfg_SBC.asm"
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;
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INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
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;
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HTIMENABLE .SET TRUE ; ENABLE SIMH TIMER SUPPORT
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;
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SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
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;
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UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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;
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SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .SET $6D ; SSER: STATUS PORT
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SSERDATA .SET $68 ; SSER: DATA PORT
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SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
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SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
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SSERORDY .SET %00100000 ; SSER: OUTPUT READY BIT MASK
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SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
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;
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HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
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@@ -343,11 +343,11 @@ PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
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PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
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;
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LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
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LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
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LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
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LPTMODE .SET LPTMODE_S100 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
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LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
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LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
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LPT0BASE .SET $C7 ; LPT 0: REGISTERS BASE ADR
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LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
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;
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PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
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@@ -3686,15 +3686,6 @@ HB_PCINITTBL:
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#IF (ACIAENABLE)
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.DW ACIA_PREINIT
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#ENDIF
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#IF (PIOENABLE)
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.DW PIO_PREINIT
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#ENDIF
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#IF LPTENABLE)
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.DW LPT_PREINIT
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#ENDIF
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#IF (PIO_4P | PIO_ZP)
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.DW PIO_PREINIT
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#ENDIF
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#IF (UFENABLE)
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.DW UF_PREINIT
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#ENDIF
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@@ -3702,6 +3693,12 @@ HB_PCINITTBL:
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.DW TMS_PREINIT
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#ENDIF
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.DW TERM_PREINIT ; ALWAYS DO THIS ONE
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#IF (PIOENABLE)
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.DW PIO_PREINIT
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#ENDIF
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#IF (PIO_4P | PIO_ZP)
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.DW PIO_PREINIT
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#ENDIF
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;
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HB_PCINITTBLLEN .EQU (($ - HB_PCINITTBL) / 2)
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;
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@@ -3773,15 +3770,6 @@ HB_INITTBL:
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#IF (ACIAENABLE)
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.DW ACIA_INIT
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#ENDIF
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#IF (PIOENABLE)
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.DW PIO_INIT
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#ENDIF
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#IF (LPTENABLE)
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.DW LPT_INIT
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#ENDIF
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#IF (PIO_4P | PIO_ZP)
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.DW PIO_INIT
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#ENDIF
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#IF (UFENABLE)
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.DW UF_INIT
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#ENDIF
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@@ -3833,15 +3821,24 @@ HB_INITTBL:
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#IF (FVENABLE)
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.DW FV_INIT
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#ENDIF
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#IF (SCONENABLE)
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.DW SCON_INIT
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#ENDIF
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#IF (LPTENABLE)
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.DW LPT_INIT
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#ENDIF
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#IF (PIOENABLE)
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.DW PIO_INIT
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#ENDIF
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#IF (PIO_4P | PIO_ZP)
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.DW PIO_INIT
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#ENDIF
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#IF (PRPENABLE)
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.DW PRP_INIT
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#ENDIF
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#IF (PPPENABLE)
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.DW PPP_INIT
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#ENDIF
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#IF (SCONENABLE)
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.DW SCON_INIT
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#ENDIF
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#IF (DMAENABLE)
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.DW DMA_INIT
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#ENDIF
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@@ -50,7 +50,7 @@
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;
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; D7 D6 D5 D4 D3 D2 D1 D0
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; +-------+-------+-------+-------+-------+-------+-------+-------+
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; | | | | /ERR | SEL | POUT | BUSY | /ACK |
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; | | | | /ERR | SEL | POUT | BUSY | /ACK |
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; +-------+-------+-------+-------+-------+-------+-------+-------+
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;
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; PORT 2 (OUTPUT):
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@@ -62,40 +62,60 @@
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;
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;==================================================================================================
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;
|
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; PRE-CONSOLE INITIALIZATION - DETECT AND INIT HARDWARE
|
||||
; S100 STYLE INTERFACE:
|
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; - S100 FPGA Z80
|
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;
|
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LPT_PREINIT:
|
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; BASE I/O PORT (OUTPUT):
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;
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; SETUP THE DISPATCH TABLE ENTRIES
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; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST
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; REMAIN DISABLED.
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; D7 D6 D5 D4 D3 D2 D1 D0
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; +-------+-------+-------+-------+-------+-------+-------+-------+
|
||||
; | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 |
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; +-------+-------+-------+-------+-------+-------+-------+-------+
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||||
;
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; STATUS PORT (INPUT, BASE I/O - 1):
|
||||
;
|
||||
; D7 D6 D5 D4 D3 D2 D1 D0
|
||||
; +-------+-------+-------+-------+-------+-------+-------+-------+
|
||||
; | | | | | | | BUSY | /ACK |
|
||||
; +-------+-------+-------+-------+-------+-------+-------+-------+
|
||||
;
|
||||
; CONTROL PORT (OUTPUT, BASE I/O - 1):
|
||||
;
|
||||
; D7 D6 D5 D4 D3 D2 D1 D0
|
||||
; +-------+-------+-------+-------+-------+-------+-------+-------+
|
||||
; | | | | | | | | /STB |
|
||||
; +-------+-------+-------+-------+-------+-------+-------+-------+
|
||||
;
|
||||
;==================================================================================================
|
||||
;
|
||||
LPT_INIT:
|
||||
LD B,LPT_CFGCNT ; LOOP CONTROL
|
||||
XOR A ; ZERO TO ACCUM
|
||||
LD (LPT_DEV),A ; CURRENT DEVICE NUMBER
|
||||
LD IY,LPT_CFG ; POINT TO START OF CFG TABLE
|
||||
LPT_PREINIT0:
|
||||
LPT_INIT0:
|
||||
PUSH BC ; SAVE LOOP CONTROL
|
||||
CALL LPT_INITUNIT ; HAND OFF TO UNIT INIT CODE
|
||||
POP BC ; RESTORE LOOP CONTROL
|
||||
;
|
||||
LD A,(IY+1) ; GET THE LPT TYPE DETECTED
|
||||
OR A ; SET FLAGS
|
||||
JR Z,LPT_PREINIT2 ; SKIP IT IF NOTHING FOUND
|
||||
JR Z,LPT_INIT2 ; SKIP IT IF NOTHING FOUND
|
||||
;
|
||||
PUSH BC ; SAVE LOOP CONTROL
|
||||
PUSH IY ; CFG ENTRY ADDRESS
|
||||
POP DE ; ... TO DE
|
||||
LD BC,LPT_FNTBL ; BC := FUNCTION TABLE ADDRESS
|
||||
CALL NZ,CIO_ADDENT ; ADD ENTRY IF LPT FOUND, BC:DE
|
||||
CALL LPT_PRTCFG ; PRINT IF NOT ZERO
|
||||
POP BC ; RESTORE LOOP CONTROL
|
||||
;
|
||||
LPT_PREINIT2:
|
||||
LPT_INIT2:
|
||||
LD DE,LPT_CFGSIZ ; SIZE OF CFG ENTRY
|
||||
ADD IY,DE ; BUMP IY TO NEXT ENTRY
|
||||
DJNZ LPT_PREINIT0 ; LOOP UNTIL DONE
|
||||
DJNZ LPT_INIT0 ; LOOP UNTIL DONE
|
||||
;
|
||||
LPT_PREINIT3:
|
||||
LPT_INIT3:
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; AND RETURN
|
||||
;
|
||||
@@ -119,24 +139,6 @@ LPT_INITUNIT:
|
||||
; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
|
||||
JP LPT_INITDEVX ; IMPLEMENT IT AND RETURN
|
||||
;
|
||||
;
|
||||
;
|
||||
LPT_INIT:
|
||||
LD B,LPT_CFGCNT ; COUNT OF POSSIBLE LPT UNITS
|
||||
LD IY,LPT_CFG ; POINT TO START OF CFG TABLE
|
||||
LPT_INIT1:
|
||||
PUSH BC ; SAVE LOOP CONTROL
|
||||
LD A,(IY+1) ; GET LPT TYPE
|
||||
OR A ; SET FLAGS
|
||||
CALL NZ,LPT_PRTCFG ; PRINT IF NOT ZERO
|
||||
POP BC ; RESTORE LOOP CONTROL
|
||||
LD DE,LPT_CFGSIZ ; SIZE OF CFG ENTRY
|
||||
ADD IY,DE ; BUMP IY TO NEXT ENTRY
|
||||
DJNZ LPT_INIT1 ; LOOP TILL DONE
|
||||
;
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; DONE
|
||||
;
|
||||
; DRIVER FUNCTION TABLE
|
||||
;
|
||||
LPT_FNTBL:
|
||||
@@ -173,8 +175,16 @@ LPT_OUT:
|
||||
#IF (LPTMODE == LPTMODE_MG014)
|
||||
LD A,%00000100 ; SELECT & STROBE, LED OFF
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
LD A,%00000000 ; STROBE
|
||||
#ENDIF
|
||||
#IF ((LPTMODE == LPTMODE_SPP) | (LPTMODE == LPTMODE_MG014))
|
||||
INC C ; PUT CONTROL PORT IN C
|
||||
INC C
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
DEC C ; PUT CONTROL PORT IN C
|
||||
#ENDIF
|
||||
OUT (C),A ; OUTPUT DATA TO PORT
|
||||
CALL DELAY
|
||||
#IF (LPTMODE == LPTMODE_SPP)
|
||||
@@ -182,6 +192,9 @@ LPT_OUT:
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_MG014)
|
||||
LD A,%00000101 ; SELECT, LED OFF
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
LD A,%11111111 ; STROBE
|
||||
#ENDIF
|
||||
OUT (C),A ; OUTPUT DATA TO PORT
|
||||
CALL DELAY
|
||||
@@ -199,7 +212,12 @@ LPT_IST:
|
||||
;
|
||||
LPT_OST:
|
||||
LD C,(IY+3) ; BASE PORT
|
||||
#IF ((LPTMODE == LPTMODE_SPP) | (LPTMODE == LPTMODE_MG014))
|
||||
INC C ; SELECT STATUS PORT
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
DEC C ; SELECT STATUS PORT
|
||||
#ENDIF
|
||||
IN A,(C) ; GET STATUS INFO
|
||||
#IF (LPTMODE == LPTMODE_SPP)
|
||||
AND %10000000 ; ISOLATE /BUSY
|
||||
@@ -256,6 +274,14 @@ LPT_INITDEVX:
|
||||
RET ; RETURN
|
||||
#ENDIF
|
||||
;
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
LD C,(IY+3) ; BASE PORT
|
||||
DEC C ; DEC TO CONTROL PORT
|
||||
LD A,$FF ; INIT VALUE
|
||||
OUT (C),A ; DO IT
|
||||
RET ; RETURN
|
||||
#ENDIF
|
||||
;
|
||||
;
|
||||
;
|
||||
LPT_QUERY:
|
||||
@@ -361,6 +387,13 @@ LPT_DETECT1:
|
||||
RET ; DONE
|
||||
#ENDIF
|
||||
;
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
LPT_DETECT:
|
||||
; PORT ALWAYS EXISTS ON FPGA
|
||||
LD A,LPTMODE_S100 ; RETURN CHIP TYPE
|
||||
RET ; DONE
|
||||
#ENDIF
|
||||
;
|
||||
;
|
||||
;
|
||||
LPT_PRTCFG:
|
||||
@@ -400,10 +433,12 @@ LPT_TYPE_MAP:
|
||||
.DW LPT_STR_NONE
|
||||
.DW LPT_STR_SPP
|
||||
.DW LPT_STR_MG014
|
||||
.DW LPT_STR_S100
|
||||
;
|
||||
LPT_STR_NONE .DB "<NOT PRESENT>$"
|
||||
LPT_STR_SPP .DB "SPP$"
|
||||
LPT_STR_MG014 .DB "MG014$"
|
||||
LPT_STR_S100 .DB "S100$"
|
||||
;
|
||||
; WORKING VARIABLES
|
||||
;
|
||||
@@ -427,6 +462,9 @@ LPT0_CFG:
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_MG014)
|
||||
DEVECHO "MG014"
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
DEVECHO "S100"
|
||||
#ENDIF
|
||||
DEVECHO ", IO="
|
||||
DEVECHO LPT0BASE
|
||||
@@ -450,6 +488,9 @@ LPT1_CFG:
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_MG014)
|
||||
DEVECHO "MG014"
|
||||
#ENDIF
|
||||
#IF (LPTMODE == LPTMODE_S100)
|
||||
DEVECHO "S100"
|
||||
#ENDIF
|
||||
DEVECHO ", IO="
|
||||
DEVECHO LPT1BASE
|
||||
|
||||
@@ -282,6 +282,7 @@ GDCMODE_RPH .EQU 2 ; RPH GDC
|
||||
LPTMODE_NONE .EQU 0 ; NONE
|
||||
LPTMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP)
|
||||
LPTMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE
|
||||
LPTMODE_S100 .EQU 3 ; S100 Z80 FPGA BUILT-IN PRINTER PORT
|
||||
;
|
||||
; PPA DRIVER MODE SELECTIONS
|
||||
;
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
#DEFINE RMN 5
|
||||
#DEFINE RUP 0
|
||||
#DEFINE RTP 0
|
||||
#DEFINE BIOSVER "3.5.0-dev.78"
|
||||
#DEFINE BIOSVER "3.5.0-dev.79"
|
||||
#define rmj RMJ
|
||||
#define rmn RMN
|
||||
#define rup RUP
|
||||
|
||||
@@ -3,5 +3,5 @@ rmn equ 5
|
||||
rup equ 0
|
||||
rtp equ 0
|
||||
biosver macro
|
||||
db "3.5.0-dev.78"
|
||||
db "3.5.0-dev.79"
|
||||
endm
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
@echo off
|
||||
set ROM=..\..\Binary\SBC_simh.rom
|
||||
set ROM=..\..\Binary\SBC_simh_std.rom
|
||||
if not "%1"=="" set ROM=..\..\Binary\%1.rom
|
||||
if not exist %ROM% goto romerr
|
||||
:: start C:\Users\WWarthen\Bin\putty.exe -load "SIMH Telnet"
|
||||
|
||||
Reference in New Issue
Block a user